Boundary Scan
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Objectives History Family of 1149 Architecture Bus Protocol Boundary scan cell TAP controller Instruction set Boundary Scan Description Language
Boundary Scan .1
Objectives
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Standards for board level testing; can be used to test 1. chips 2. chip interconnections 3. modules 4. module interconnections 5. subsystems 6. systems 7. Multi-Chip Modules
Boundary Scan .2
History
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1985: Joint European Test Action Group (JETAG, Philips) 1986 VHSIC Element-Test & Maintenance (ETM) bus standard (IBM et al.) VHSIC Test & Maintenance (TM) Bus structure (IBM et al.) 1988: Joint Test Action Group (JTAG) proposed Boundary Scan Standard 1990 Boundary Scan approved as IEEE Std. 1149.1-1990 Boundary Scan Description Language (BSDL) proposed by HP 1993: 1149.1a-1993 approved to replace 1149.1-1990 1994: 1149.1b BSDL approved 1995: 1149.5 approved 1999: 1149.4 approved
Boundary Scan .3
Overview of P1149 Family
Number
1149.1
Title
Status
Testing of digital chips and Std. 1149.1-1990 interconnections between Std. 1149.1a-1993 chips Std. 1149.1b-1994 (BSDL) Extended Digital Serial Interface Direct Access Testability interface Mixed-Signal Test Bus Standard Module Test and Maintenance (MTM) Bus Protocal Unification Near completion Discontinue Std. 1149.4-1999 Std. 1149.5-1995
1149.2 1149.3 1149.4 1149.5
1149
Not yet started
Boundary Scan .4
1149.1-1990, 1149.1a-1993
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Testing of chips and interconnections on board For digital circuits Most successful among 1149 family Widely used in industry, e.g., in advanced CPU, HDTV, satellite system, etc.
Boundary Scan .5
Basic Chip Architecture for 1149.1
Boundary Scan Cell Boundary Scan Path
I/O Pins
Internal Logic
I/O Pins
Sin
Sout
M U X
TDI
Miscellaneous Registers
Instruction Register
TDO
TRST* TMS
Bypass Register
TAP Controller
TCK
Boundary Scan .6
Boundary Scan Circuitry in a Chip
Data Registers
Design-Spec. Reg. Device-ID Reg.
TDO TDI TRST* TMS TCK
BS Register
M U X
0 1
1D C1 EN
T A P
T A P C
Bypass Reg.(1 bit)
3 3
ClockDR ShiftDR UpdateDR Reset* ClockIR ShiftIR UpdateIR
IR decode
Instruction Register
Select TCK Enable
Boundary Scan .7
Hardware Components of 1149.1
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TAP (Test Access Port) :
TMS, TCK, TDI, TDO, TRST* (optional)
TAP Controller :
A finite state machine with 16 states Input : TCK, TMS Output : 9 or 10 signals included ClockDR, UpdateDR, ShiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK and the optional TRST*.
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IR (Instruction Register) TDR (Test Data Registers) :
Mandatory: Boundary scan register and Bypass register Optional: Device-ID register, Design-Specific registers, etc.
Boundary Scan .8
Bus Protocol
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Signals
TDI: Test Data In TDO: Test Data Out TMS: Test Mode Selection TCK: Test Clock TRST* (optional): Test Reset
Basic operations
Instruction sent (serially) over TDI into instruction register. Selected test circuitry configured to respond to instruction. Test instruction executed. Test results shifted out through TDO; new test data on TDI may be shifted in at the same time.
Boundary Scan .9
A Typical Boundary Scan Cell
SOUT
IN
0 1 0 1 SIN
M U X
M U X
OUT
ID
QA
ID
QB
Mode_Control
shiftDR ClockDR
UpdateDR
Operation modes:
1. Normal: Mode_Control=0;
IN->OUT
2. Scan: ShiftDR=1,ClockDR;
TDI->...->SIN->SOUT->...TDO
3. Capture: ShiftDR=0, ClcokDR;
IN-> QA, OUT driven by IN or QB
4. Update: Mode_Control=1, UpdateDR;
QA->OUT
Boundary Scan .10
State Diagram of TAP Controller
Control of data registers 1 0 Test-Logic-Reset Control of instruction registers
0
Run-test/idle
1 1 1
Select-DR-Scan
1 1
Select-IR-Scan
0
Capture-DR
0
Capture-IR
0
Shift-DR Shift-IR
0 0 1 1
Exit1-IR
1
Exit1-DR
1 0 1
0
Pause-DR
0
Pause-IR
1
Exit2-DR
0 0
1
Exit2-IR
1
Update-DR
1
Update-IR
Boundary Scan .11
States of TAP Controller
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Test-Logic-Reset: normal mode Run-Test/Idle: wait for internal test such as BIST Select-DR-Scan: initiate a data-scan sequence Capture-DR: load test data in parallel Shift-DR: load test data in series Exit1-DR: finish phase-1 shifting of data Pause-DR: temporarily hold the scan operation (allow the bus master to reload data) Exit2-DR: finish phase-2 shifting of data Update-DR: parallel load from associated shift registers
Boundary Scan .12
Timing of instruction scan
TCK TMS
Test-LogicReset
1
Select-DRScan Run-test/ Idle
1
Select-IRScan
0 0 0
Capture-IR Shift-IR
1
Exit -IR 1
0 0 0 0
Pause-IR
1
Exit -IR 2
0 0
0 0
Shift-IR
1 1
Update-IR Exit -IR 1
0 0
0 0
Run-Test/Idle
Control State
TDI Data input to IR IR shift-register Parallel output of IR Data input to TDR TDR shift-register Parallel output of TDR Register selected TDO enable TDO = Don't care or undefined Inactive Active Instruction register Inactive Active Inactive Old data IDCODE New instruction
Boundary Scan .13
Timing of data scan
TCK TMS
0 0 0 0 1
SelectDR-Scan Run-Test/Idle
0 0 0 0 1 0 0 0 0 1 0 0 0 0
Capture-DR Pause-DR Exit -DR Exit -DR Shift-DR Shift-DR 1 2
1 1 0 0
Update-DR Exit -DR 1
0
SelectDR-Scan Run-Test/Idle
1 1
SelectIR-Scan Test-LogicReset
Control State
TDI Data input to IR IR shift-register Parallel output of IR Data input to TDR TDR shift-register Parallel output of TDR Instruction Register TDO enable TDO = Don't care or undefined Inactive Active Old data Test data register Inactive Active Inactive New data Instruction IDCODE
Boundary Scan .14
Instruction Set
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EXTEST:
Test interconnection between chips of board
SAMPLE/PRELOAD:
Sample and shift out data or shift in data only
BYPASS:
Bypass data through a chip
Optional :
INTEST, RUNBIST, CLAMP, IDCODE, USERCODE, HIGH-Z, etc.
Boundary Scan .15
EXTEST
Chip1 Internal Logic
TDI Registers
TAP Controller
0
Chip2 Internal Logic
TDO TDI Registers
TAP Controller
1. Shift-DR (Chip1)
TDO
2. Update-DR (Chip1) 3. Capture-DR (Chip2)
TDI
Internal Logic
Registers
TAP Controller
Internal Logic
Registers
TAP Controller
TDO
TDI
TDO
4. Shift-DR (Chip2)
TDI
Internal Logic
Registers
TAP Controller
Internal Logic
Registers
TAP Controller
TDO
TDI
TDO
Boundary Scan .16
EXTEST
Input
1. Shift-DR (Chip1)
Input
QA TDI
QB
M U X
Internal Logic QA TDO QB
M U X
Output
2. Update-DR (Chip1)
Input from Chip1
QA TDI
QB
M U X
Internal Logic QA TDO QB
M U X
Output to Chip2
3. Capture-DR (Chip2)
QA TDI
QB
M U X
Internal Logic QA TDO QB
M U X
Output
4. Shift-DR (Chip2)
Input M U X Internal Logic QA TDO QB M U X Output
QA TDI
QB
Boundary Scan .17
SAMPLE/PRELOAD
Input
SAMPLE
QA QB
M U X
Internal Logic
M U X QA QB
Output
TDI
TDO
Input
PRELOAD
QA QB
M U X
Internal Logic
M U X QA QB TDO
Output
TDI
Sample/Preload is one instruction that allows 1. Sample and shift (out) or 2. Shift (in) only
Boundary Scan .18
BYPASS
Internal Logic
TDI
Bypass Register (1 bit)
TDO
TAP Controller
Boundary Scan .19
INTEST
0
1.Shift-DR
TDI
Internal Logic
Registers
TAP Controller
2.Update-DR
TDO TDI
Internal Logic
Registers
TAP Controller
TDO
3.Capture-DR
TDI
Internal Logic
Registers
TAP Controller
4. Shift-DR
TDO TDI
Internal Logic
Registers
TAP Controller
TDO
Boundary Scan .20
INTEST
Input
1. Shift-DR
QA TDI
QB
M U X
Internal Logic QA TDO QB
M U X
Output
Input
2. Update-DR
QA TDI Input
QB
M U X
Internal Logic QA TDO QB
M U X
Output
3. Capture-DR
QA TDI
QB
M U X
Internal Logic QA TDO QB
M U X
Output
Input
4. Shift-DR
QA TDI
QB
M U X
Internal Logic QA TDO QB
M U X
Output
Boundary Scan .21
Test Bus Configuration
Application chips
TDI TCK TMS TDO TDI TCK TMS TDO
Application chips
TDI TCK TMS TDO TDI TCK TMS TDO
#1
#1
Bus master TD 0 TDI TMS TCK
Bus master
TD0 TDI TMS1 TMS2 TMSN TCK
#2
#2
TDI TCK TMS TDO
#N
TDI TCK TMS TDO
#N
Ring configuration
Star configuration
Boundary Scan .22
A Printed Circuit Board with 1149.1
(Ring configuration, test controller on board)
Chip1 Chip2
Internal Logic
Registers
TAP Controller
M U X
Internal Logic
Registers
TAP Controller
M U X
TAP Controller
M U X
Registers
TDI
MASTER Controller
TDO TMS TCK
Internal Logic
Chip3
Boundary Scan .23
Boundary Scan Description Language (BSDL)
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Now the IEEE 1149.1b standard Purposes:
To provide a standard description language for boundary scan devices. To simplify the design work for boundary scan---automated synthesis is possible. To promote consistency throughout ASIC designers, device manufacturers, foundries, test developers and ATE manufacturers. For easy incorporation into software tools for test generation, analysis and failure diagnosis. To reduce possibility of human error when employing boundary scan in a design.
Boundary Scan .24
Features of BSDL
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BSDL describes the testability features of boundary scan devices which are compatible with 1149.1. It's a subset of VHDL. Elements of a design which are absolutely mandatory for the 1149.1 and system-logic are not included in the language.
Examples: BYPASS register, TAP controller, etc.
BSDL may be used in a full or in a partial VHDL environment.
Boundary Scan .25
A Complete Example
12 D6 D5 D4 D3 D2 D1 CLK C O R E L O G I C Q6 Q5 Q4 Q3 Q2 Q1 D6 13 D5 14 D4 15 D3 16 D2 17 D1 1 CLK 12
TAP Controller
11 6 7 8 9 10 11 C O R E L O G I C 0 10 1 2 3 7 4 6 5 Q1 Q2 9 8 Q4 Q3 Q5 Q6
2 3 5 4 TDI TCK TMS TDO Boundary Scan .26
Entity
entity demo is generic(PHYSICAL_PIN_MAP:string:="UNDEFINED"); port(CLK:in,bit;Q:out,bit_vector(1 to 6);D:in,bit_vector(1 to 6); GND,VCC:linkage,bit;TDO:out,bit;TMS,TCK,TDI:in,bit); use STD_1149_1_1990.all; attribute PIN_MAP of demo:entity is PHYSICAL_PIN_MAP; constant DW_PACKAGE:PIN_MAP_STRING:="CLK:1," & "Q(6,7,8,9,10,11),D(12,13,14,15,16,17),GND:18,VCC:19," & "TDO:5,TMS:4,TCK:3,TDI:2"; attribute TAP_SCAN_IN of TDI:signal is true; attribute TAP_SCAN_MODE of TMS:signal is true; attribute TAP_SCAN_OUT of TDO:signal is true; attribute TAP_SCAN_CLOCK of TCK:signal is (20e6,BOTH); attribute INSTRUCTION_LENGTH of demo:entity is 4; attribute INSTRUCTION_OPCODE of demo:entity is "BYPASS (11111),"& "EXTEST(0000)," & "SAMPLE(1100,1010)," & "INTEST(1010)";
Boundary Scan .27
Entity (Cont.)
attribute INSTRUCTION_CAPTURE of demo:entity is "0101"; attribute BOUNDARY_CELLS of demo:entity is "BC_1"; attribute BOUNDARY_LENGTH of demo:entity is 12; attribute BOUNDARY_REGISTER of demo:entity is -- num cell port function safe [ccell disval rslt] "12 (BC_1,CLK,input,X)," & "11 (BC_1,D(1),input,X)," & "10 (BC_1,D(2),input,X)," & "9 (BC_1,D(3),input,X)," & "8 (BC_1,D(4),input,X)," & "7 (BC_1,D(5),input,X)," & "6 (BC_1,D(6),input,X)," & "5 (BC_1,Q(1),output3,X,000,1,Z)," & "4 (BC_1,Q(2),output3,X,000,1,Z)," & "3 (BC_1,Q(3),output3,X,000,1,Z)," & "2 (BC_1,Q(4),output3,X,005,1,Z)," & "1 (BC_1,Q(5),output3,X,005,1,Z)," & "0 (BC_1,Q(6),output3,X,005,1,Z)"; end demo;
Boundary Scan .28
Package
package STD_1149_1_1990 is attribute PIN_MAP:string; subtype PIN_MAP_STRING is string; type CLOCK_LEVEL is (LOW, BOTH); type CLOCK_INFO is record FREQ:real; LEVEL:CLOCK_LEVEL; end record; attribute TAP_SCAN_IN: boolean; attribute TAP_SCAN_OUT:boolean; attribute TAP_SCAN_CLOCK:CLOCK_INFO; attribute TAP_SCAN_MODE:boolean; attribute TAP_SCAN_RESET:boolean; attribute INSTRUCTION_LENGTH:integer; attribute INSTRUCTION_OPCODE:string; attribute INSTRUCTION_CAPTURE:string;
Boundary Scan .29
Package (Cont.)
type ID_BITS is ('0', '1', 'X'); type ID_STRING is array (31 downto 0) of ID_BIT attribute REGISTER_ACCESS:string type BSCAN_INST is (EXTEST, SAMPLE, INTEST,RUNBIST); type CELL_TYPE is (INPUT, INTERNAL, CLOCK, CONTROL, OUTPUT2, OUTPUT3, BIDIR_IN, BIDIR_OUT); type CAP_DATA is (PI, PO, UPD, CAP, X, ZRRO, ONE); type CELL_DATA is record CT:CELL_TYPE; I:BSCAN_INST; CD:CAP_DATA; end record; type CELL_INFO is array(positive range<>) of CELL_DATA; constant BC_1:CELL_INFO; attribute BOUNDARY_CELLS:string; attribute BOUNDARY_LENGTH:integer; attribute BOUNDARY_REGISTER:string; attribute DESIGN_WARING:string; end STD_1149_1_1990;
Boundary Scan .30
Package Body
constant BC_1:CELL_INFO:=( (INPUT,EXTEST,PI), (OUTPUT2,EXTEST,PI), (INPUT,SAMPLE,PI), (OUTPUT2,SAMPLE,PI), (INPUT,INTEST,PI). (OUTPUT2,INTEST,PI), (OUTPUT3,EXTEST,PI), (INTERNAL,EXTEST,PI), (OUTPUT3, SAMPLE,PI), (INTERNAL,SAMPLE,PI), (OUTPUT3, INTEST,PI), (INTERNAL,INTEST,PI), (CONTROL,EXTEST,PI),(CONTROL,EXTEST,PI), (CONTROL,SAMPLE,PI),(CONTROL,SAMPLE,PI), (CONTROL,INTEST,PI),(CONTROL,INTEST,PI) );
Boundary Scan .31
