“th prio Figs — / 19 loz |2eck Properties of Silicon and Gallium Arsenide Property Silicon Gallium Arsenide UNSH Cota src Diamond Zincblende Lattice constant (A) 5.431 5.646 a Distance between neighboring atoms (A) 236 246 py Engines M0 ‘Atoms or molecules/em? 5x10? 2.21 x 107 d Density (g/cm?) 2.328 5.32 Melting point C) i412 1238 ‘Thermal expansion coefficient (300 °K) 2.6 x 10-* 6.86 x 10-* Thermal conductivity (W/cm-°C) AS 0.46 Energy gap (eV) Lu 1.435 Relative permittivity ng Ba Breakdown field strength (V/jim) =30 =40 Intrinsic carrier concentration, cm~° (300 °K) 1.45 x 10° Bx 10 Effective density of states Valence band (cm=*) 1.04 x 10 7x 10% Conduction band (cm~*) 2.8 x 10" 4.7 x 10'7VLSI FABRICATION PRINCIPLES Silicon and Gallium Arsenide Cassette ports; Second Edition SORAB K. GHANDHI Rensselaer Polytechnic Institute Troy, New York ges sak saz gis aie gas ®) A Wiley-Interscience Publication JOHN WILEY & SONS, INC. New York / Chichester / Brisbane / Toronto / SingaporeThis tex is printed on acid-free pap. Copytight © 1994 by John Wiley & Sons, fc All rights reserved. Published simultaneously in Canada Reproduction or transition of any part of this work beyont {hat permite by Section 107 or 108 of the 1976 United Stes Copyright Act without the permission ofthe eopycight owner is unlawful, Requests for pemission or forther information should be adatesed 1 the Permissions Depart John Wiley & Sons, In, 605 Thin! Avenus, New York, NY. 1w1s8-0012, Library of Congress Cataloging in Publication Data: Ghandi, Sorsb Khushi, 1928 VLSI fabrication principles silicon and gallium arsenide / Srab K. Ghandhi—Rev, efi, 2nd ed] Pp em Includes bibliographical references and index, ISBN 0.471-88005-8 (alk. paper) 1, Integrated citeits—Very large scale integration. 2. Silicon. 3. Gallium arsenide. 1. Tite ‘TK7S740873 1904 o21.3815'2—de20 9340716 Printed inthe United States of America 9876545 To my wife, Cecille and my sons, Khushro, Rustom, and Behram for making it all worthwhilePREFACE TO THE SECOND EDITION It is now 10 years since the publication of the first edition of this volume. In its Preface, I had noted that “The aim of this book is to provide graduate stu- dents and practicing engineers with a body of knowledge of VLSI fabrication principles that will not only bring them up-to-date, but also allow them to stay up-to-date in the field.” This is still the primary focus of the second edition; in fact, it is even more important now because of the proliferation of new tech: niques and technologies that are being brought to bear on this field. Thave used this book in teaching courses to both graduate students and prac- ticing engineers, and found that the best way to achieve this goal is to emphasize the basic principles governing the direction of developments in this field. Con- sequently, this approach has been carried over to this edition, as has the overall organization of its chapters. Within each chapter, however, the reader will find that many changes have been made to reflect advances that have occurred in each area. For example, developments in the areas of Deposited Films and Etching have been very rapid, with a proliferation of new techniques on an almost daily basis. This chapter has been expanded to reflect this growth; moreover, I have attempted to bring some order to this apparently chaotic situation by emphi sizing the basic principles underlying these developments, Thus. many new technological developments have been described but always with an emphasis on their underlying physical principles. In areas such as Diffusion and Epitaxy, for example, our understanding of the basic physical principles has advanced to the point where the technology is on a considerably firmer footing than it was 10 years ago. Here, the material hhas been completely rewritten to reflect this understanding. vilPREFACE TO THE SECOND EDITION My experience in teaching this material has brought about many changes in the order of its presentation. Often, what appeared logical at first writing did not come across that way in the classroom environment. I have attempted to correct this problem and made many changes, based on my teaching experi ence since the publication of the first edition. The list of references with each chapter has been greatly expanded and updated to allow the interested reader to Probe further into the topics which have been covered. Finally, in response to ‘many requests from colleagues in industry, tables of important data have been collected at the end of each chapter for ready reference, It is almost impossible to provide a comprehensive list of acknowledgments for a book that is based on more than 40 years of interaction with colleagues in the area of solid state. Certainly, all of those singled out for thanks in the first edition require a redoubling of these thanks, since they have been of continuing help to me. My special thanks go to Dr. Krishna K. Parat for his critical reading of many sections of this book, and to Professor Ishwara B. Bhat for many stim- ulating discussions, as well as for his help in solving most of the problems that are provided at the end of each chapter. Ms. Priscilla Magilligan deserves my thanks for doing a superb job of typing this manuscript and its interminable revisions, using an arcane computer software package that was far beyond my comprehension, ‘Sonas K. Guanos Niskayuna, New York January 1994 PREFACE TO THE FIRST EDITION ‘This book discusses the basic principles underlying the fabrication of semicon- ductor devices and integrated circuits. Its emphasis is on processes that are espe- cially useful for Very Large Scale Integration (VLSD schemes; however, many processes used for discrete devices and medium-density integrated circuits have also been included, since they are the precursors of VLSI technology. “The aim of this book is to provide graduate students and practicing engineers with a body of knowledge of VLSI fabrication principles that will not only bring them up-to-date, but also allow them to stay up-to-date in this field. This is difficult to do in as fast-moving an area as VLSI. I believe that an effective approach is to concentrate on a broad background in the area, and to emphasize the basic principles governing the direction of developments in this field. As fa practicing engineer for 13 years, and a professor and consultant to industry for an additional 19, 1 believe that this approach will best serve the long-term needs of workers in the area, “My experience as an author has convinced me that the above approach is the correct one for this book. In 1968 I wrote a book on microelectronics® using this approach. It has been a source of deep satisfaction to me that, even after 14 years, itis still considered to be a well-regarded “honest” book, notwithstanding ‘the fact that many new technologies have become firmly established since. The reason for this, I believe, was the book's emphasis on basic principles rather than on the latest technological details. VLSI Fabrication Principles was written with this idea in mind. Unlike my last volume, however, this book emphasizes fabrication principles. I have “The Theory and Practice of Microelectronics, Published by John Wiley and Sons, New York. ixPREFACE TO THE FIRST EDITION avoided discussions of the physics of device operation as much as possible, since this topic is already covered in excellent books® in the area. Even so, this new volume is about one and one-half times the length of the previous one, because of the many advances in the field, This book is about both elemental and compound semiconductors. Silicon is clearly the most widely used material today, and will remain the mainstay of the industry, However, many new materials (gallium arsenide is only one) are under investigation because of their unique capabilities. Gallium arsenide has already advanced technologically to the point where it is being used 10 make many unique devices and integrated circuits. In terms of both research and advanced development, its exploitation represents the most rapidly growing. segment of solid state technology today. 7 From an academic viewpoint, believe that a student's valuable time ina uni versity can be put to the best use by acquiring the broadest base of knowledge in the field, rather than by premature specialization in any one specific area of technology. This is particularly true because many of the new problems being uncovered by workers in the latest silicon technology bear a strong resemblance to problems encountered many years ago by workers in gallium arsenide. For example, the anomalous behavior of arsenic diffusion in silicon, which was first explained in 1975, is governed by the same body of mathematics that describes the diffusion of zinc in gallium arsenide (1963). It is my hope, then, that stu- dents of this volume will acquire a broad perspective on the subject, and be flexible enough to work in any area of semiconductor fabrication technology, as the need arises. This book emphasizes the basic processes that are involved in integrated circuit fabrication. Each chapter discusses principles common to all semicon- ductors, with separate sections where necessary to discuss problems and char- acteristics that are unique to silicon or gallium arsenide. ‘The emphasis is on VLSI techniques; however, in order not to be unduly restrictive, I have also considered techniques that apply to the fabrication of medium and large-scale imegrated circuits, as well as of discrete devices. Chapter 1 describes basic Material Properties, especially those that are important in device processing. This is followed by Chapter 2 on Phase Dia- ‘grams, which outlines a valuable (ool for investigating the behavior of combi- nations of two or more materials in intimate contact, when subjected to heat treatments. Chapter 3 describes basic aspects of the Growth of starting mate- rials, and limitations imposed by the different growth technologies. Chapters 4-6 describe the “anchor” technologies of Diffusion, Epitaxy, and Jon Implantation. Emphasis has been placed on these topics, because they are the Key fabrication processes used today. Again, the stress is on the basic prin- ciples underlying these processes, rather than on the very latest development Wiley & Sons, New York (1981). ah e PREFACE TO THE FIRST EDITION =— XI in each area, Of necessity, some very new techniques have been omitted, since their eventual role in device fabrication is not yet clear uusses Native Oxide Films, which are grown out of the semi- conductor. These play a key role in control of the device surface and thus in its long-term stability. Here, the emphasis is on accepted technologies, and on their limitations. ‘Deposited Films are discussed in Chapter 8. The large variety of available choices prevents a detailed discussion of every combination, Consequently, these films have been grouped on a functional basis—films for protection and masking, films for interconnections, films for ohmic contacts, and films for ‘Schottky devices. I hope that this approach will provide some cohesiveness to this topic. Chapter 9 outlines Etching and Cleaning processes. Both wet and dry pro- cesses are considered, with special emphasis on the latter, since they represent 4 clear direction for VLSI fabrication Chapter 10 outlines the basic principles of Lithographic Processes. The emphasis here is on photolithography and electron beam lithography. However, promising approaches such as X-ray lithography are considered as well. A dis- ‘cussion of the principles underlying the various resist systems is also included. Chapter 11, on Device and Circuit Fabrication, is a synthesis of all of the preceding chapters, leading to the fabrication of complete microcircuits. No attempt is made to describe the many combinations of process steps that can be used for this purpose. Instead, basic techniques common to all VLSI schemes are first considered, These include isolation, self-alignment, local oxidation, and planarization. This is followed by a detailed discussion of microcircuits based on the metal-oxide-semiconductor, metal-Schottky gate-semiconductor, and bipolar junction transistor devices. An extensive reference list is provide to guide the reader to many of the important variations that are being considered at the present time, but have not been fully evaluated in terms of performance and cost. Finally, a short Appendix provides the necessary mathematical back- ‘ground for the chapter on diffusion. ‘Wherever possible, problems have been provided, many of which deal with practical situations and are intended to bring out points not covered in detail in the text. In addition, there are extensive references at the end of each chapter. No attempt has been made to use them to give credit to persons who did the original work; rather, their choice has been based on the need to give the reader means for further study. A book such as this takes many years to write, and springs from many sources of inspiration and encouragement. It would indeed be difficult to single out all of these for acknowledgment. I know, however, that my primary thanks must go to my many graduate students who provide me with much intellec: tual stimulation and challenge. They have been exposed to this material, in one form or another, over the past five years. Their many penetrating questions have often led to rethinking and reworking the text over these years.xii PREFACE TO THE FIRST EDITION Next, I must acknowledge the encouragement and understanding T have received from Dr. Donald Feucht and John Benner of the Solar Energy Research Institute, Their generous support of funded research in this area has provided continuing forum for the development of new ideas and new understanding, which have been incorporated into this book. Discussions with many friends in industry, especially those at the Radio Corporation of America and the Gen- eral Electric Company, have added much to the relevance of this book, and are zratefully acknowledged. A number of my friends and colleagues have been kind enough to read and comment upon chapters of this book in their areas of specialization. ‘These include Drs. B. Jayant Baliga, Ronald J. Gutmann, Shinji Okazaki, Kenneth Rose, Shambhu K. Shastry, and David S. Yaney. My wife and family have been very supportive during what must have been a trying period for them. Indeed, their pride in this endeavor has done much to make it all very worthwhile. Finally, much credit and thanks must go to R. Carla Reep for typing the ‘manuscript and also for editing and checking it from its typed version to the page-proof stage. Her participation has greatly reduced my work, and allowed ‘many revisions to be made in order to bring this manuscript into its final form. S. K. Guano Mishayuna, New York November 1982 CONTENTS 1 MATERIAL PROPERTIES 1 M 12 13 14 16 PHYSICAL PROPERTIES / 3 CRYSTAL STRUCTURE / 13 CRYSTAL AXES AND PLANES / 16 ORIENTATION EFFECTS / 19 14.1 Silicon / 19 14.2 Gallium Arsenide / 21 POINT DEFECTS / 23 1.5.1 Thermal Fluctuation Effects / 25 Vapor Pressure Effects / 29 Chemical Point Defects / 33 Contamination Control / 41 DISLOCATIONS / 45 1.6.1 Screw Dislocations / 45 1.6.2 Edge Dislocations / 47 1.6.3 Dislocation Movement and Multiplication / 48 1.64 Process-Induced Dislocations / 51 1.65 Two-Dimensional Defects / 53 xixiv CONTENTS 1.7 ELECTRONIC PROPERTIES OF DEFECTS / 53 17.1 Point Defects / 54 1.7.2 Dislocations / 55 1.7.3 Two-Dimensional Defects / 56 TABLES / 58 REFERENCES / 64 PROBLEMS / 67 2 PHASE DIAGRAMS AND SOLID SOLUBILITY 2.1 UNITARY DIAGRAMS / 70 2.2 BINARY DIAGRAMS / 70 22.1 The Lever Rule / 71 2.2.2. The Phase Rule / 72 2.2.3. Isomorphous Diagrams / 73 2.2.4 Eutectic Diagrams / 75 2.2.5 Compound Formation / 78 2.2.6 Peritectic and Other Reactions / 82 2.2.7 Phase Diagrams for Oxide Systems / 87 2.3. SOLID SOLUBILITY / 88 2.4 TERNARY DIAGRAMS / 91 24.1 Isothermal Sections / 93 24.2 Congruently Melting Compounds / 94 2.4.3 Degrees of Freedom / 94 244 Some Temary Systems of Interest / 95 REFERENCES / 99 PROBLEMS / 100 3. CRYSTAL GROWTH AND DOPING 3.1 STARTING MATERIALS / 102 3.2 GROWTH FROM THE MELT / 106 3.2.1 ‘The Czochralski Technique / 106 32.2 Gradient Freeze Techniques / 110 3.3 CONSIDERATIONS FOR PROPER CRYSTAL GROWTH / 113, 3.3.1 The Role of Point Defects / 113 3.3.2. Thermal Gradients in the Crystal / 115 3.3.3. Turbulences in the Melt / 117 69 102 34 36 37 38 39 Cortenntellemetetna = <= Soul: 3.34 Pull and Spin Rate / 118 3.3.5 Crystal Orientation / 118 3.3.6 Crystal Hardening Techniques / 119 DOPING IN THE MELT / 120 3.4.1 Rapid-Stirring Conditions / 121 3.4.2 Partial-Stirring Conditions / 123 3.43. Radial Doping Variations / 126 3.4.4 Constitutional Supercooling / 128 SEMI-INSULATING GALLIUM ARSENIDE / 129 3.5.1 EL2-Doped GaAs / 130 3.5.2. Chromium-Doped GaAs / 131 PROPERTIES OF MELT-GROWN CRYSTALS / 132 SOLUTION GROWTH / 134 ZONE PROCESSES / 135 38.1 Zone Refining / 137 3.8.2 Zone Leveling / 140 3.8.3 Neutron Transmutation Doping / 140 PROPERTIES OF ZONE-PROCESSED CRYSTALS / 141 TABLES / 142 REFERENCES / 145 PROBLEMS / 149 4 DIFFUSION oe at 42 43 44 THE NATURE OF DIFFUSION / 151 DIFFUSION IN A CONCENTRATION GRADIENT / 154 42.1 Field-Aided Motion / 156 4.2.2 Interstitial Diffusion / 159 4.2.3. Substitutional Diffusion / 161 4.24 Interstitialcy Diffusion / 166 4.2.5 Interstitital-Substitutional Diffusion / 167 THE DIFFUSION EQUATION / 171 43.1 The D = Constant Case / 172 43.2. The D = f(N) Case / 180 43.3. Lateral Diffusion Effects / 181 IMPURITY BEHAVIOR: SILICON / 1834s 46 47 48 49 4.10 4.4.1 Shallow Impurities / 184 44.2 Deep-Lying Impurities / 184 IMPURITY BEHAVIOR: GALLIUM ARSENIDE / 197 45.1 Zine in Gallium Arsenide / 198 45.2 Silicon in Gallium Arsenide / 201 DIFFUSION SYSTEMS / 202 46.1 Choice of Source / 204 DIFFUSION SYSTEMS FOR SILICON / 209 47.1 Boron / 210 4.7.2. Phosphorus / 213 4.73 Arsenic / 214 474 Antimony / 216 4.1.5 Gold and Platinum / 216 SPECIAL PROBLEMS IN SILICON DIFFUSION / 217 4.8.1 Redistribution During Oxide Growth / 217 4.8.2 Diffusion During Oxide Growth / 220 48.3 Cooperative Diffusion Effects / 222 DIFFUSION SYSTEMS FOR GALLIUM ARSENIDE / 224 49.1 Temary Considerations / 226 4.9.2 Sealed-Tube Diffusions / 227 4.9.3 Leaky Box Diffusions / 231 4.9.4 Open-Tube Diffusions / 232 4.9.3 Masked Diffusions / 234 EVALUATION TECHNIQUES FOR DIFFUSED LAYERS / 235 4.10.1 Junetion Depth / 236 4.10.2 Sheet Resistance / 237 4.10.3 Surface Concentration / 238 4.104 Diffused Layers in Silicon / 239 4.10.5 Diffused Layers in Gallium Arsenide / 244 TABLES / 246 REFERENCES / 251 PROBLEMS / 256 EPITAXY sa 52 33 55 56 SeeeenaneeeaeneaE 258 GENERAL CONSIDERATIONS / 261 5.11 Nucleation and Growth / 261 5.1.2 Doping / 267 5.1.3 Dislocations / 268 5.14 Thermally Induced Strain / 270 MOLECULAR BEAM EPITAXY / 273 5.2.1 The Growth Chamber / 274 Sources for Growth and Doping / 276 5.2.3. Substrate Holders / 278 5.2.4 Flux and Growth Rate Monitors / 279 5.2.5 Requirements for Good Growth / 279 5.26 Gas Source MBE / 283 VAPOR-PHASE EPITAXY / 283 5.3.1 Source Chemicals / 284 5.3.2 Steady-State Growth / 285 5.3.3. Flow Considerations / 288 5.34 System Design Aspects / 292 PE PROCESSES FOR SILICON / 296 SA. Chemistry of Growth / 296 5.4.2 Epitaxial Systems and Processes / 209 543 In Situ Etching Before Growth / 300 5.44 Impurity Redistribution During Growth / 301 545 Selective Epitaxy / 308 5.4.6 Crystal Defects / 310 PE PROCESSES FOR GALLIUM ARSENIDE / 313 5.5.1 General Considerations / 313 5.52 Growth Strategy / 316 5.5.3 The Halide Process / 317 5.54 The Hydride Process / 320 5.5.5 The Organometallic Process / 321 5.5.6 Impurities and Doping / 325 55.7 Selective Epitaxy / 328 5.5.8 Growth Imperfections / 329 LIQUID-PHASE EPITAXY / 330 5.6.1 Choice of Solvent / 3316 (CONTENTS: 5.6.2 Nucleation / 333 5.6.3. Growth / 334 5.6.4 In Situ Etching / 339 5.6.5 Doping / 340 5.7 LPE SYSTEMS / 340 58 59 5.7.1 Hydrodynamic Considerations / 341 5.1.2 Vertical Systems / 342 5.7.3. Horizontal Systems / 343 5.7.4 Growth Imperfections / 344 HETEROEPITAXY / 345 8.1 Silicon on Sapphire / 346 8.2 Gallium Arsenide on Silicon / 347 EVALUATION OF EPITAXIAL LAYERS / 348 5.9.1 Sheet Resistance / 348 5.9.2 Layer Thickness / 351 5.9.3. Mobility and Cartier Concentration / 352 5.9.4 Impurity / 354 TABLES / 356 REFERENCES / 358 PROBLEMS / 366 ION IMPLANTATION 61 62 64 PENETRATION RANGE / 370 6.1.1 Nuclear Stopping / 374 6.1.2 Electronic Stopping / 380 6.1.3 Range / 382 6.14 Transverse Effects / 384 IMPLANTATION DAMAGE / 389 ANNEALING / 393 6.3.1 Annealing Characteristics of Silicon / 395 63.2 Annealing Characteristics of Gallium Arsenide / 399 63.3. Rapid Thermal Annealing / 406 ION IMPLANTATION SYSTEMS / 407 64.1 Jon Sources / 410 64.2 The Accelerator / 412 64.3 Mass Separation / 413 65 66 67 68 69 368 aeEEe TS EREELEaSEeeee 648 645 PROCESS CONSIDERATIONS / 416 6.5.1 Diffusion Effects During Annealing / 417 65.2 Multiple Implants / 419 65.3 Masking / 420 6.5.4 Contacts to Implanted Layers / 425 6.5.5 Implantation through an Oxide / 426 HIGH-ENERGY IMPLANTS / 430 HIGH-CURRENT IMPLANTS / 431 6.1.1 The SIMOX Process / 431 APPLICATION TO SILICON / 432 6.8.1 Bipolar Devices / 432 68.2 MOS Devices / 433 APPLICATION TO GALLIUM ARSENIDE / 437 69.1 Field Effect Transistor Devices / 438 69.2. Integrated Circuits / 440 TABLES / 442 REFERENCES / 443 PROBLEMS / 449 Beam Scanning / 414 Beam Current Measurements / 416 7 NATIVE FILMS 451 TA 72 73 THERMAL OXIDATION OF SILICON / 452 TL. Intrinsic Silica Glass / 452 7.1.2 Extrinsic Silica Glass / 454 7.1.3. Oxide Formation / 456 7.14 Kinetics of Oxide Growth / 458 7.1.5 Oxidation Systems / 465 7.1.6 Halogenic Oxidation / 470 7.1.7 Mechanical Stress / 472 7.1.8 Oxidation-Induced Stacking Faults / 473 7.1.9 Properties of Thermal Oxides of Silicon / 474 ‘THERMAL NITRIDATION OF SILICON / 483 7.21 Oxynitride Films / 484 ‘THERMAL OXIDATION OF GALLIUM ARSENIDE / 485Sesleri 74 15 16 7.3.1 Interface Trap Density / 486 ANODIC OXIDATION / 487 74.1 Oxide Growth / 491 7.4.2 Anodic Oxidation Systems / 493 74.3 Properties of Anodic Oxides / 494 PLASMA PROCESSES / 495 EVALUATION OF NATIVE FILMS / 498 TABLES / 500 REFERENCES / 503 PROBLEMS / 508 8 DEPOSITED FILMS 510 81 82 83 84 85 86 FILM DEPOSITION METHODS / 511 8.1.1 Vacuum Evaporation / S11 8.1.2 Sputter Deposition / 514 8.1.3. Chemical Vapor Deposition / S18 FILM CHARACTERISTICS / 522 82.1 Growth Habit / 522 8.2.2 Step Coverage / 523 8.2.3. Mechanical Stress / 524 8.2.4 Blectromigration / 526 FILMS FOR PROTECTION AND MASKING / 527 8.3.1 Silicon Dioxide / 528 8.3.2 Phosphosilicate and Borosilicate Glass / 530 8.3.3 Silicon Nitride / 533 8.3.4 Self-Aligned Masks / 535 FILMS FOR DOPING / 546 8.4.1 Dopant Sources for Silicon / 546 8.4.2 Dopant Sources for Gallium Arsenide / 547 FILMS FOR INTERCONNECTIONS / 548 8.5.1 Single-Metal Interconnections / 551 8.5.2 Multimetal Interconnections / 553 8.5.3 Multilevel Interconnections /' 554 FILMS FOR OHMIC CONTACTS / 556 8.6.1 Single-Layer Contacts / 558 86.2 Kirkendall Effects / 561 87 CONTENTS =— Xx! ] 8.6.3. Multilayer Contacts / 564 8.6.4 Die Bonds / 568 FILMS FOR SCHOTTKY DIODES / 570 TABLES / 576 REFERENCES / 578 9 ETCHING AND CLEANING 587 91 92 93 94 95 96 97 WET CHEMICAL ETCHING / 589 9.1.1 Crystalline Materials / 589 9.1.2 Application to Silicon / 591 9.1.3 Application to Gallium Arsenide / 594 9.14 Anisotropic Effects / 598 1 9.1.5 Selective Etches / 603 / 9.1.6 Crystallographic Etches / 604 | 9.1.7 Nonerystalline Films / 606 9.1.8 Problem Areas / 612 DRY PHYSICAL ETCHING / 613 9.2.1 Ton Beam Etching / 615 9.2.2 Sputter Etching / 617 DRY CHEMICAL ETCHING / 620 9.3.1 Photoresist Removal / 622 9.32. Pattern Delineation / 624 REACTIVE ION ETCHING / 625 9.4.1 Loading Effects / 626 9.4.2. End-Point Detection / 628 9.4.3. Etch Chemistries / 629 CHEMICALLY ASSISTED ION BEAM TECHNIQUES / 636 ETCHING-INDUCED DAMAGE / 638 CLEANING / 639 9.1.1 “Dry” Cleaning Processes / 642 9.7.2 Schottky Diodes and Gates / 643 TABLES / 646 REFERENCES / 654 PROBLEMS / 661ao CONTENTS: 10 LITHOGRAPHIC PROCESSES 662 " 10.1 10.2 10.4 105 PHOTOREACTIVE MATERIALS / 664 10.1.1 Image Reversal / 669 PATTERN GENERATION AND MASK-MAKING / 669 10.2.1 Pattern Generation / 671 10.2.2 Mask-Making / 673 PATTERN TRANSFER / 674 10.3.1 Optical Printing / 676 ADVANCED TECHNIQUES / 685 10.4.1 Short Wavelengths / 685 10.4.2 Multilayer Resists / 687 10.4.3 Phase-Shifting Masks / 690 10.4.4 Electron-Beam Techniques / 691 10.4.5 Ton-Beam Techniques / 692 10.46 X-Ray Printing / 693 PROBLEM AREAS / 696 10.5.1 Mask Defects / 697 105.2 Pattem Transfer Defects / 697 TABLES / 700 REFERENCES / 701 DEVICE AND CIRCUIT FABRICATION 704 Ma 12 113 1a is 16 17 ISOLATION / 705 IL1.1 pon Junction Isolation / 706 IL1.2 Mesa Isolation / 708 11.1.3. Oxide Isolation / 711 SELF-ALIGNMENT / 712 LOCAL OXIDATION / 714 113.1 Trench ‘Techniques / 719 PLANARIZATION / 721 1.4.1 Chemical-Mechanical Polishing / 726 METALLIZATION / 726 GETTERING / 728 MOS-BASED SILICON MICROCIRCUITS / 730 17.1 The p-Channel Transistor / 731 1s ng ‘Appendix Al (CONTENTS XXII 11.7.2. The n-Channel Transistor / 731 11.7.3. Complementary Transistors / 735 11.14 Memory Devices / 738 11.7.5 Hard and Soft Errors / 747 11.1.6 Silicon-on-Insulator Devices / 748 BJT-BASED SILICON MICROCIRCUITS / 749 LL8.1 ‘The Buried Layer / 751 11.8.2 Choice of Transistor Type / 754 1183 Transistor Properties / 755 11.84 p-nep Transistors / 758 11.85. Special-Purpose Bipolar Transistors / 760 118.6 Field Effect Transistors / 761 118.7 Advanced Structures / 762 11.88 Bipolar-CMOS Integrated Circuits (BICMOS) / 767 1189 Diodes / 769 118.10. Resistors / 772 1.8.11 Capacitors / 775 GALLIUM ARSENIDE MICROCIRCUITS / 778 11.9.1 The Depletion-Mode Transistor / 779 119.2. The Enhancement-Mode Transistor / 783 11.9.3 Enhancement/Depletion-Mode Pairs / 784 119.4 The High-Electron-Mobility Transistor / 784 11.9.5 Self-Aligned Technology / 786 11.9.6 The Heterojunction Bipolar Transistor / 787 TABLES / 790 REFERENCES / 790 ‘THE MATHEMATICS OF DIFFUSION 801 SOLUTIONS FOR A CONSTANT DIFFUSION COEFFICIENT / $02 All Reflection and Superposition / 802 A.1.2. Extended Initial Conditions / 803 A.1.3__ Diffusion through a Narrow Slot / 804 A.L4 Miscellaneous Useful Solutions / 805 A.LS Some Useful Error Function Relations / 807 A..6 — General Solution for Diffusion into a Semi-Infinite Body / 807NY CONTENTS A2 AB Ad INDEX SOLUTION FOR A TIME-DEPENDENT DIFFUSION COEFFICIENT / 811 A2.1 — Ramping of a Diffusion Fumace / 812 SOLUTION FOR CONCENTRATION-DEPENDENT, DIFFUSION COEFFICIENTS / 813 DETERMINATION OF THE DIFFUSION CONSTANT / 815 A4.1 The p-n Junction Method / 815 4.2 — The Boltzmann—Matano Method / 816 REFERENCES / 817 819 VLSI FABRICATION PRINCIPLESCHAPTER 1 EEE MATERIAL PROPERTIES Although many elements and intermetallic compounds exhibit semiconducting, properties, silicon is used almost exclusively in the fabrication of semiconductor devices and microcircuits. Of the many reasons for this choice, the most impor- tant are the following: 1. Silicon is an elemental semiconductor. Together with germanium, it can be subjected to a large variety of processing steps without the problems of decomposition that are ever present with compound semiconductors. For much, the same reason, more is known today about the preparation and properties of extremely pure single erystal germanium and silicon than for any other element in the periodic table 2, Silicon has a wider energy gap than germanium. Consequently it can be fabricated into microcircuits capable of operation at higher temperatures than their germanium counterparts. At the present time the upper operating anibient temperature for silicon microcircuits is between 125°C and 175°C, which is entirely acceptable for both commercial and military applications. 3. Unlike germanium, silicon lends itself readily to surface passivation trea ‘ments. This takes the form of a layer of thermally grown SiO; which provides a high degree of protection to the underlying device. Although the fabrication of devices such as metal-oxide-semiconductor (MOS) transistors has emphasized that this oxide falls short of providing perfect control of surface phenomena, it is safe to say that the development of this technique provided a decisive adva tage for silicon over germanium as the starting material in microcircuits (1)‘As a result of the above, a significant technological base has been estab- lished to take advantage of its characteristics. This includes the development cof a number of advanced processes for deposition and doping of silicon layers, as well as sophisticated equipment for forming and defining intricate patterns for very-large-scale integration (VLSI), Although silicon is the workhorse of the semiconductor industry, it is not an optimum choice in every respect. Many compound semiconductors, for example, are direct band gap, whereas the band gap of silicon is indirect. This results in unique properties which allow functions that cannot be performed by silicon. These include transferred electron oscillators, lasers and light-emitting devices, and a variety of highly efficient, lightweight, photovoltaic devices for space as well as terrestrial applic Of the many compound semiconductors, GaAs has come under the greatest scrutiny, and its technology is the most highly developed. Its low-field electron ‘mobility is larger than that of silicon, so that majority carrier devices in GaAs are faster than in silicon, GaAs has a lower saturation field than silicon, so that GaAs devices have a smaller power-delay product. Finally, Gas can be made sulting (I. with a bulk ressvity onthe oder of 10” fem, Davies circuits. In sum, both discrete components and integrated circuits made in GaAs are faster than those made in silicon (2) The importance of GaAs as an electronic material is greatly enhanced by the fact that itis closely latice-matched to aluminum arsenide, which has a much wider energy gap (2.16 eV). Combinations of these materials, the temary alloys Al,Ga,.,As, can thus be grown on GaAs with a wide range of com- Positions (and energy gaps), and still have a reasonably defect-free interface. ‘The growth of device-quality AIGaAs has allowed the fabrication of practical heterostructure devices, such as highly efficent double heterostructure lasers, high-electron-mobility transistors, and a number of novel bipolar device struc. tures. Comparative studies [3] of silicon emitter coupled logic circuits and AIGaAS/GaAS heterojunction bipolar transistor logic have predicted a propa- ation delay improvement over silicon by a factor of three or more, for devices with the same feature size. Recent advances in molecular beam epitaxy and in organometallic vapor- Phase epitaxy have allowed the fabrication of structures with multiple layers of GaAs and AlGaAs, controlled to atomic dimensions. This has not only resulted in improvements in conventional devices, but has also opened up the possi- bility for entirely new device concepts involving superattices and quantum well ‘structures [4]. In addition to GaAs, other new materials and material systems ate under active consideration for device and circuit applications. These include almost all combinations of I1I-V compounds, and more recently the I-VI compound semiconductors. The technology of these materials is in its infancy theless, unique application advantages have resulted in a few becoming com- scaly viable today, By way of example, Gay-snAs an be grown laice- ef om InP for = O53. The enery gap of this material makes it dally Site frente td dtecos with Iw 1oss opal ters operaing in the soa to 1m range [5]. A second example isthe system CaTe-HigTe, whose Pinar components are ltice-matched to within 0.28%. This allows the fabri cation of Hg),Cd,Te devices which can be optimized over the 0.9- to 16-um ange of wavelengths [6] The lage variety of such material combinations pe- Tins them all fom becoming developed tothe same level as GaAs, They wil Nor be considered inthis book, excep in passing. Nonthces, iis important to recognize thatthe fabrication principles of GaAs can offen serve 28 useful starting point for work with other compound semiconductors, Tn this chapter some of te properties of silicon and GaAs are considered, especially those which have a bearing onthe fabrication processes tha follow as well as on the properties of devices made by these fabrication technologies. A Shor lst ofthese properties is provided in Table 11, athe end ofthis chapen* 1.1. PHYSICAL PROPERTIES ‘Together with carbon, germanium, tin, and lead, silicon belongs in group IV of the periodic table. In single-crystal form, it adopts the diamond lattice struc: ture, with each atom covalently bonded to four nearest neighbors. Many of its physical properties result from this strong covalent bonding. In pure form, its lattice constant is 5.43086 A at 300 K, increasing by +0.02% with doping. ‘The nearest neighbor distance between silicon atoms in the diamond lattice is 2.35163 A. Single-crystal GaAs adopts the zincblende structure, with each Ga atom bonded to four nearest-neighbor As atoms, and vice versa. The edge dimension of the unit cell of undoped, stoichiometric GaAs is 5.65325 A, with a nearest neighbor distance of 2.44793 A between Ga and As atoms [7, 8]. Heavily doped GaAs has a slightly larger lattice constant, by about 0.02%. The lattice param eter is reduced by about 0.01% for nonstoichiometric As-tich gallium arsenide, and increased by about this same amount for Ga-rich material. Its limits for stoichiometry are between 49,998 and 50.009 at.% of arsenic. ‘The presence of dissimilar atoms makes GaAs about 69% covalent, and sig- nificantly alters its electronic band structure. Figure 1.1 shows simplified band structures of both silicon and GaAs at 300 K, along two principal directions in the crystal. For both materials the valence band maximum occurs at the zero ‘wave vector point (P). With GaAs, the minimum conduction energy is located at the same point, so that it has a direct energy gap, whose value is approximately 1.43 eV at 300 K. With silicon, however, the minimum conduction energy is located near the x point, so that it has an indirect energy gap of about 1.11 eV at 300 K. Other important intervalley spacings are indicated in Fig. 1.1 as well *The comparative properties of GAAS, AIAS, and Al,Gaj-y As are detailed in Ref. 8cam r nox Lair qo x ig. L1 Simplified energy band structure of silicon and GaAs ‘The wider energy gap of GaAs results in two important advantages over si icon. First, the intrinsic carrier concentration is about four orders of magnitude lower (10° em” as compared to 10" cm” for silicon at 300 K), so that truly SI GaAs is possible whereas ST silicon is not. Next, the barrier height of metals on Gad is sufficiently large (=0.85 eV) so as to give low-leakage Schottky diode structures with a wide variety of metals. In contrast, most metal-Si combina- tigns (with the notable exception of Pd-Si and Pt-Si) have low barrier heights, around 0.6 eV, and result in correspondingly leaky devices. The surface properties of silicon and GaAs are strikingly different. Silicon, especially when thermally oxidized, has a significantly lower density of surface states than does GaAs. As a result, its surface can be inverted by the use of a simple metallic gate, placed on this oxide. This has allowed development of the MOS transistor, which is the comerstone of silicon-based VLSI technology. In contrast, the fermi level in GaAs is strongly pinned near the midgap, because of the high surface state density. For this reason, an equivalent MOS based technology is not available in this material. However, the combination of GaAs with AlGaAs to form a heterojunction circumvents this problem, and also allows the fabrication of high-electron-mobility transistors (HEMT) which have a significant speed advantage over silicon devices [3] A second consequence of fermi-level pinning in GaAs is that the Schottky barrier height is relatively independent of the choice of metal, and of the surface processing conditions. With n-type GaAs the barrier height is about 0.85 eV. By the same token, the batrier height on p-type Gas is also relatively fixed, at about 0.6 eV, so that low leakage Schottky devices can only be made on lightly doped material - [As we have pointed out, only platinum and palladium can be used to make satisfactory Schottky diodes on n-silicon. Considerable attention must be paid to surface processing conditions in order to fabricate these structures with co sistent values of barrier height. This necessitates the deposition of the metal on a silicon substrate which has been in-situ cleaned. Sputtering is the preferred deposition process for these metals, since back-sputtering can be used for sur- face cleaning, prior to the actual deposition. ‘The effective mass of electrons and holes is inversely proportional to the curvature of the energy bands, and is listed in Table 1.1. Note that the electron effective mass m, for silicon is considerably larger than that for GaAs: the elec- tron mobility is Correspondingly lower, typically 1500 cm?/ V s for silicon as compared to 8500 cm?/V s for GaAs at 300 K. This accounts in large measure for the speed advantage of GaAs over silicon in majority carrier n-type devices [9]. This is because the larger electron mobility results in a higher low field velocity at low electric field strength, as well as reduced parasitic resistance. In addition, the ability to attain a high drift velocity at low electric fields allows GaAs digital circuits to be operated with lower power-speed products than those made in silicon, ‘The energy band structure of GaAs also exhibits an upper satellite valley, about 0.38 eV removed from the lower [7]. The effective mass of electrons in this valley is considerably larger (1.2 iy as compared with 0.067 for the lower valley), so that the electron mobility is correspondingly reduced. The transfer of electrons from the lower to the upper valley at electric fields above 3.5 KV/em consequently results in a fall in mobility, and gives GaAs the unique differential mobility character shown in Fig. 1.2, which is rot present in silicon. Bulk microwave oscillators, sometimes referred to as Gunn oscillators {10, 11), have exploited this property and are in common use today. ety 10? ems) ation ° 3 10 20 etre (end 1.2 Velocity versus electri field strength characteristics of silicon and GaAs at 300 K- Adapted from McCumber and Chynoweth {10}MATERIAL PROPERTIES The hole effective masses of silicon and GaAs are comparable, as are their mobility values; typically the latter are 500 cm?/V s and 450 cm?/V s for lightly doped silicon and GaAs, respectively, at 300 K. Majority carrier devices, based ‘on hole transport, have not been developed in Gas for this reason. On the ‘other hand, p-type silicon (and GaAs) are preferred over n-type materials in ‘minority carrier devices because the electron diffusion length is larger than the hole diffusion length. Commercially available silicon is nearly uncompensated. Thus n-type mate- rial has a negligibly small amount of shallow or deep acceptors unintentionally incorporated in it. Similarly, the concentration of donors which are unintention- ally present in p-type silicon is negligibly small. As a result, the drift mobility of starting silicon, shown in Fig. 1.3, is essentially that of uncompensated mate- rial. A plot of resistivity as a function of carrier concentration is shown in Fig. 14. Although relatively free of compensation, bulk silicon typically has in it a significant amount of inert impurities such as carbon, oxygen, fluorine, sodium and calcium, By way of example, Table 3.1 in Chapter 3 lists the impurity content ofa typical silicon crystal, grown by different manufacturing techniques 12} ‘The purification of Gaas is not as advanced as that of silicon, so that many shallow and deep impurities are unintentionally present in GaAs. These are listed, together with their typical concentrations, in Table 3.2 in Chapter 3 [13] 10.000 s1(900K) 000] lem? vs 100 107 107 107 107 10 Concentration fem) 1.3 Electron and hole drift mobilities in silicon. 102 102 Carrier concentration (cm) 10 13 0 10? 10?) Resistivity (ohm-cm) Fig. 14. Resistivity versus carrier concentration in silicon Some of these impurities form complexes with gallium or arsenic; some are inactive, while yet others are active and of both n- and p-type. In addition, they can be incorporated substitutionally on vacant gallium or arsenic lattice sites, whose concentrations are a function of the temperature and the ambient partial pressures of the gallium and arsenic vapor species. As a result, all GaAs is compensated to some extent: that is, it has in it both ionized acceptors Nj and ionized donors Nj. The degree of compensation in n-GaAs is often specified by the ratio (Wj -+N)/n, where m is the free electron concentration (=Nj)~N,). ‘An alternative approach is to specify the compensation ratio as N4/Nj. In compensated material, the total number of ionized impurities is larger than the free carrier concentration, so that the mobility is lower than what would be expected if it were uncompensated. The results of theoretical calculations of electron mobility, which include all major scattering mechanisms, are shown in© MATERIAL PROPERTIES: Fig. 1.5, for drift mobility* as a function of the free electron concentration, at 300 and 77 K, respectively, and for different values of the compensation ratio tay, Experimentally, the ne? cartier concentration in n-type GaAs can be obtained readily by Hall measurements at any given temperature. However, determina- tion of the total ionized impurity concentration necessitates (a) an analysis of the temperature dependence of the Hall mobility and (b) fitting these data to the relevant scatter processes [15]. Based on this approximation, a semiempirical relation, which takes into account all scattering mechanisms, has been devel- oped for n-type GaAs. This relationship, shown in Fig. 1.6, shows the 77K Hall mobility measured at 5 KG, as a function of Nj +N, and zyx. This curve can be used to estimate the compensation ratio, since rx is also obtained from the Hall measurements at this temperature. ‘The above method becomes increasingly inaccurate when the free electron concentration exceeds 2x 10"”/em’. Alternative computations, correlated with ‘measurements of the free carrier absorption in addition to the electron mobility have been made to extend the range to 5x 10!*/em* [16]. However, devia- tions from band parabolicity, due to either (a) interaction between impurities, (b) many body effects, or (c) inhomogeneous distribution of impurities causing band-gap fluctuation, can cause inaccuracies in this approach. For these reasons, a more direct approach, utilizing quantitative secondary ion mass spectrometry ‘measurements in conjunction with Hall data, has been favored for determination of the total impurity concentration in heavily doped GaAs [17] ‘A plot of hole mobility in p-type Gas arsenide is shown in Fig. 1.7. Studies of this material [7] have not been extensive, since its primary role has been in injecting p* contacts to n-type GaAs. Recently, however, it has become more important because of its use in photovoltaic devices. since its minority carrier diffusion length is larger than that for holes in n-type material ‘The number of hole-clectron pairs generated by an electron, as it travels unit distance in a semiconductor, is described by an electron ionization rate, cy. Sim- ilarly, ap relates to holeelectron pairs created by hole transport in a semicon- ductor. These ionization rates determine the upper operating voltage of semi conductor devices. Devices such as Impact Avalanche Transit Time (IMPATT) diodes, which are important microwave power sources, are designed to operate in a mode where these effects are exploited. Figure 1.8 shows the ionization rates for electrons and holes in silicon and GaAs. Here, we note that the coefti- ients for GaAs ate similar, while those for silicon are not. It can be shown that IMPATT diodes made of GaAs are more efficient than silicon devices for this reason [18]. Empirical relations for the ionization rates of electrons and holes are given in Table 1.1 “The Hall mobility is approximately equal to 1.93 times the electron drift mobility i the dom- inant seater mechanism is due to ionized impurities, The Hall and drift mobilities of holes are approximately equal 1.1 PHYSICAL PROPERTIES 9 TT TT 47 caascoox) 000 Mobiity(en?/V #) 2000] as Soom oL a ily vid ys 10 wo 107 108 wo"? Free electron concentration fom?) Tt T TT a TT T1171 7 Gaasorn) | 10 10 10 10 Free leon concentration (en) a LS Electron mobility at 77 and 300 K, as a function of (Nj, +N3)/. From Rode U4}. Reprinted with permission from Physical Review ‘The nature of the energy band gaps of silicon and GaAs give rise to uniquely different optical properties, as seen in the absorption characteristics of these materials for radiation above the energy gap (19, 20]. As shown in Fig. 1.9, the variation of the absorption coefficient of silicon is more gradual than that of GaAs, for photon energies beyond their respective band gaps. This is a con-18 10! ‘oF 0 ao 70" w95 ona fo") ews Fig. 16-1077, as a function of +N and n, Adapted from Stillman and Wolfe [15]. sequence of the indirect band-gap nature of silicon, where phonons must be involved in order to conserve momentum during the recombination process. ‘The absorption edge of GaAs has been studied in much detail, and is related to the free electron and hole concentration in the material, This is illustrated in Fig. 1.10. ‘The direct gap character of GaAs results in a number of features of impor- tance in optically related applications. First, almost complete absorption of light, occurs in an extremely short penetration depth in Gas as compared to that in silicon—typically 1 jm as compared t0 100 um. As a result, optical devices in GaAs have dimensions which are comparable to those of integrated cir- cuits. The optical integrated circuit is thus an achievable goal in GaAs. Second, GaAs devices are extremely efficient emitters of optical radiation, since the recombination process is accompanied primarily by photon emission. Third, ‘1.1 PHYSICAL PROPERTIES = 11 $00 TTT TTT TTT ans 300K) 10" 1010) 107 10 0? 10 Hote concentration fom~2) Fig. 1.7 Hole mobility in gallium arsenide. Adapted from Blakemore [7] GaAs recombination processes are faster than in silicon, because ofthe absence of phonon participation. For these reasons, high-speed optical devices have become the almost exclusive domain of GaAs and other direct gap compound semiconductors Additional properties of silicon and GaAs, which impact directly on the ease with which devices can be manufactured in a factory environment, are given in Table 1.1. By way of example, the critical resolved shear stress is 7.75% 10? dyn em’? for GaAs, and 3.61 x 10” dyn cm-? for silicon. As a consequence, GaAs Ba So 5, By Be ELECTRONS & HOLES nm en he Laney FIELO (Wem) Fig. 1.8. onization coefficient for electrons and holes in GaAs and Si at 300 K. From Howes and Morgan [9]. ©1985. Reprinted by permission of John Wiley and Sons12 MATERIAL PROPERTIES: th % 3% Absorption Coefficient, em! uf 30 18 36 244780 Photon Energy, eV Fig. 1.9 Band-gap absorption of Si and semi-insulating GaAs, From Hovel [19]. slices larger than 75~100 mm in diameter are extremely fragile, and cannot be subjected to heat treatment or physical handling during processing without fear of breakage [21]. Silicon, on the other hand, can be readily handled in slices as large as 200-300 mm in diameter in a manufacturing environment. The thermal conductivity of silicon is about 2.75 times larger than that of GaAs. As a consequence, the power-handling capacity of a GaAs integrated circuit is severely limited by the thermal resistance of the substrate, Often, these slices must be mechanically or chemically thinned prior to mounting on a headet. This is a delicate process at best, with a high chance of wafer breakage, igh purity 1 6ar0!eni3 ~ j 3 : 2 130 eo 150 180 PHOTON ENERGY (ev) Fig. 1.10 Band-gap absorption of doped GaAs. From Casey and S with permission from the Journal of Applied Physics. [20]. Reprinted 2 OSA ne US ‘An important consequence of this poor thermal conductivity of GaAs is that packing densities achievable in silicon microcireuits cannot be matched in cit- Cults built on bulk GaAs substrates. This limitation has given rise to consid- erable research into the growth of thin single-crystal films of GaAs on silicon Substrates [22], in the hope of circumventing the heat dissipation problem. If successful, this approach would also soive the physical handling problems of large GaAs slices. 4.2. CRYSTAL STRUCTURE Both silicon and GaAs belong to the cubie class of crystals and exhibit the following structures 1. Simple Cubic (s.c.). This is illustrated in Fig. 1.1la. Very few crystals ‘exhibit as simple a structure as this one; an example is polonium, which exhibits this structure over a narrow range of temperatures. 2. Body-Centered Cubic (b.c.c.). This is illustrated in Fig. 1.115. Molyb- denum, tantalum, and tungsten exhibit this erystal structure. 3. Face-Centered Cubic (fc.c.). This is illustrated in Fig. 1-11. The struc- ture is exhibited by a large number of elements, such as copper, gold, nickel, platinum, and sitver. (The face-centered atoms are shown different from the comer atoms for illustrative purposes.) 4, The Zincblende or Sphalerite Structure. This structure consists of two interpenetrating f.c.c. sublattices, with one atom of the second sublattice located at one-fourth of the distance along a major diagonal of the first sublattice. This configuration is illustrated in Fig. 1.12a and 1.126, where solid circles belong to the first sublattice and open circles belong to the second. In GaAs, each sublattice contains atoms of only one type (either gallium or arsenic). The dia- ‘mond lattice is a degenerate form of this structure, with identical atoms in each sublattice. Silicon belongs to this class. The position of the various atoms in the zincblende lattice can be calculated in multiples of the lattice constant a. Thus for the f.c.c. structure the various coordinates (normalized to a) for the comer lattice sites are 0, 0, 0; 0, 0, 1; 0,1,.0; 0, 1, 1: 1, 0, 0; 1, 0, 1; 1, 1, 0; and 1, 1, 1, Coordinates for the fave. centered sites are #,4,054,4,10.4 1,3, respectively. For the zincblende lattice itis necessary to include the coordinates of the second sublattice, spaced at 4,1, from those of the fist. Within the unit cell, these are | S344, 8) 8 and 3,1,3, respectively. In Fig. 1.126 these lattice sites'are shown different from those of the original sublattice. With reference to Fig. 1.12, the following comments may be made:Fig. LIL Cubic crystal lattices, 1. The coordination number for the zincblende lattice is 4; that is, each atom has four nearest neighbors which belong to a different sublattice. In silicon each atom has four valence electrons which provide covalent bonding with these nearest neighbors. In GaAs, however, each arsenic atom (with five valence elec- trons) has four neighboring gallium atoms, each of which has three valence electrons. In like manner, each gallium atom (with three valence electrons) has 4.2 CRYSTAL STRUCTURE 15 (Fa Fig. L12. The zincblende lattice four neighboring arsenic atoms, each having five valence electrons. Together, these gallium-arsenie pairs enter into bonding, which is about 69% covalent in character, and 31% ionic. Figure 1.13 shows an enlarged picture of a sub- cell with side a/2 in order to delineate tetrahedral covalent bonds of the type described here. 2. The distance between two neighboring atoms is (/3/4)a, where a is the lattice constant. For silicon, the lattice constant is approximately 5.43 A at room temperature, so that this distance is 2.351 A. The radius of the silicon atom is thus 1.18 A, if we assume a “hard sphere” model for atoms. Since each atom is situated within a terahedron comprising its four neighbors, this is referred to as the tetrahedral radius. For GaAs, the lattice constant is approximately 5.65 A at room temperature, so that the distance between neighbors is 2.44 A. The tetrahedral radii of gallium and arsenie are 1.26 A and 1.18 A, respectively; together they add up 10 244 A 3. Using the hard-sphere model, 34% of the silicon lattice and 33.8% of the GaAs lattice is occupied by atoms. Thus these are relatively loosely packed structures as compared to fc.c. crystals, where the packing density is approxi- mately 74%. Table 1.2 at the end of this chapter lists the tetrahedral radii* and energy levels of various impurities that are commonly introduced into the silicon lattice Note tht the effective radius of an impurity tom in a zincblende latice is independent ofthe ‘chemical components ofthis latie. The concept of a constant tetrahedral radius isan empirical but very useful one. This radius. is. bowever. ot the same as the radius of the atom in its own, Tatice (i. its ionic radius), since the internal field conditions are quite different for these cases,16 MATERIAL PROPERTIES Fig. 1.13 ‘The zincblende subeell to control its electronic behavior, or may be present as contaminants. If ry is the tetrahedral radius of the silicon atom, the radius of the impurity atom may be written as ro(I se). The quantity € is defined as the misfit factor, and is indicative of the degree of strain present in the lattice as a result of introducing this impurity. To a fair approximation, it is also an indication of the amount of dopant which can be incorporated into electronically active sites in the lattice, before the onset of strain induced damage to the crystal lattice. Impurities used for doping GaAs are listed in Table 1.3 at the end of this chapter. Some of these dopants are incorporated on only one sublattice, corre- sponding to a single misfit factor. Yet others can substitute on either or on both lattices, so that two misfit factors describe their behavior more appropriately. 1.3. CRYSTAL AXES AND PLANES Directions in crystals of the cubic class are very conveniently described in terms of Miller notation [23]. Consider, for example, any plane in space, which sat- ‘1.3 CRYSTAL AXES AND PLANES = 17 isfies the equation =1 ay ais Here a,b, and c are the intercepts made by the plane at the x,y, and 2 axes, respectively. Writing h,, and / as the reciprocals of these intercepts, the plane may be described by hx+ ky +, a2) The Miller indices for such a plane® are written as (ikl). Integral values are usually chosen in multiples of the edge of the unit cell. Figure 1.14a shows a cubic crystal with some of its important planes indi- cated. Here the plane ABCD is designated (110), while the plane EDC is des- ignated (111). The (100) and (010) planes are also shown in this figure. Figure 1.146 shows an example of how planes with negative indices may be described. ‘Thus the plane PORS is defined by (0, —1,0) and is commonly written as (010). The plane RSTU is written in like manner as (110). ‘The atom configurations in many of the Miller planes in a cubic crystal are identical. Thus the planes (001), (010), (100), (00T), (010), and (T00) are essen’ tially similar in nature. For convenience they are written as the {001} planes. Figure 1.14c shows examples of planes with higher indices. Thus the plane GHKL is denoted by (1, 1,0) or preferably by (210). Similarly, the plane HKL is written in Miller notation as (212), Planes with higher Miller indices may be sketched by extending these prin- ciples. They are not, however, often encountered in discussions of the material Properties of semiconductors. Often, these planes can be considered as stepped structures, with the steps and the risers consisting of different low-Miller-index planes. Indices of lattice plane direction (ie., of the line normal to the lattice plane) are simply the vector components of the direction resolved along the coordinate axes. Thus the (111) plane has a direction written as [111], and so on. This is an extremely convenient feature of the Miller index system for cubic crystals. For this notation the set of direction axes [001], [010], [100], [001], [010], [100] is written as (001). The angle 6 included between two planes (1 vj¥)) and (u51yW) is given by (3) “It should be oted that (ik!) refers 10 any one ofa series of parallel planes in a cubic crystal, This may be seen by a simple shifting ofthe origin forthe references axes.18 MATERIAL PROPERTIES y 1.14 Miller planes ‘The line describing the intersection of these planes is [u v w, where We yyw) = vow (14a) = wa — wath (4b) w= mys — tvs (ae) ‘The separation between two adjacent parallel planes {k/} is given by (as) This separation is equal to a for the 100 planes, to 0.707a for the (110) planes, and to 0.577a for the {111} planes. Thus the {111} planes are the closest spaced among the low-index planes. ‘1.4 ORIENTATION EFFECTS = 19 1.4 ORIENTATION EFFECTS Many fabrication processes are orientation-sensitive; that is, they depend on the direction in which the crystal slice is cut. This is to be expected, since many mechanical and electronic properties of the crystal and its surface are also orientation-dependent. Some of the consequences of crystal orientation are now described. 1.4.1 Silicon For silicon the (111) planes exhibit the smallest separation (3.135 A), Therefore growth of the crystal along a (111) direction is the slowest, since it results in the setting down of one atomic layer upon another in closest packed form. Based ‘on packing considerations, (111) silicon is therefore the easiest to grow. It is thus the least expensive, and is used in many bipolar devices and microcirouits today. ‘The atom density in the principal planes can be shown to be in the ratio {100} : (110) : (111) = 1: 1.414 : 1.155. Since atoms in these planes have 2, 1, and 1 dangling bonds respectively, the bond densities are in the ratio 1 £0,707 : 0.577. Crystal dissolution is related to the density of broken bonds; therefore itis slowest in the (111) di delineate these faces. As ‘a consequence, parallel-plane alloyed junctions can only be made on (111) sil- icon, Crystal dissolution by chemical etching is also slowest in the (111) direc- tions, for this reason, Consequently, selective etches will preferentially etch sil- icon by exposing {111} planes. The use of this technique for cutting V-grooves in a (100)-oriented silicon slice, as well as deep vertical trenches with parallel sides, is outlined in Chapter 9, together with a number of suitable etch for- ‘mulations. This forms the basis for many important microelectronic processes which are used today, as well as for a variety of micromachining applica- tions (24) The ultimate tensile strength of silicon (0.35 x10! dyn em’) is a maxi- mum in the (111) directions. In addition, the modulus of elasticity in the (111) directions is higher than in the (110) or (100) directions (1.9% 10", 1.7 10, and 1.3 x 10” dyn cm’, respectively). As a result, silicon tends to cleave along the {111} planes [25], since they are normal to the (111) di tions. Silicon microcircuits, especially those fabricated in large diameter (2100 mm), are generally diced by sawing apart through most of the slice thickness, and then breaking apart by deforming the slice. Smaller-diameter slices (which ‘are about 200 jum thick) are usually separated into individual chips by cleaving. This is done by scribing the surface with a diamond tool into a rectangular pat- tem, and deforming it until it breaks by the propagation of the scribe cracks through the bulk of the silicon, along the natural cleavage planes. The {111} cleavage planes within a slice meet the (100) plane of the surface at an angle of 54.74° along the (110) directions. Thus it is desirable to make20 =~ MATERIAL PROPERTIES scribe lines along the (110) directions, for easy cleaving. In practice, each slice is supplied by the manufacturer with a reference flat ground into it s0 as to allow the first scribe line to be made along an easy cleavage plane. The (110) directions on the (100) surface are mutually at 90° to each other, so that both sets of scribe lines can be made along easy cleavage planes as shown in Fig. 1.15. Note, however, that the sides of chips cut apart in this manner will not be at right angles to the plane of the surface. Separation of (111) silicon into dice presents a special problem, since the 111} cleavage planes intersect the surface on (110) directions which are mutu- ally at 60°, as seen in Fig. 1.15. Thus, only one side of rectangular chip can be scribed in the (110) direction. As a result, cleaving of the other side results in a jagged, zigzag line, with each individual jag along one of the (110) dinec- tions. Chips that are separated by this technique must have considerable spacing provided between them to prevent damage to the microcircuit It is difficult to grow silicon in the [110] direction, so that this material is not used for conventional applications. However, (110) silicon plates can be readily cut out of suitably oriented (111) silicon, An unusual property of (110) silicon is that some of the { 111} planes intersect its surface at 90°. AS a result, this material finds use in situations where it is required to etch deep vertical, parallel-sided grooves in silicon [24]. Other processes which are orientation-dependent are diffusion and oxidation. ‘These are taken up in detail in Chapters 4 and 7, respectively The electronic properties of the silicon surface are related to the density of, dangling bonds on the surface, as well as to their bond strength. Typically it has been observed that the surface state density for (100) silicon is fower than serie ne sere Line stem Lh i ) 100 tah { ill i I ' ! { ' ' ' ' { i 1 Ker \ gs 16 wo or LAS. Scribe lines and cleavage planes for {111} and {100) silicon. 1.4 ORIENTATION EFFECTS 21 that for (111) silicon by a factor of about 3 [26]. As a result, (100) silicon is often used for bipolar applications where low 1/f (or Ricker) noise is requined Furthermore, almost all MOS circuits are built on (100) silicon today, because its use results in improved control of the threshold voltage, This represents a very large application area, so that the gap between slice costs for these two orientations has been sharply reduced. 1.4.2. Gallium Arsenide As noted earlier, GaAs comprises two interpenetrating fcc. sublattices, One of these is displaced one-quarter of the way along the main diagonal of the other, resulting in asymmetry [27]. This is seen in Fig. 1.16, which shows a schematic view of the gallium arsenide lattice, with the (111} axis (body diagonal) in the plane of the paper. We note that the crystal structure consists of hexagonal rings, stacked in plane of the paper, but with different spacings. Assigning the layers to gallium and arsenic, their succession in the [111] direction is Ga-As—Ga- ‘As—Ga-As—, whereas in the (TT T] direction it is As-Ga—As-Ga—As-Ga—. In silicon these two directions are identical; with GaAs they can be distin- guished from each other, and the [111] axis is a polar axis for this structure. 111) plane in this figure is referred to as the (111) Ga face, whereas the (ITD) plane is called the (111) As face. These faces are often referred 10 as (111) A and (111) B, or simply as the A and B faces, respectively. (110) Ge face) Gi on) am ae (ice) Fig. 1.16 Schematic ofthe zincblende lattice, observed at right angles to the [111] axis,22 MATERIAL PROPERTIES Looking down on the crystal from the top, at the (111) Ga face, we have two possibilities: We can get a gallium atom connected by three covalent bonds to arsenic atoms in the next (lower) layer, with one dangling bond. Altematively, it is possible to have an arsenic atom connected by one covalent bond to a gallium atom in the next (lower) layer, with three dangling bonds. Energetically, the first of these situations is more Favored, and the second does not appear to even exist. In fact, crystal growth and etching always seem to occur by the growth or dissolution of such double layers. Looking at the (111) As face from the bottom, the opposite situation is observed, with arsenic atoms connected by three bonds to the next layer of gallium, and so on As a result of these bonding configurations, the (111) Ga face has gallium atoms with no free electrons, since all three of theit valence electrons are attached to arsenic atoms in the lower layer. The (111) As face, on the other hand, consists of arsenic atoms, each with two free electrons, since only three of their five valence electrons are attached downwards. The (111) As face is thus more electronically active than the (111) Ga face. ‘This difference in activity is manifested in a number of situations. Thus, etching of the (111) As face occurs very rapidly with a resultant smooth polish. ‘The (11) Ga face, on the other hand, etches very slowly so that all imper- fections become delineated, resulting in a rough surface. This is also true for mechanical processes, where it has been observed that the (111) As face is more readily lapped than the (111) Ga face. At temperatures below 770°C, surface evaporation occurs more rapidly from the (111) As face, suggesting that the surface energy of atoms on this face higher than for the (111) Ga face. Differences in the evaporation rate are not observed above 800°C, where molecular dissociation, with an activation energy of about 112 kcal/mole (4.86 eV/molecule), dominates the process. Crystal oxidation occurs more readily on the (111) As face than on the (111) Ga face. Again, this is due to the higher electronic activity associated with the (111) As face, ‘The (111) planes of GaAs consist of alternate layers of group IIL and group atoms. These are differently charged, so there is a strong electrostatic attrac: tion between them. As a result, itis difficult to cleave Gads along {111 planes. ‘The situation for the {110} faces is quite different, since these contain an equal density of gallium and arsenic atoms. Each atom is attached by one bond to an atom in the lower layer; two bonds connect in the surface plane to two nearest neighbors, leaving a fourth dangling bond. Interatomic forces are thus strong, within the {110} planes, but weak between adjacent {110} planes. As a result, this is the preferred cleavage plane for GaAs. This situation is exploited in the fabrication of laser diodes made on {110} GaAs. Rectangular chips, with perfectly parallel faces, can be cleaved from this material because the {110} cleavage planes intersect the surface at right angles and along mutually orthog- onal directions. The (100) faces of gallium arsenide consist of either all gallium or all arsenic atoms. In either case, each atom is attached by two bonds to atoms in the lower 1.5 POINT DEFECTS =<3 layer, leaving two free dangling bonds. The properties ofthis face do not depend ‘on whether the face is made up of gallium ot of arsenic atoms. 1.5 POINT DEFECTS Localized defects of atomic dimensions, which can occur in an otherwise per fect crystal lattice, are called point defects. These include vacancies, intersti- tials, misplaced atoms, dopant impurity atoms deliberately introduced for the ;purpose of controlling the electronic properties of the semiconductor, and impu- rity atoms which are inadvertently incorporated as contamination during mate- rial growth or processing, ‘A study of point defects is important because most mechanisms for diffusion and crystal growth are defect-induced, Many defects are introduced during the actual act of device fabrication. Finally, all point defects (chemical or otherwise) alter the electrical properties of the semiconductor in which they are present. Consider, at first, the silicon lattice, Here the most elementary point defect is the vacancy. This is present when, as a result of thermal fluctuations, an atom is removed from its lattice site and moved to the surface of the crystal, which can serve as a sink, Defects of this type are known as Schottky defects and are associated with an energy of formation of about 2.6 eV and an enerey of migration of about 0.18 eV. Figure 1.17a shows schematically how such a defect occurs in an otherwise regular silicon latice. oP eee ceece oo ee o o C) Fig. 1.17, Point defectsUTS eS AA second elementary point defect that may be present in a crystal lattice is the interstitial. Such a defect occurs when an atom becomes located in one of the many interstitial voids within the crystal structure, Figure 1-17 shows schematically how this may occur in an otherwise regular crystal lattice, Tn silicon, which isa loosely packed erystal structure, the energy of formation of this defect is around 1.1 eV. A vacaney- interstitial pair, or Frenkel defect, occurs when an atom leaves its regular site in a crystal and takes up an interstitial position, as shown in Fig, 1L17e, This interstitial is usually in the vicinity of the newly formed vacancy, so that the energy of formation of Frenkel defects is comparable 10 that oF interstitial defects—that is, about 1.1 eV. Figure 1.18 shows the unit cell for the diamond lattice. Wi cell are the centers of five inertial voids, at $4,454, 5,433.3, 1,5, {fe}. Another three voids, with their centers locaied at the midpoint of each of the twelve cube edges (each is shared by four unit cells) add up to a total of eight voids per unit cell. Each of these is large enough to contain an atom (again assuming hard spheres), even though there is a constiction in passing from one void to another. From a purely geometric viewpoint, therefore, inter stitial defects can be expected to be quite common in silicon, Various combinations of these defects ean also occur. Thus a single vacancy is created by the breaking of four covalent bonds, whereas two vacancies, side by side, require the breaking of only six bonds. Consequently the energy of formation of a divacancy of this type is less than that requited to form two separate vacancies. The divacancy is thus commonly encountered. On the other hand, the di-intersttal is much more diffcul, if not impossible to form. The classification of point defects is somewhat more complex for the GaAs lattice, Here 1. Schottky defects may exist in the form of either gallium or arsenic vacan- ci 2. Either a gallium or an arsenic atom can be interstitally located in a void. As a result, there are two possible types of interstitial : 3. There are two kinds of Frenkel pairs, depending on the type of atom which itis displaced into a void. 4. It's possible for a gallium atom to be located on an arsenic site, or vice versa. These are known as antisite or antistructure defects. By the same token, the number of combinations of defects which can occur is much larger than for silicon. A detailed study of these possibilities is beyond the scope of this book. An important type of point defect is created by chemical impurities which are intentionally introduced into the lattice (dopants), or unintentionally in the form. of contamination. Impurity atoms that take up their locations at sites ordinarily © ners sites Fig. 118. Interstitial sites in the zincblende lattice. : a8 substintonal impurities, tema eccoped by lative atoms ae efemed . Gell ters impuies are located inthe many inertial voids that are preset in the late Substutonal impress usally el ies on the oer hand conductivity type Interstitial mpi, on i Suh not always tre, a notable exception being lium in silicon, which i inersial but behaves ikea donce stronically active and determine the wre usually inactive. 1.5.1. Thermal Fluctuation Effects v interstitials, Frenkel pairs, etc.) in a semi- ‘The defect concentration (vacancies, interstitial ) in a semi conductor is caused by thermal flactations in the material and by the vapor pressure of the species surrounding it, With silicon processing, vapor pressure effects are negligible, since the vapor pressure of silicon is only 10 * tor at 1100°C. It is for this reason that silicon processing can be carried ou ly in an open-tube environment. ; 7 The presnce of defects nthe moter changes both he itera ecey of the crystal as well as its entropy, Consequently thet equibsium concentration is a function of the energy of formation and of the equilibrium temperature.reese the other hand, the concentration of a chemical defect is primarily a function of the amount available for introduction into the crystal, and of its solid solubility The equilibrium concentration of Schottky defects in silicon may be deter. ‘mined on the assumption that all other defects can be neglected (27). Let ‘N= total number of atoms in a crystal of unit volume (=5% 10 silicon) number of Schottky defects per unit volume energy of formation of a Schottky defect—that is, the energy required ‘© move an atom from its lattice site within the crystal to a lattice site on its surface (= 2.6 eV). em” for The number of ways in which a Schouiky defect can occur is given by ee 1 ms (N~ iis)!ng! a ‘The entropy associated with this process is S= kIn(number of ways) ", depending on the position of the fermi level. 1.5.2. Vapor Pressure Effects ‘The situation with GaAs is quite different from that with silicon. Although this material melts at 1238°C, the surface layers decompose into gallium and arsenic long before this point is reached, The vapor pressures of these individual com-30 MATERIAL PROPERTIES Ponents are quite different, so there is a preferential loss of the more volatile species (arsenic). If processing is carried out in an evacuated ampoule, this arsenic goes into its volume until it establishes a sufficient partial pressure to prevent further decomposition of the GaAs, Although gallium and arsenic vacancies are generated by thermal fluctuations as well, the vacancy concentra. tion in this material will be dominated by vapor pressure effects so that thermal fluctuation effects can be neglected. In its vapor phase, arsenic consists of AS, Ass, and As,. All of these species are present, and in equilibrium over the gallium arsenide. Furthermore, some gallium in the form of vapor is also present. The partial pressure of these species is shown in Fig. 1.19 as a function of temperature [30]. Note that all of these curves are double-valued. The upper branch of the arsenic curves and the lower branch of the gallium curves are for conditions over GaAs which is preferen- tially rich in arsenic. In like manner, the lower branch of the arsenic curves and the upper branch of the gallium curves are for conditions over gallium-rich GaAs. Under processing conditions, GaAs will usually be gallium-rich, with pre- dominantly As) and Ass in the vapor phase. Note, however, that at tempera- tures below 637°C, the partial pressures of arsenic and gallium over GaAs are approximately equal. As a consequence, GaAs evaporates congruently below this point, with essentially no gallium or arsenic vacancy generation. In mol ular beam epitaxy, thermal cleaning of the GaAs is performed routinely under vacuum at about 600°C for a short period of time, to take advantage of this property (see Chapter 5). Mass-action relationships can be applied to solids in order to determine the role of vapor pressure in controlling the vacancy concentrations [28]. Consider the decomposition reaction and the vacancy formation reactions of GaAs. The decomposition reaction is GaAs(s) = Ga(g) + 4As,(g) (1.22a) assuming that Asp is the dominant arsenic species, For this reaction the mass- action law relationship gives k= PoaPis (1.226) where Pos and pa. are the pressures of Ga and As», respectively. Gallium vacan- cies are generally considered to exist as V2, and Vg, [31]. The formation reac tions for these are Gals) = VG, + Galg) (1.23a) Gals) = VG, + Galg) +h? (1.23) 1200 ree) vzxe /_1100 1000 900900 1} wk 10" wo 12 0 Pressre (tm) wo woe 107}- a Aca eam 080 Oso 10 108/71) i allium arsenide, as a func- Fig. 1.19 Partial pressures of gallium and arsenic over gall tion of temperature. From Arthur [30]. Reprinted with permission from the Journal of Physies and Chemistry of Solids Applying the mass action principle, ka = [VE,} Pon (24a) ky = pIVeqlPos (1.240) Combining these equations with Bq. (1.22b) gives O= HPht (1.25a) Wal= Pk ban ys 5 pe (1.25b) Wal hmsSeeeseeseee eee eases eee eee eeeeeeaSS so that [Weal = V8) + [Vel ky kan) op [Eta] es (1.26) Thus, the concentration of gallium vacancies is directly proportional to the square root of the arsenic partial pressure. Arsenic vacancies are generally considered to exist as V!, and V3, (311, Assuming that arsenic is in the form of As>, the formation reactions are As(s) = V8 + LAsi(g) (1.27) AS(3) = Vi + LAsi(@) +e" (1.270) Applying the mass action principle as before, we obtain Val WAI+IVAL = [bs ebed Jos a (1.28) where ks and kg are the equilibrium constants for Eqs. (1.27a) and (1.27), respectively, Thus, the concentration of arsenic vacancies is inversely propor. tional to the square root of arsenic pressure. Equations (1.26) and (1.28) can both be simplified when applied to extrinsic GaAs, where one of the terms can be neglected. Additionally, the product of the uncharged and charged vacancy concentra tions, (V&,JIV 4] and [VG,][V3,], is a function of ene ‘alone and is inde- pendent of the arsenic partial pressure. This interesting relationship is similar to the mp product in a material, which is also a function of temperature, and not of doping | Calculations for the arsenic and gallium vacancy concentrations in GaAs, Under equilibrium pressure conditions, have given : [Vea] = 3.33 x 1o'e Pat? (1.29) [ash = 2.22 x 10% 0747 (1.298) ‘These values must be considered as very approximate. Experimental data a 100°C indicate an uncertainty in [Va.] of less than a factor of 10 [32], No experimental data are available for the gallium vacancy concentration. (1.5 POINT DEFECTS: 4.5.3. Chemical Point Defects 'As mentioned earlier, point defects can also take the form of impurities which fre present in the semiconductor lattice, either introduced deliberately for doping purposes, or inadvertently as contamination during processing. They are also present as both dopants and contaminants in as-grown bulk material. ‘Chemical point defects of these types are located in substitutional as well as interstitial sites. As a general rule, substitutional impurities are electronically active whereas many contaminants are interstitial in behavior and are electron- ically inactive. Among impurities which are electronically active, donors and acceptors which have energy levels within 3&7 of the conduction and valence ‘band edges, respectively, are referred to as shallow’ impurities, and are used for doping purposes. They are fully ionized at room temperatures. Impurities which have one or more energy levels outside of this range are referred to as deep. Their presence in the semiconductor reduces its minority carrier lifetime, fand strenuous attempts are made to avoid their incorporation during microc cuit fabrication. In some cases, however, they are deliberately introduced for the purpose of reducing lifetime in high-speed devices. Silicon belongs to group IV of the periodic table; impurities from groups UI and V are substitutional in nature and are electronically active in it. A group V atom has an excess valence electron which does not enter into cova- Tent bonding with its four silicon neighbor atoms. Consequently, this electron is loosely bound, and is free to participate in the conduction process. Group V atoms thus behave as n-type impu ‘An estimate of the binding energy of this electron to its atom may be made by noting that a group V impurity can be represented by a nucleus with a single orbiting electron: that is, it is hydrogen-like in character. Elementary atomic theory shows that the energy levels of the hydrogen atom are given by mot eee 1.30a} Barnes om where ¢» is the permittivity of free space, his Planck’s constant, q is the mag nitude of the electron charge, and ai takes on the values 1,2,.... An equivalent situation can be considered for a crystal by replacing the mass of the electron With its effective mass (mi) and the permittivity of free space by that of the crystal, so that mi n (1.300) Ba°lP (ceo) where ¢ is the relative permittivity of the crystal ‘The energy required to remove an electron from the ground state of the hydrogen atom is 13.6 eV. This is known as the first ionization potential. Theva MATERIAL PROPERTIES: comparable value in a crystal would thus be 13.6 my, a «31 Eton = Assuming an effective mass ratio’ of about 0.6 and a permittivity of 11.8 for silicon gives an ionization energy of about 0,06 eV. This is relatively shallow, so that these impurities are almost fully ionized at room temperature. A group TI impurity has a hole (the absence of an electron) which is loosely bound to it. Using analogous reasoning, we arrive at a very similar figure for its ionization energy. Table 1.2 at the end of this chapter lists group IIT and V impurities in siticon, together with their ionization energies. All are seen to follow the arguments presented above, with the exception of indium, which is generally considered to be a deep impurity in silicon. ‘The above reasoning can also be applied to the behavior of impurities in GaAs, which is a group III-V compound semiconductor. Here, impurities belonging to group VI will usually be incorporated substitutionally. and on the arsenic sublattice, Consequently, each impurity atom of this type contributes ‘one loosely bound electron for conduction purposes: that is, it is n-type. In like ‘manner, impurities from group II are also substitutional, but are incorporated ‘on the gallium sublattice where they result in p-type conduction AAs with silicon, these impurities are shallow, and their ionization energies can be estimated by using the hydrogen model. The effective mass of holes in GaAs ism, = 0.5mo, so that the ionization energy for p-type impurities is approximately 0.045 eV. On the other hand, the effective electron mass under low-field conditions is much smaller (m’, = 0.067mg) so that the ionization energy for electrons is only 0,005 eV. As a result, n-type GaAs is degenerate at most useful concentration levels. Typically these n-type impurities are fully ionized, even at liquid nitrogen temperatures (77 K). Impurities from group IV (carbon, germanium, silicon, tin, lead) are usually incorporated substitutionally into GaAs, partly on each sublattice, depending oon the relative vacancy concentrations and site occupation probabilities [33] Group IV impurities will be n-type on the gallium sublattice, but p-type on the arsenic sublattice, The net free carrier concentration is thus less than the impurity concentration and is either n- or p-type, depending upon the conditions under which these impurities are incorporated. ‘The site occupation probability for impurity incorporation is strongly related to the conditions under which the material is grown. Thus, silicon incorpo- rates almost entirely as n-type during vapor-phase growth, which is carried out under highly nonequilibrium conditions. On the other hand, it can incorporate “This is roughly the average of the conductivity effective mass ratio and the density-of states cffeetive mass ratio, SEASEEeEAESEARTaSTEESETIESEIEESD 1 n- or p-type during liquid-phase epitaxy, which is carried out under con- Sitar approaching thermal equiv, This sivation is used @ advantage in the growth of successive n- and p-layers for the fabrication of light-emitting odes, using silicon as the dopant in both cases. Table 1.3 lists shallow impu- fities in GaAs together with their ionization energies and conductivity types Tn principle, a shallow impurity may exhibit more than one energy level for each of its charge states. Only one impurity level, however, is normally observed within the energy gap for shallow donors and acceptors. Additional levels, corresponding to the second and higher ionization potentials, have also been observed at low temperatures [34]. It should be emphasized that energy levels given in Tables 1.2 and 1.3 are not precise, but are reasonably accurate for moderate doping, concentrations. With heavier doping, these impurity levels broaden into bands. In addition, the impurity atoms come closer together (their average distance varies inversely as the cube root of the doping concentration), with a resulting decrease in their potential energy. AS a result, the activation energy of the impurity, measured as the minimum energy difference between the impurity level and the appropriate band edge, falls. Experimentally the activation energy can be fitted to Eq(N) = Ex(0) ~ a"? (132) where Eo(N) is the activation energy at a doping level of N impurity atoms em”, and Eo(0) is the activation energy at low doping levels. For boron and phosphorus in silicon, £o(0) values are 0.08 eV and 0.054 eV, respectively, and takes on the value of 4.3 x 10* eV em [35]. Thus boron-doped silicon and phosphorus-doped silicon are degenerate [Eo(N) = 0 eV] at doping levels in excess of 6.44 x 10!* and 1.98 x 10!* cm->, respectively. Similar considera- tions apply to acceptors in GaAs. As mentioned earlier, donors in GaAs are degenerate at most useful concentration levels. "The hydrogen model is an extremely elementary one. Indeed it is remarkable that it can predict the energy levels of shallow impurities with any degree of accuracy, but it cannot be extended beyond this point. Thus it cannot explain the ionization energy of indium (which belongs to group I) in silicon, oF of impurities from other groups in the periodic table. Doping with elements other than those from groups IIT to V of the periodic tuble often gives rise to a complex energy-level structure in silicon. In general these impurities exhibit more than one energy level, often of more than one type (ie., both donor and acceptor levels). Furthermore, these levels are usu- ally found quite deep in the forbidden gap. The effective mass theory described above does not apply t0 these impurities because their electronic wave fune tions are more highly localized than for shallow impurities [36]: The deliberate introduction of deep levels is sometimes done in order to reduce minority carrier lifetime in high-speed silicon microcircuits,A relatively simple model can be used to illustrate the general character of deep levels created by the introduction of these impurities into silicon [29]. Con- sider, for example, what happens when a monovalent impurity is introduced into 4 substitutional site. Such an atom, in the neutral state, has only one attached electron which provides covalent bonding with its neighboring silicon lattice atoms. When additional electrons are attached (0 it, it is successively transferred toa more and more negatively charged state. Each additional electron gives rise to a possible new energy level. Since these electrons are attached successively to more negatively charged atoms, it is probable that the value of the associ- ated energy level will continually increase in sequence until it goes beyond the edge of the conduction band. At this point the atom will lose this electron to the conduction band, resulting in no further identifiable energy levels. Finally, 4 monovalent impurity atom may lose an electron and be promoted to a pos. itive (donor) charge state. Based on the above arguments, it is reasonable 0 Postulate that the energy-level structure of a monovalent impurity atom may consist of as many as one donor level and three acceptor levels, progressively spaced in order of increasing negative charge. In most instances, only a few of these levels are identifiable within the energy gap. A notable exception is gold. in germanium, which exhibits all four energy levels. Similar considerations can be applied to the behavior of deep impurities in GaAs. Here, their energy levels will be progressively spaced in order of increasing negative charge, but will depend also on whether the impurity oceu- pies a vacant gallium or arsenic site. Again, only a few of these energy levels are seen for each specific impurity in practice. Associated with each charge state is a concentration, so that the solid sol- ubility of the impurity will depend upon the position of the fermi level in the semiconductor. Consider, for example, the situation with gold in silicon, which is known to adopt the charge states Au, Au, and Au’, For this impurity, Au! +e = Aw (1.33a) Au! +h = Aut (1.336) Applying the principle of mass balance, and writing k and ky as the equilibrium constants, gives Aun y= oom = Ae (1.34b) TAu'y Moreover, ky an (1.35a) ky * i (1.356) a") where the subscript é refers to concentrations in intrinsic silicon, ‘A typical device, in which there are multiple regions of different doping and impurity type, will have a spatial distribution of electric field. However, the equilibrium distribution of Au? will not be affected by this electric field. Rather, it will be set by the diffusion of gold into silicon from an external source. Hence, [Au] = [Av (1.36) Consequently, assuming an unlimited source, we have (Au = [Aw] + [Au] + [Au") (1.374) = tau") + [Au U2 + [aut 2 (1.37) rom Eqs. (1.37a) and (1.37b), itis seen that the solubility of an impurity with multiple charge states is a strong function of the background doping level of the semiconductor. ‘A further complication can arise with some impurities, which incorporate in a ‘more complex manner than described here. By way of example, experimental studies of gold in silicon have shown that about 90% incorporates in active substitutional sites, while the rest is neutral and interstitial. With platinum, about 90% is in active, substitutional sites: the remaining 10% is also active, but its exact lattice configuration is as yet unidentified. One possibility is that it forms active platinum-silicon complexes in silicon. With nickel in silicon, as much as 99.9% is inactive and in interstitial sites. Finally, we note that the fraction of an impurity which is active is also a function of the doping concentration. This is because the introduction of a dopant at high concentrations is usually accompanied by the generation of strain in the lattice, caused by misfit Impurities in both silicon and GaAs are sometimes incorporated in the lat- tice in the form of electronically active complexes. For GaAs, many impuri- ties exhibit energy levels which have been identified as being associated with impurity-gallium and impurity—arsenic pairs. It is also possible for an impu- Fity to combine with a vacancy, to form an electronically active defect. Oneexample of this type of defect is a deep acceptor in GaAs, which results from ‘the combination of a gallium vacancy and a shallow donor The ionization energies of some deep-lying impurities in silicon are also listed in Table 1.2. Many of these are present unintentionally in the starting ‘material. Table 1.3 shows this information for GaAs, A number of specific impurities are now considered, together with their characteristics 1.5.3.1 Impurities in Silicon Gold. Gold is of special importance in silicon technology, where it is commonly used for minority carrier lifetime reduction in high-speed digital Circuits [37]. It is also used for the control of lifetime in semiconductor power devices. Ithas a solid solubility of 2 10" atoms em, and can be incorporated in large concentrations into silicon without the formation of any complexes. It exhibits both a donor level at E. - 0.76 eV, and an acceptor level at £; +057 eV, depending on the particular charge state in which itis incorpor- ated. It is commonly referred to as an amphoteric impurity because of this roperty. Platinum. Platinum is increasingly used as a substitute for gold in silicon (38), About 90% of it is incorporated into substitutional sites, where it exhibits an acceptor energy level at E, +0.92 eV, and a donor level at E, 0.85 eV. The Femaining platinum is believed to be in the form of an electronically active complex, and behaves as an acceptor at E, +0.42 eV. Its capture cross section is extremely large, and accounts for most of the lifetime reduction properties of this dopant, ‘The energy levels of platinum in silicon are highly asymmetric with respect {0 their location in the energy gap, and they result in very different lifetime Characteristics from those obtained with gold in silicon. In particular, the space charge generation lifetime in platinum-doped devices at room temperature is many hundred times longer than the low-level lifetime. Thus platinum doping can reduce low-level lifetime in the neutral regions of a diode without a comparable increase in its leakage current. In contrast, a direct consequence of the symmetrical location of the gold acceptor level is that leakage current in Pon diodes is inversely related to the lifetime in the neutral regions Oxygen. Silicon is commonly grown in silica crucibles, so that a large amount of this impurity is usually present. Depending on the erystal growth technique, this ranges from 10° to over 10'* cm”, The dissolved oxygen is mostly in interstitial sites, and can be identified by a characteristic absorption peak at 1107 cir’ ' (9.1 um). About 0.1% of this oxygen can be converted ito an active Si-O complex during heat treatment [39] at low temperatures (400 500°C) This complex is donor-like and has been tentatively identified as SiO,. It disappears with processing at higher temperatures and can be eliminated by a {650°C anneal for as litle as 20 min, followed by quenching. However. extended 1.5 POINTDEFECTS 39 heat treatment at this temperature can result in the formation of a new donor, especially in crystals with a high carbon content, the concentration of dissolved oxygen in silicon is given [40] by 0; = 55x 10% 68 4T (1.38) This is far above the solubility limit at integrated circuit processing tempera- tures. AS a result, during device processing, most of it combines with silicon, and precipitates in the form of hexagonal platelets of SiO,, typically 1 xm across and | jm apart [41]. Although inert, their presence distorts the potential lines in the depletion layer of p-n junctions. This results in premature break- down and “soft spots.” Carbon. Carbon has a high solid solubility and is often incorporated in silicon in the 10! to 10"*-em”* range, during its chemical purification process. Its presence is indicated by an infrared absorption line at 603 m-> (=16.7 pm). It is electrically inactive, and forms silicon-carbon complexes in the form of microprecipitates. Again, its presence in high concentrations leads to premature breakdown of pn junctions. A number of metal—carbon complexes have been reported in the literature as well [42]. In addition to those listed in Table 1.2, a number of other deep levels have bbeen reported in the literature, but there is litle agreement concerning their positions and concentrations. Many have been attributed to oxygen complexes with other impurities such as copper, cobalt, and nickel 1.5.3.2. Impurities in Gallium Arsenide resent in the form of complexes ‘Many impurities, both shallow and deep, are present in th with gallium or arsenic. Both active and inactive complexes have been identified in GaAs, and little is known of the manner in which they are incorporated into the lattice. A number of specific impurities are now considered briefly, together with some of their characteristics: Selenium and Tellurium. Both are n-type and located on the arsenic sublattice. At high concentrations they tend to form compounds with gallium (GaSe) and GayTe;) which are inactive. Evidence of complexes with gallium vacancies have also been observed Tin. Although belonging to group IV, tin is almost always n-type in lium arsenide which is grown by chemical vapor transport processes (see Chapter 5). Tin is located on both types of lattice sites, with an increasing fraction incorporated on arsenic sites at high concentration, Thus, its electron, concentration varies sublinearly with the tin concentration. Tin-doped GaAs, grown by liquid-phase epitaxy, exhibits a shallow donor level,‘40 MATERIAL PROPERTIES Rare Earths. Interest in doping with rare earths comes about because they exhibit extremely narrow emission lines.. This is true, regardless of the semiconductor in which they are introduced. Erbium is of commercial importance as a dopant in GaAs because its level corresponds to 1.54 um, the wavelength at which silica fibers have minimum optical transmission loss [43]. Its solid solubility in GaAs is around 3 x 10" em* Silicon. This is also a group IV element, and is incorporated on both sublattices. It is of special importance because its relative incorporation can be readily controlled in liquid-phase epitaxy to give either p-type GaAs by Jow-temperature processing, or n-type GaAs by processing at high temperatures (see Section 2.2.5). It is used extensively as a dopant in (a) vapor phase epitaxy, (b) molecular beam epitaxy, and (c) ion implantation, where it behaves n-type. Silicon is present in all GaAs as a contaminant. Often it is in the original materials from which it was made, Processing in silica vessels is also an important contributory factor. The background concentration of undoped GaAs is thus critically dependent on how this contaminant is incorporated into the lattice. Both growth temperature and arsenic overpressure play an important role here, since they determine the relative vacancy concentrations, and hence the incorporation of this impurity. In addition, silicon—oxygen complexes, with the silicon on gallium sites and the oxygen as an interstitial, have been identified [44] as the cause for a number of doping anomalies in GaAs. Carbon. This is also present as a contaminant in GaAs, Although belonging to group TV, it has been observed as a shallow acceptor and as a deep donor, at concentration levels as high as 8 x 10 cm, It incorporates. readily during growth by organometallic vapor-phase epitaxy [45], where it exhibits exclusively p-type behavior. Copper. Copper is a deep, triple acceptor (46] in GaAs. It has a high solid solubility (6x 10" cm~) and moves extremely rapidly, even at relatively low Processing temperatures (300—400°C). It is often present as a contaminant, and is very effective in reducing the diffusion length of n-type GaAs. Chromium and Iron. Chromium behaves as a single acceptor, with an impurity level that is extremely close to the center of the enerey gap. It is used during crystal growth to intentionally counterdope n-type GaAs to make it semi-insulating (SI) with a resistivity of as high as 10? Q-cm, This makes it of ‘great importance technologically, since it permits the possibility of using GaAs as an insulating substrate on which active layers of doped GaAs can be grown, The incorporation of chromium in GaAs during crystal growth is covered in detail in Chapter 3. Chromium-doped, SI GaAs has been extensively studied in recent years, It has been found [47] that only some slices of this material retain their ST Properties upon heat treatment, while others do not. This behavior is related 15 POINTDEFECTS 41 to impurities which are initially present in the material, in addition to the chromium. Stable SI GaAs requires a low background concentration of these impurities; this, in turn, permits the use of low concentrations of chromium for counterdoping purposes. Iron can also be used for making SI GaAs. However, because it has no midgap energy levels, the highest resistivity obtained with this impurity is 4x 10' Q-cm. ts solid solubility is in excess of 10!” em”. Oxygen. Oxygen can best be described as a problem contaminant, It exhibits two levels in the energy gap, one at E,—0.14 eV and one at E, — 0.57 to 0.75 €¥, and has a solid solubility in excess of 10"” cm”? [48]. Its presence in n-type GaAs results in raising the resistivity of material, until SI behavior is achieved with a resistivity on the order of 10° 2-em. This is somewhat surprising, since the fermi level in this material is well above the oxygen donor level. A generally accepted theory for this behavior is based on the fact that undoped, n-type GaAs contains silicon as the primary donor contaminant. Incorporated oxygen combines with this silicon to form inactive silicon-oxygen complexes, thus tying up this donor so as to shift the material toward p-type. This in tum allows the remaining oxygen to become ionized and moves the fermi level toward the center of the gap. Oxygen-doped, SI GaAs has a relatively high mobility (4000 em? /V s), which is not what would be expected in a highly compensated material. This would lend strength to the above arguments. Oxygen cannot be used for making SI GaAs, since it is highly mobile at processing temperatures. Its real importance lies in the restrictions it places on the thermal processing of GaAs in an open-air ambient. Such processing poses the ever-present risk of converting the material inadvertently to high resistivity This is perhaps the primary reason why many of the simple thermal processes available for silicon are not possible with GaAs. Finally, it is worth noting that GaAs can have in it many inactive impurities which have only a slight effect on the mobility or the free carrier concentration, ‘Thus high-purity GaAs, with a free electron concentration of 10!=10" em, ‘can contain as much as 10"°10'7 atoms cm of carbon and oxygen, in addition to such impurities as aluminum, calcium, potassium, nitrogen, strontium, and {tantalum in the $10!°-cm”* range. These impurities are generally interstitial, or form complexes which are electronically inactive. 1.5.4 Contamination Control Chemical point defects, in the form of undesired impurities, can be incompo- rated inadvertently during every microcircuit fabrication step. As a result, the avoidance of these impurities is of prime consideration, and is a continuous Part of the fabrication process. The use of ultrapure, “semiconductor grade” Starting chemicals and substrates, and the conduet of processes under clean room conditions, is aimed at achieving this goal. Nevertheless, impurities do getSe MATERIAL PROPERTIES incorporated during this process. As noted above, these usually behave as deep levels, and contribute to phonon-assisted recombination in both GaAs and sil- icon. In GaAs, the minority carrier lifetime is dominated by radiative processes, and is extremely short, typically in the 10- to 100-ns range. The presence of these impurities reduces it further, and affects the current collection efficiency of detectors and solar cells. It also deteriorates the performance of light-emitting diodes and lasers, since recombination via these impurities is usually nonradia- tive. Silicon is an indirect gap semiconductor, in which the lifetime is large, often in the 500 us range. Here, the presence of deep impurities significantly reduces the minority carrier lifetime and degrades the performance of devices such as bipolar transistors and solar cells. It also reduces the refresh time of storage diodes used in dynamic random access memories. ‘The metal-oxide-semiconductor (MOS) transistor is a majority carrier device, so that its transport properties are not affected by the presence of impurities. However, the leakage current of the source and drain regions of these devices increases with the concentration of these deep-Iying impurities. Th problem in VLSI applications, since it increases the standby power dissipation in these devices and limits the number of devices which can be operated on single chip. As a result, special attention must be taken to minimize the con- centration of these impurities ‘As mentioned earlier, almost every chemical impurity outside of groups IIL and V of the periodic table exhibits one or more deep impurity levels in silicon. Some are present as contaminants in as-grown silicon. Yet others are introduced into silicon as trace impurities in the chemical solutions and transport gases. Some impurities are present in large quantities in the air, in glassware, in dif- fusion tube liners, and in the quartz diffusion tubes themselves. The amount of these impurities that is incorporated into the silicon depends on the processing time and temperature involved and on the diffusion-induced stress. Thus con tamination problems are most severe with deep-liffused, heavily doped strue- tures. Almost all deep impurities diffuse primarily by an interstitial mechanism and move rapidly through the slice at processing temperatures. Their diffusivity is typically 5~6 orders of magnitude higher than that of substitutional impurities such as boron or phosphorus. During processing, they tend to condense around dislocations so as to form metallic precipitates, which can cause distortion of the potential lines if they are located in the depletion layer of a p-n junction, leading to localized regions of high electric field through which excess leakage ‘current flows. Thus a second consequence of deep impurities is that they “deco- rate” dislocations, and give rise to “soft” spots and “soft” breakdown character- isties with excess reverse currents at voltages below their avalanche breakdown value. The elimination or reduction of these precipitates leads to improvement in the sharpness of the reverse characteristic, as well as to improvement in the ‘minority carrier lifetime of the material ‘The most straightforward approach for lifetime improvement is to use clean SaensEeTTnESETEEETEEEEEESEEETES processing, to minimize deterioration of the original lifetime of the as-grown silicon. Sealed tube diffusions, for example, are almost exclusively employed for the formation of deep p-diffusions in silicon high voltage power devices. Diffusions of this type invariably result in junctions with long lifetimes and hard reverse characteristic ‘The deliberate manipulation of clusters and deep impurities away from active regions presents a powerful altemative technique for their reduction by a pro cess known as damage gertering. Here, the strategy is to create a region of damage far from the active device; upon subsequent heat treatment, rapidly moving impurities segregate in this region in order to relieve the strain created by this damage. Sandblasting or otherwise abrading the back surface has been used with both silicon and GaAs [49]. This results in the formation of an almost infinite supply of vacancies. During high-temperature processing, these vacancies act as sinks for fast-moving deep impurities that diffuse throughout the slice. Controlied amounts of damage can also be introduced by the use of deposited films, such as layers of silicon nitride [50], on the back surface of the wafer. Here the high interfacial stress created by the deposition process results in the formation of a dislocation network, toward which it is desired that deep impu rities migrate, Polycrystalline silicon can be used for the same purpose, and has the advantage of being extremely pure compared to other deposited materials, Ton implantation of heavy neutral species such as argon has also been explored as an altemative technique for producing the desired surface damage [51, 52]. A disadvantage of this method is that the damage anneals out with subsequent high-temperature processing, so that its benefits are relatively short- lived. Impurities of special concem in silicon processing are copper. iron, and gold [53]. All diffuse rapidly through the silicon lattice, and have reasonably large solid solubilities and capture cross sections. In contrast, other impurities tend to form inactive complexes and to have extremely low values of solid solubility. Both copper and iron diffuse by a rapid intersttial-substitutional mecha nism, but ultimately take up substitutional sites by combining with vacancies, Morcover, since their substitutional solid solubility is lower than their int stitial value, they freeze out upon cooling.and tend to condense around dislo- cations. Once there, however, they may either remain in the slice or Teave by out-diffusion, The vapor pressure of copper is 15-20 times higher than that of iron. Consequently, nearly allthis impurity leaves by out-diffusion, On the other hand, there is litle out-diffusion with iron; typically, about 33% segregates in this layer of dislocations, the rest being retained in the bulk. Gold moves primarily by an interstitial-substitutional mechanism and also takes up substitutional sites in the lattice by combining with vacancies. Unlike copper and iron, the solid solubility of substitutional gold is much higher than that ofthe interstitial species; thus it remains in solution upon cooling. Further- more, since gold does not form compounds with silicon, it does not segregate by this processMATERIAL PROPERTIES: Layers of borosilicate (BSG) and phosphosilicate (PSG) glasses, in contact with the silicon at elevated temperature, are extremely effective in removing and the energy associated with itis infinite. In practice, however, crystals usu- ally contain many dislocations, randomly distributed. As a result, their strain fields are also randomly distributed and cancel each other at distances approxi- mately equal to the mean distance between them. In typical crystals, R, is about 10° atom spacings. The inner radius limit R; is set by the fact that a region of atomic dimensions can no longer be considered as an elastic continuum, and the theory of elasticity ceases to hold. As a consequence, it is reasonable to eliminate the inner 4-5 atoms from consideration. Practical values of the ratio Ro/R; are usually taken around 10%. Using this value, the strain energy for a screw dislocation in silicon may be calculated as about 10-19 eV/atom length. (By way of comparison, values for aluminum and diamond are 3.1 and 29 eV, respectively.) 1.6.2 Edge Dislocations ‘An edge dislocation is shown in Fig. 1.22. Here an extra half-plane of atoms, ABCD, is present in the otherwise regular lattice, with most of the distor- tion concentrated around the line AD. A dislocation of this type is created by applying a shearing force along the face of the crystal, parallel to a major crys- tallographic plane. When this force exceeds that required for elastic deforma- tion, the upper half of the crystal moves by a slip mechanism. The plane along which slip occurs is commonly referred 10 as a slip plane. The strain energy associated with an edge dislocation is given [59] by Bel Ro Ey [tr l(# =) aa) where ¥ is Poisson’s ratio (=0.3 for both silicon and GaAs), Its magnitude is, thus approximately 50% larger than that for a screw dislocation,48 MATERIAL PROPERTIES: Fig. 1.22 Edge dislocation, In view of the large energies of formation for both basic dislocation types, it must be concluded that their equilibrium concentration is negligible. They ‘cannot be created by purely thermal means, since the thermal energy associ ated with processing temperatures as high as 1500 K is under 0.15 eV (2347), Rather, mechanical forces, induced during thermal processing, are the driving forces behind the generation of these dislocations 1.6.3 Dislocation Movement and Multiplication Figure 1.23 indicates the manner in which an edge dislocation may move com- pletely through a crystal. The mechanism for such a movement is called slip Its a characteristic of the slip mechanism that it results in movement along planes of high atomic density where opposing forces are at a minimum. The displacement of a screw dislocation also takes place along a slip plane In Fig. 1.20 this slip plane is given by ABCD. The end result of such a dis- placement is identical to the movement of an edge dislocation, even though the strain pattem is different. In addition to slip, climb is an altemative method by which a dislocation can move in a crystal. For an edge dislocation, such as that shown in Fig. 1.22, climb of the plane ABCD takes place at right angles to the slip plane EFGH. Figure 1.24 shows that this may occur as the result of the movement of either substitutional or interstitial atoms out of the plane ABCD. Altematively, climb ‘16 DISLOCATIONS 49 @ © 1.23 Crystal movement along a slip plane. ‘may also occur by atoms moving into the plane. Intuitively, it is seen that the energy of formation associated with such a process is on the sume order of ‘magnitude as that for the energy of migration (=0.18 eV) of a point defect. In fact, it is somewhat less, since the migration of these atoms is aided by the stress field surrounding the dislocation, Climb in a screw dislocation occurs by @ complex motion, Here the screw dislocation line twists itself into a helix, which can then climb, The actual move- ment of dislocations in a crystal is made up of combinations of these and other types of movements. ‘The energy of movement of a dislocation has been shown to be 0.15 eV/atom spacing for silicon and somewhat less for GaAs. This is the energy barrier that ‘must be overcome in order for a dislocation to move in a crystal. A comparison, with the energy of formation of a dislocation (about 10-19 eV) shows that itis Fig. 1.24 Climb of an edge dislocation50 MATERIAL PROPERTIES extremely easy t0 induce dislocation motion in a erystal by thermal means, even though its almost impossible to create a dislocation in this manner. Thus one of the more important problems of crystal growth and device processing is to avoid (or minimize) the formation of dislocations in the first place. Alternatively, if such dislocations are unavoidable, they can sometimes be relieved by annealing. During crystal growth, techniques are available for inducing these dislocations to grow out of the crystal, leaving behind a relatively dislocation-free lattice. There is considerable evidence indicating that dislocation multiplication occurs in a crystal in addition to dislocation movement. Examination of deformed crystals has shown that this is indeed the case, and various mech- anisms have been suggested for this multiplication. Figure 1.25 shows a model for the Frank-Read mechanism by which this can occur [60]. Consider a dis- location, as shown in Fig. 1.25a. Under the application of a force F, the dis location tends to expand along its length by climb. If, however, it is pinned at xy, possibly by the presence of some obstruction such as an oxygen or metallic cluster, it will tend to bow out of its slip plane, as shown in Fig. 1.25b. In doing 50, it becomes longer and requires a greater force to maintain its new radius. A critical condition is reached at which the dislocation line becomes semicireular, For a force in excess of that required for this condition, the dislocation becomes unstable and progresses as shown in Fig. 1.25¢ and d. Eventually it returns to its original form by the collapse of the cusp, as shown in Fig. 1.25e, leaving an expanding loop in addition to it. The provess now repeats itself, resulting in multiple dislocation loops from a single dislocation source of this type. A iP o @ © Fig. 1.25 Mechanism for dislocation multiplication, 1.8 DISLOCATIONS 51 conclusion to be drawn from the above is that the presence of insulating and ‘metallic clusters in the semiconductor should be avoided, since they can lead to dislocation multiplication in the presence of thermally induced stress. On the other hand, the presence of clusters in a material ean also serve to harden it, as is the case for SiO) in silicon. As a result, a balance must be struck between these extremes. 1.6.4 Process-Induced Dislocations As-purchased single-crystal silicon has a dislocation content which is below the measurement limit, and can be essentially considered to be dislocation- free. GaAs is somewhat poorer because of its combination of relatively low critical resolved shear stress (7.75 x 10° dyn cm”? as compared to 3.61 x 10” dyn cm” for silicon) and is typically available with 5000 dislocations em-? at the present time, In both these materials, the energy of formation of dislocations is so large that it is extremely difficult to form them by purely thermal means. However, many conventional processing steps, especially those involving high impurity concentrations, can lead to the formation of dislocations. These must form closed loops, or else terminate on the crystal surface where the microcir- cuit is fabricated. This, in tur, can affect the performance of the circuit. A few of the common causes for dislocation formation are now considered, but the list is by no means comprehensive. ‘The diffusion of an impurity will introduce stress in the crystal lattice, whose magnitude is related to the misfit factor and to the impurity concentration. Both lattice contraction or dilation can occur, depending on whether the tetrahedral radius of the impurity is smaller or larger than that of the semi- conductor, respectively. Diffusion-induced dislocations will occur if this stress exceeds the elastic limit of the semiconductor. In silicon technology, boron Presents a serious problem because of its combination of large misfit factor (€ = 0.254) and its high solid solubitity (2.5 x 10° em”? at 1100°C). Diffusion at this temperature creates a stress which is seven times larger than the elastic limit of silicon (=1 x 10° dyn cm?) and results in damaged material, with a high dislocation content. on implantation, where substrates are subjected to high energy bombard- ‘ment, is another source of these dislocations. Their complete removal can only be accomplished by subsequent annealing at temperatures within a few hundred degrees of the melting point of the semiconductor. Annealing at lower temper- atures results in varying degrees of effectiveness, depending on the nature and extent of ion damage. Rapid removal of a slice from a fumace causes its edges to cool faster than the center. This results in both radial and tangential stresses. which are pro- Portional to the temperature gradient, and dislocations are generated when this stress exceeds the critical resolved shear stress (CRSS) of the semiconductor. This problem is avoided by slow heating and cooling of the semiconductor52 MATERIAL PROPERTIES during thermal processing. It is of special concem during rapid thermal pro- cessing. An important process in silicon technology is the growth of an oxide on the substrate by means of its thermal oxidation (see Chapter 7). Conversion of the silicon to silicon dioxide in this manner results in a volume change by a factor of 2.23. This fact, combined with the difference in coefficients of thermal expansion of these materials, often results in the formation of dislocations in the silicon during the cool-down process. Moreover, it can cause cracking of the oxide film and thus a toss of its masking properties. In practice, the oxide film thickness is kept as small as possible in order to avoid this problem. ‘The deposition of thin films of materials such as silicon dioxide and silicon nitride, which are often used for masking purposes, also results in strain in the underlying conductor. The actual amount of strain and its sign (tensile versus compressive) is related to the deposition parameters. This is especially true for silicon nitride films which are frequently grown by the reaction of silane and ammonia in a hydrogen plasma. Here, both system pressure and reac- tant composition can affect the magnitude and sign of the residual strain in the film. Highly localized stress can be introduced in both grown and deposited films when windows are cut in them to delineate regions for selective processes such as regrowth, diffusion, and ion implantation. This stress occurs in the comers of the windows, and results from stress relief over the rest of the region. Here too, the stress generally increases with film thickness. Thus, it is prudent practice to make masking films as thin as possible. ‘Thin metal films, deposited at room temperature by vacuum evaporation or sputtering, often have a built-in stress. The magnitude and sign of this stress depends upon the nature of the film growth process, and on the material itself. Subsequent processing can further alter the stress atthe interface. For example, ductile aluminum, if excessively heat-treated in contact with silicon, forms an extremely strong alloy which places considerable stress. on the underlying semiconductor during device fabrication, and with subsequent thermal cycling during device operation The above are only a few of the processes which can result in the forma- tion of dislocations in the semiconductor. In all cases, an understanding of the problem can generally indicate the direction for its partial or total relief Dislocations can also be generated during device operation. During electron— hole recombination, for example, one of the methods by which excess energy is released is by its transference to the lattice in the form of phonon vibra- tions. This excess energy can often increase the rate of defect reactions. For ‘example, in GaAs lasers and light-emitting diodes, dislocations are a source of nonradiative recombination, Rapid degradation of these devices has been traced to the enhanced motion of these dislocations by a climb process, when they are operated at high optical power densities (61]. Additionally, this rapid movement leads to the development of networks of dislocations, which originate preferen- tially at hetero-interfaces, Many studies of these dark line defects have shown 1.7 ELECTRONIC PROPERTIES OF DEFECTS 53. an increase in the dislocation velocity in the presence of optical irradiation. Moreover, it has been established that they develop rapidly in material with a high initial density of defects {62]. Thus, solution of this problem lies in the use of high-quality starting substrates, and processing techniques which do not result in the production of dislocations. 1.6.5 Two-Dimensional Defects ‘Two-dimensional defects can be created at the boundary separating an error in the stacking sequence in a crystal. Defects of this type are known as stacking faults, Usually, these faults are decorated by fast-moving impurities which cluster around them. This leads to enhanced leakage current if the fault is in the vicinity of a pn junction Twinning is a gross form of two-dimensional defect that may occur in a crystal. Its presence is usually indicative of material that has a high dislocation content and is not suited for device or microcircuit fabrication. Experimental evidence shows that excessive twinning is encountered if the material is physi- cally restricted during its growth from a melt. Thus crucible-grown materials are highly prone to this defect, since it is difficult to prevent sticking of the semiconductor to the walls of the crucible. Twinning occurs when one portion of a crystal lattice takes up an orienta- tion with respect to another, the two parts being in intimate contact over their bounding surfaces. This bounding surface is called the twinning plane. Figure 1.26 shows a two-dimensional representation of twinned and untwinned parts of a crystal. For this case, atoms along xx” are common to both twinned and ‘untwinned sections, and the twinning plane is sometimes referred to as the com- position plane. Finally, the surface of a semiconductor represents an important two-dimen: sional defect, since it is a discontinuity in an otherwise reasonably periodic lattice. This is true for an ideal, atomically clean surface with dangling bonds, as well as for the practical case where surface bonds are terminated by an inter- facial layer or by contaminants. The electronic properties of this region have a strong inffuence on microcircuits which are essentially surface-oriented in char- acter. 1.7 ELECTRONIC PROPERTIES OF DEFECTS The deliberate insertion of chemical defects into the semiconductor lattice is the basis for the fabrication and control of electrical properties of semiconductor devices and microcircuits. This subject has been discussed in Section 1.5.3 However, atention must also be paid to the electronic behavior of defects that are intrinsic to the erystal and to complexes of these defects with impurities.(54 MATERIAL PROPERTIES: 1.7.1 Point Defects In silicon the presence of a vacancy in a crystal results in four unsatisfied bonds which would ordinarily be used to bind the atom to its tetrahedral neighbors. ‘Thus a vacancy tends to be acceptor-like in behavior. The addition of each electron to this vacancy results in successively higher values of energy level because of the large mutual electrostatic repulsion present between them. It is highly improbable, however, that such a vacancy will exhibit as many as four energy levels within the band gap. One acceptor level at Ey + 0.54 eV and a second acceptor level at B, + 1.0 eV have been positively identified in silicon by a number of workers. A donor level at Ez ~ 0.98 to 1.06 eV has also been identified and is considered to be due to a distorted bond configuration. In like manner, an interstitial has four valence electrons that are not involved in covalent binding with other lattice atoms and which may be lost to the con- duction band. As a result, it should exhibit donor-like behavior, and one or more levels within the energy gap. A singly ionized donor level, at about E--0.71 eV, and a singly ionized acceptor level, at about Ey +0.62 eV, have been identified here. Many complex vacancy-interstitial combinations are also electronically active in silicon, For example, electron irradiation in the 1- to 2-MeV range gives rise to four energy levels at £,+0.27 eV, Ee —0.23 eV, Ee—0.17 eV, and E,—0.41 eV [63]. Annealing for 36 h at 300°C alters the defect structure, with the last two levels converting to one level at E- ~ 0.36 eV. The energy levels associated with vacancies and interstitials in silicon are deep. They serve as localized centers for minority carrier recombination, and result in a fall inthe lifetime. In general there is an inverse relationship between the concentration of these levels and the minority carrer lifetime. This has been verified by numerous experiments on material with as-grown defects as well as with induced defects (by electron and nuclear radiation, and by plastic deforma- tion techniques). In fact, the deliberate introduction of deep levels into silicon by electron irradiation provides a promising technique for controlling lifetime in high-power semiconductor devices. Intrinsic defects in GaAs include both arsenic and gallium vacancies, their concentrations being determined by the overpressure of arsenic during pro- cessing. Many workers have considered these defects to be neutral (64). How- ever, it has been established that, in addition to being neutral, arsenic vacancies behave as deep donors, whereas gallium vacancies exhibit deep acceptor-like behavior [65] Many other intrinsic defects are also observed in GaAs, with their nature and concentration being a function of the manner in which the material is grown [31]. The majority of these tend to thermally anneal out by 250°C. A notable exception is the antisite defect, Asc,, which is stable to 950°C. Some of these defects are listed in Table 1.4 at the end of this chapter. Intrinsic defects also occur in the form of complexes with other intrinsic defects, as well as with impurities. Yet other defects take the form of impurity pairs, which result from the presence of residual impurities in the GaAs. the Gane at defec-impurty complex i the glum vacaney-shllow donor pair (V,-donor), which behaves as a deep acceptor [66], It oceurs with Ail group IV ‘and group VI shallow donors, and is identifiable by a broad photoluminescence signal centered around E —1.2 eV [67], Itis believed that the gallium vacancy is an ionized acceptor, and that the donor atom is bound to it by coulombic forces in this complex. One consequence of the presence Of this center is that the free carrier concentration in n-type GaAs is gener- filly less than the dopant concentration, so that the materials compensated U6 ene el of many ofthese comple ae aio Hedin Table 1 COfien, these levels have been identified by photoluminescence, and their impu- rity type is unknown ‘An important defect in GaAs, commonly called EL2, is present in material which is grown from an arsenic-rich melt, and is considered to be an Ascu-Vas Complex. This defect is donor-like in character and is located at E, ~ 0.76 eV’ that is in the middle of the energy gap [69]. It is highly stable, and can with- stand thermal processing at temperatures above 900°C. It has electron and hole Capture cross Sections of 1.5% 10°! em? and 2x 107 em, respectively, that is, itis an electron trap, EL2 is of great technological importance, because it can convert p-type GaAs to semi-insulating material, and is widely used for this purpose because of its thermal stability. Its properties and manner of incorporation are described in Chapter 3. 1.7.2 Dislocations Many of the electronic properties of dislocations are similar to those of an ensemble of point defects, Thus there is considerable evidence to show that dislocations in silicon are acceptor-like, because of the presence of dangling {or unfilled) bonds at the edge of the half-plane comprising the dislocation. Fig. 1.26 A twinned structureHowever, itis possible to obtain a diffusional rearrangement of the atoms which reduces the formation of dangling bonds of this type [70]. This would explain the absence of strong acceptor-like properties for these dislocations, The behavior of dislocations in GaAs is not firmly established. As noted ear lier, they serve as recombination centers, and greatly lower the internal quantum efficiency in light-emitting diodes and lasers. Their presence results in acceler. ated degradation of laser devices. Dislocations take the form of a line of defects, with an associated distortion of the energy-band structure in their vicinity. Thus they behave as anisotropic scattering centers for carriers because of the extended space charge region sur- rounding them. Furthermore, this distortion of the enerey-band structure leads to the formation of trapping sites for free holes and electrons, and a concurrent reduction in minority carrier lifetime, in proportion to their concentration, ‘The most important property of a dislocation is that it interacts with chemical and other point defects in its neighborhood. This interaction exists between the localized disturbance, due to impurity atoms, and the strain field in the vicinity of the dislocations. Its extent is directly proportional to the misfit between the impurity and the lattice atom. Thus the presence of a dislocation is usually asso- ciated with an enhanced rate of impurity diffusion in its neighborhood, leading {o the formation of diffusion pipes. Often the presence of the dislocation results in the segregation of metallic impurities in its vicinity. Taken together, they lead to such problems as excessive leakage and premature breakdown in semicon- ductor junctions made on this material 1.7.3 Two-Dimensional Defects The twinning plane in a crystal is a two-dimensional region with a large con- centration of broken, or unsatisfied, bonds. This region is known as a grain ‘boundary, and the actual number of such broken bonds is related to the angle of the grain boundary. This is shown in Fig. 1.27 for a symmetric grain boundary with an angle 0. If d is the atomic spacing, the distance between broken bonds is given by a 2sin(@72) (1.43) 1f0 © 5°. this distance is on the order of 211 lattice spacings. This is comparable to the lattice spacing for dopant atoms with a concentration of 3.3% 10" cm”. As a result, a crystal having a fow-angle grain boundary of this type can still be Considered as a coherent structure. The term lineage is used for grain boundaries where @ < 1°. Here any loss in coherency due to this type of grain boundary can be ignored, 1.7 ELECTRONIC PROPERTIES OF DEFECTS = S7- at 1.27 Model for a tow-angle grain boundary lat stig fas ston have bean snw exit sized sates st Eon e and a E03 e¥ Usually hs tate dese ih fs roving impurities, whose effect dominates the electrical behavior ofthe device. fn pely snr cones, Hane own ha fsy ested semicon sac exis amr of dpi eve thoughout cna gop (0 Tee ae de oe presence of wate Covalent bon a ae acer‘ n charter, na ate sas many oe both ae emit with ail eae of te aie, This et a eduction in the densiyof deep levels, and alles thei istbuin i the cnersy gap [26] The detailed nature ofthese surface states is covered in Chap ter 7.6s TABL Property Crystal Structure Lattice constant (A) Distance between neighboring atoms (A) ‘Atoms or molecules (em~3) Atomic or molecular weight Density (g em~) Dielectric constant Refractive index (A = 2m) Infrared refractive index felting point (’C) ‘Thermal coefficient of expansion (K~!) Intrinsic carrier concentration (om Effective density of slates Valence band (cm) Conduetion band (em Effective mass electrons Holes Heavy Light Splitoft Electron mobility (em? / Vs) Hole mobility (em? / V5) “Thermal conductivity (W/om'C) Spectic heat /e°0) Silicon Diamond 5.43086 2.35163 4.99441 x 1022 28.0855 2328 "7 3.45 1412 2.33 x 10°6 at 300 K 3.0% 10-6 at 400 K 4.0% 1078 at 650 K 5.0% 10° at 900 K 45x 10-6 at 1100 K 1.206 1673/2 oxp( 1206 3.x 10167 o( oe (4.25 x 101 at 300°C) 1,83 10!° 3.22 10!9 0.3mo(nearx) 0.5mo(T) O.16ni9(T}) 1350 490 Ls o7 ) 1 Properties of Silicon and Gallium Arsenide at 300 K Gallium Arsenide Zineblende 4.65325 + 0.00002 2.44793 + 0,00002 2.21 x 102 144.642 (69.72 for Ga, 74.922 for As) $3174 124 +12 10-47) (12.85 at 300 K) 3317 3.255.(144.5 x 10°57) (3.299 at 300 K) 1238 5.69 10° + 1.5 10°7 (6.05 x 10°5) at 300 K 2.25 x 108 at 300 K 8.78 x 10! at 500 K 3.02 x 10! at 700 K 1.01 x 10! at 900 K 6.5% 10"® at 1050 K 96x 10!8 42x 10"7 0.063m0(0) 0.35manearx) O.5mo(P) 0.076m0(R) 0.1559 P) 8500 400 058 0.ol a g BU ES|ZIS ae en, 22e8e/ass ee 1132 Bo |RgeES/SES 11118811128 a as 8 & E 83 © # |s.23_ Boece g 2 Beees| ||| 8asse © = g4ee2 Sssece z g g|* 3a S 3 z a go feces d Ee|-SSSeenag : $e/csssssags i) so 3 ag|Ba8828i808 8 4 2 ze & 3 £ ] sxe asaveeeyeeeees| eo e zg 3 e al £ = u = 5 é| Ol X SLE Ol x19 (89 wip) sous seas pbajosas fons 9.00 98 soi xs 9.088. OI XS'> (eto Up) tod pj sod 1997 210161 Go udp) smmpous sSunoy. x ——baxa.o1 xs 9) (sti) Provan {ats foooss (at fea) Josarres fos, Jaooren 121940) yes uoneztu0] ee = (wo / 4%) ploy proysonys, OL x tz OLx8 A010 (31 ong 1 a ce (31 00g. Ae 12") Senevac camara - as zly-01xsors O18 w-orxecy TT 60 ULSI “AUAISMYgIP [PUAEOH, apHaSY wn Kuadog (Ponuyuod) ¥ OE We apmuasay winy Jo sonsedord 11 ATA.SIeSPaSneeStaSETESTESREETTECESSEEE: 62 MATERIAL PROPERTIES 1.7 ELECTRONIC PROF TABLE 1.4. Point Defects in Gallium Arsenide TABLE 1.3 Properties of Impurities in Gallium Arsenide® Distance from E, Distance from By ‘Acceptor Donor Defect nev) (ineV) Level, Level, oo — Misfit Misfit Distance from Distance from Vas 0.045 Tetrahedral Factor Factor Valenee—-Condution AS os Radius on on Band Band Vas-Asi 03 0.06 Dopant Type? (A) As Site. Ga Site (ev) (ev) ASGa-Was nae Fea 03 s n 10h OI 0.0061 Gans 0077 Se mn Ld 0034 0.0059 023) Te nm 132 OI — = 0.0088 17 Sn n 14 0.186 0.111 = 0.006 1s Be Pp 1.06 — 01590028 = 12 Ca p18 0.175 0.035 = 121 Li P 0.023, 0.05 120 Mg p14 — out 0.028 = 130 Zn p13 — 008 0.031 ae 132 c np 0770347 0.389 0.026 0.006 cues 2 Ge nip 022-0034 0.032 0.04 0.0061 — Si nip 118 0.063 0.035 0.0058 Ag 4 132 0.206 on Au @ 613 019 0.09 Ca d 0.16 Co a 0.16, 0.56 - cr a 0.79) Cu a 014,024,044 0.16 Fe a 0.38, 0.52 Mn d 09 Ni a 0.35, 0.42 SS Vv a 127 0.65-0.75 See Refs 16 and = deep impurity(OF MATERIAL PROPERTIES REFERENCES 1 M. M. Atalla, E, Tannenbaum, and E. I. Scheibner, Stabilization of Silicon Surfaces by Thermally Grown Oxides, Bell Syst. Tech, , J. 38, 749 (1958). B. M. Welch, Advances in GaAs LSI/VLSI Processing Technology, Solid State Technol. (Feb. 1980), p. 95, P. Ashburn, A. A. Rezazadeh, EF. Chor, and A. Brunnschweiler, Comparison of Silicon Bipolar and GaAlAs/GaAs Heterojunction Bipolar Technologies Using. a Propagation Delay Expression, /EEE J. Solid State Circuits 24, 512 (1989) R. K. Richardson and A. C. Beers. Eds., Applications of Multiquantum Wells, Selective Doping and Superlatices, in Semiconductors and Semimetals, Vol. 24, Academic Press, New York, 1985, Y. Suematsu, Long Wavelength Optical Fiber Communication, Proc. IEEE 71, 692 (1981), R. K. Willardson and A. C. Beers, Eds,, Mercury Cadmium Telluride, in Semicon- ductors and Semimetals, Vol. 18, Academic Press, New York, 1981 4.8, Blakemore, Semiconducting and Other Major Properties of Gallium Arsenide, J. Appl. Phys. $3, R123 (1985). S. Adachi, GaAs, AIAs and Al,Gaj_,As: Material Parameters for Use in Device and Research Applications, J. Appl. Phys, $8, RI (1985), M. J. Howes and D. V. Morgan, Bds., Gallium Arsenide Materials, Devices and Circuits, John Wiley and Sons, New York, 1985. D. B, McCumber and A. G. Chynoweth, Theory of Negative Conductance Amplifi cation and of Gunn Instabilities in Two-Valley Semiconductors, IEEE Trans. Elec- tron Dev. ED-13, 4 (1966). C. Hilsum, Transferred Electron Amplifiers and Oscillators, Proc. IRE 50, 185 (1962), LD. Crossman and J. A. Baker, Polysilicon Technology, in Semiconductor Silicon H.R. Huff and E. Sint, Eds., The Electrochemical Society, Princeton, NJ, 1977, pls. J. Krauskopf, J. D. Meyer. B. Wiedemann, M. Waldschmidt, K, Bethge, G. WolE, and W. Schiitz, Impurity Analysis of Gallium Arsenide, in Sth Conference on Semi Insulating IN-V Materials, Malmo, Sweden, G. Grossmann and L.. Lebedo, Eds. Adam Hilger, Philadelphia, PA, 1988, p. 165. D. L. Rode, Low Field Electron Transport, in Semiconductors and Semimetals, Vol. 10, R. K. Willardson and A. C. Beer, Eds., Academic Press, New York, 19 G. E, Stillman and C. M. Wolfe, Electrical Characterization of Epitaxial Layers, Thin Solid Films 31, 69 (1976). W. Walukiewiez. L. Lagowski. L. Jastrebski, M. Lichtensteiger, H.C. Gatos, El tron Mobility and Free-Carrier Absorption in GaAs: Determination of the Compen- sation Ratio, J. Appl. Phys. 50, 899 (1979) R. Venkatasubramanian, 8. K, Ghandhi, and T, F. Kuech, Compensation Mecha nisms in n*-GaAs Doped with Sulfur, J. Cryst, Growth 97, 827 (1989). 35, 36. 3, 38, ‘REFERENCES 69 G. Salmer and J, Pribetich, Theoretical and Experimental Study of GaAs Impatt Oscillator Efficiency, J- Appl. Phys. 44, 314 (1973), H. Hovel, Semiconductors and Semimetas, Vol. 1: Solar Celts, R.K. Willardson and A. C. Beer, Eds.. Academic Press, New York, 1975. H, C. Casey and F, Stern, Concentration Dependent Absorption and Spontaneous Emission of Heavily Doped GaAs, J. Appl. Phys. 47. 631 (1976) R. E. Williams, Modern Gallium Arsenide Processing Methods, Artech House, Boston, MA, 198. S.J. Pearton, S. M. Vernon, C. R. Abernathy, K. T. Shor, R. Caruso, M, Stavola J. M. Gibson, V.E. Haven, A. E, White. and D. C. Jacobson, Characteristics of GaAs Layers Grown Direcly on $i Substrates by Metalorganic Vapor Phase Deposition, J- Appl. Phys. 62, 862 (1987). C. Kittel, nroduction to Solid State Physics, John Wiley and Sons, New York, 1966, J.D. Meindl and K. D. Wise, Eds, Special Issue on Solid State Sensors, Actuators and Inerface Electonics, JEFF Trans, Electron. Dey. ED-26, 1861 (1979) K. E, Bean and PS. Gieim, The Influence of Crystal Orientation on Silicon Semi- conductor Processing, Proc IEEE $7, 1469 (1969) E, H. Nicollian and J. R. Brews, MOS Physics and Technology. John Wiley and Sons, New York, 1982 R. G, Rhodes, Imperfections and Active Centers in Semiconductors, Pergamon, New York, 1964. H, Reiss, C. 8. Fuller, and F. J, Morin, Chemical Interactions Among Defects in Germanium and Silicon, Bell Syst. Tech. J. 38, 935 (1956) W. Shockley and J. T. Last, Statistics of the Charge Distribution for a Localized conductor, Piys. Rev. 107(2), 392 (1957) JR, Arthur, Vapor Pressures and Phase Equilibria in the Ga-As System, J. Phys Chem. Solids 28, 2257 (1967) J.C. Bourgoin, H. J. von Bardeleben, and D. Stievenard, Native Defects in Gallium Arend, J. Appl. Phys. 68, ROS (1988). H.R. Potts and G. L. Pearson, Annealing and Arsenic Overpressure Experiments on Defects in Gallium Arsenide, J. Appl. Phys. 37, 2098 (1966). AG. Milnes, Deep Impurities in Semiconductors, John Wiley and Sons, New York, 1973, W, Kohn, Shallow Impurity States in Silicon and Germanium, Solid State Phys. 8, 257 (1957) G. L. Pearson and J. Bardeen, Electrical Properties of Pure Silicon and Sitcon Alloys Containing Boron and Phosphorus, Ps. Rey. 78, 865 (1949). M, Lannoo and J. Bourgoin, Point Defects in Semiconductors. 1 Theoretical Aspects, Springer-Verlag, New York, 1981 W. M, Bulls, Propenties of Gold in Silicon, Solid State Electron. 9, 143 (1966). K. P.Lisiak and A. G. Milnes, Platinum as a Lifetime Control Deep Impurity in Silicon, J Appl. Plys. 6, $229 (1975) Flaw inaia 39, 40, 41 45, 46. 41, 48, 49, 50, 51 2 34. 55, 56. St, SaSSEEETETCEEETESTETaTETTaTE SS. Kishino, ¥. Matsushita, M. Kanamori and T. Fizuka, Thermally Induced Micro defects in Czochralski-Grown Silicon: Nucleation and Growth Behavior, Jpn. J. Appl. Phys. 21, 1 (1982), W, Wijaranakula, Solubility of Interstitial Oxygen in Silicon, Appl. Phys. Lett. $9, 1185 (1991). ‘A. Kanamori, Annealing Behavior of the Oxy} Lett, 34, 287 (1979). T. Nozaki, Concentration and Behavior of Carbon in Semiconductor Silicon, J. Electrochem. Soc, IN7, 1566 (1970), 0 Donor in Silicon, Appl. Phys. S. Pomrenke, H. Ennen, and Y. Haydi, Photoluminescence Optimization and Chae- acterization of the Rare Earth Element Erbium Implanted in GaAs, InP and GaP, Appl. Phys, 59, 601 (1986). M. E, Weiner and A. S. Jordan, Analysis of Doping Anomalies in GaAs by Means of @ Silicon-Oxygen Complex Model, J. Appl. Phys. 43, 1767 (1972), T. F. Kuech and E. Veuhofl, Mechanism of Carbon Doping in MOCVD GaAs, J Cryst. Growth 68, 148 (1984), R.N, Hall and J. H. Racette, Diffusion and Solubility of Copper in Extrinsic Ger ‘manium, Silicon and Gallium Arsenide, J. Appl. Phys. 38, 379 (1964). D.C, Look, The Electrical Characterization of Semi-insulating GaAs, J. Appl. Phys 48, 5141 (1977) M. Skowronski, 8, T. Neild, and R. E. Kremer, Location of Energy Levels of Oxygen—Vacancy Complex in GaAs, Appl. Phys. Lett. 87, 902 (1990). F.C. Wang and M, Bujatti, The Effect of Substrate Gettering on GaAs MESFET Performance, IEEE Trans. Electron. Dev. ED-32, 2839 (1985). P.M, Petroff, G. A. Rozgonyi, and T. T. Sheng, Elimination of Process-Induced Stacking Faults by Preoxidation Gettering of Si Wafers, J. Electrochem. Soc. 123, 565 (1976). T. W. Sigmon, L. Csepregi, and J. W. Mayer, fon Implantation Geuering of Gold in Silicon, J. Electrochem. Soe. 123, 1116 (1976). €. O. Bosler, J. P. Donnelly, W. T. Lindley, and R. A. Reynolds, Impurity Gettering in Semi-insulating Gallium Arsenide Using Ion Implantation Damage, Appl. Pays. Lett. 29, 698 (1976). S.K. Ghandhi, Semiconductor Power Devices, John Wiley and Sons, New York, 1977. D. Huber and J. RefMle, Precipitation Process Design for Denuded Zone Formation in CZ-Silicon Wafers, Solid State Technol, (Aug. 1983), p. 137, I ¥. Tan, E, F, Gardner, and W. K. Tice, Intrinsic Gettering by Oxide Precipitate Induced Dislocations in Czochralski Si, Appl. Phys, Lett, 30, 175 (1977), S. Kishino, K, Nagasawa, and T. lisuka, Heavy Metal Gettering by an Intrinsic Get: tering Technique Using Microdefects in Czochralski-Grown Silicon Wafers, Jpn J. Appl. Phys. 19, LASS (1980) 1. J. Magee, J. Peng, J.D. Hong, W. Katz, and C, A. Evans, Back Surface Gettering of Au in GaAs, Phys. Status. Solidi. A $8, 161 (1979), 58, D. Hull and D. J. Bacon, Introduction ro Dislocations, 3rd edition, Pergamon Press. New York, 1989. 59. H. F. Matare, Defect Electronics in Semiconductors, Wiley-Interscience, New York, 1971 60, F.C. Frank and W. T: Read, J, Multiplication Processes for Slow Moving Dislo- cations, Phys, Rev. 79, 722 (1950) 61, PW. Hutchinson and P. $. Dobson, Defect Structures of Degraded GaAlAs-GaAs Double Heterojunction Lasers, Philos. Mag 32, 745 (1975). 62. P.M, Petroff, Point Defects and Dislocation Climb in II-V Compound Semicon. ductors, J. Phys. Collog. Suppl. 40, 201 (1979). 63, A. O. Evwaraye and B. J. Baliga, The Dominant Recombination Centers in Electron-Irradiated Semiconductor Devices, J. Electrochem, Soc. 124, 913 (1977). 64, H.C. Casey, Jt, Diffusion in the II-V Compound Semiconductors, in Atomic Dif- {fusion in Semiconductors, D. Shaw, Ed., Plenum, New York, 1973, p. 351 65. S. Y. Chiang and G. L. Pearson, Properties of Vacancy Defects in GaAs Single Crystals, J. Appl. Phys. 45, 2986 (1975). 66. D. T. J, Hurle, Revised Calculation of Point Defect Equilibria and Non-stoichiom- try in Gallium Arsenide, J. Phys. Chem. Solids 40, 613 (1979), 67. E. W, Williams, Evidence for Self-Activated Luminescence in GaAs: The Gallium. Vacaney-Donor Center, Phys. Rev. 158, 922 (1968), 68. J. Nishizawa, H. Otsuka, S. Yamakoshi, and K, Ishida, Nonstoichiometry of Te: Doped GaAs, Jpn. J. Appl. Phys. 13, 46 (1974) 69. S, Makram-Ebeid, P, Langdale, and G. M. Martin, Nature of EL2: The Main Native Midgap Electron Trap in VPE and Bulk GaAs, in Semi-insulating I/-V Materials, D. C. Look and J. S. Blakemore, Eds, Shiva Publishing Lid., England, 1984, p. 184. 70. J. Hornstra, Dislocations in the Diamond Lattice, J. Phys. Chem. Solids 8, 129 (1958). 71. A. Many, Y. Goldstein, and N, B. Grover, Semiconductor Surfaces, North-Holland, Amsterdam, 1965. PROBLEMS 1. Compute the atom density for the principal planes of GaAs in terms of the cube edge. Identify these atoms and their positions by means of a sketch. Calculate the bond density for these planes. 2. A (100) surface, misoriented 2.29° towards the nearest [110], can be char- acterized as a series of steps, with risers of height equal to one-half the cube edge. Calculate the step length and the Miller index of this plane. 3. We wish to chemically delineate a window ina slice, with vertical walls. Beginning with (110) silicon, and using an anisotropic etch which exposes{111} planes, indicate all the directions of the edges of this oxide cut, and also all the planes delineated by this etch. Sketch a plan view of the window, A flat is provided on the slice to aid in making the first cut. What is the plane of this flat? What is the direction of the line made by the intersection of this flat with the (110) surface? It is possible for a tetrahedral stacking fault to be initiated during the growth of an epitaxial layer on (111) silicon, This fault usually begins at the substrate-layer interface, and propagates along {111} planes until it reaches the surface. ‘Sketch the outline of a stacking fault within a unit cell, and identify its var- ious (111) planes. Determine the thickness of the epitaxial layer in terms of the length of one side of the stacking fault, as it penetrates to the surfac It is only necessary to show the unit cell outline. - Stacking faults also arise during epitaxial growth in (100) silicon. Again, these propagate along {111} planes. Repeat Problem 4 for this situation, Mlustrate by means of the unit cell outline. When InAs is epitaxially grown on GaAs, a 2-ym region is formed in which the film accommodates to the substrate lattice, What is the defect concen tration in this region, assuming that it is uniform, and that growth is on the (100) plane. Note that this will give you a pessimistic number, because efffects such as lattice distortion or strain relief have not been considered, Assume that a = 6.058 A for indium arsenide. . What is the equilibrium concentration of Schottky defects in silicon at 300 and 1500 K. Repeat for Frenkel defects and compare the numbers. Comment on the results. }. Gold is introduced into n-type silicon. Show that it will behave p-type. Repeat for p-silicon. Here, show that the gold will behave n-type. In both ‘cases, assume that the gold concentration is well below the background con- centration, . A piece of n-GaAs has a total donor concentration of 5x 10! cm, Plot the 77-K mobility as a function of the compensation ratio (Nj, +N3)/n. CHAPTER 2 ——————— PHASE DIAGRAMS AND SOLID SOLUBILITY ‘A number of different materials are used in the fabrication of semiconductor devices and microcircuits. As a consequence, combinations of two or more of these are often encountered at various points within the structure. By way of example, ohmic contacts to silicon and Gas are made by the alloying of var- ious metals to the semiconductor. Occasionally, combinations of materials are inadvertently formed during heat treatment or during the storage of devices at elevated temperature. The most notorious of these, formed at the interface between gold leads and aluminum-bonding pads, results in the so-called purple plague,* which sets an upper limit to the temperature at which many silicon microcircuits can be stored. In this chapter, the behavior of these combinations is described by means of phase diagrams [1~4]. This behavior is important since it often determines the nature and choice of the fabrication process. In addition, it provides a clue as to the problems that may arise when certain combinations of materials are used together ‘A phase is defined as a state in which a material may exist, which is charac- terized by a set of intensive properties, such as composition, electrical polariza- tion, color, and so on. If these phases are presented for equilibrium conditions, the resulting diagram is called an equilibrium diagram, Since equilibrium con- ditions are attained at rates that are much slower than the freezing rate, most diagrams involving one or more solid phases are usually called phase diagrams and represent quasi-equilibrium conditions. "This topic is weated in Section 2 69(0 PHASE DIAGRAMS AND SOLID SOLUBILITY por pressure (tor) ‘00076 100 7200 Temperature, (°C) Fig. 2.1. Unitary phase diagram, 2.1 UNITARY DIAGRAMS ‘These are diagrams showing the phase change in a single element, usually as a function of temperature and pressure. They also apply to compounds that undergo no chemical change over the range for which the diagram is co structed. In its simplest form, the unitary diagram consists of three lines that intersect at a common point, thus delineating three areas on a two-dimensional plot. Figure 2.1 shows such a diagram for water, and illustrates the three phases in which it can exist. The common point, referred to as a rriple point, is invariant for the system and defines the temperature and pressure at which soli, liquid, and gaseous phases are all in equilibrium with one another. OA, OB, and OC are univariant lines. Water can coexist in two phases for any pressure—temperature combination represented by these lines. Phase changes, which are represented by crossing these boundaries, occur at sharply defined temperatures, because the heat evolved (or absorbed) during this transition is the latent heat. This ‘characteristic is used in the experimental construction of phase diagrams. 2.2 BINARY DIAGRAMS. ‘These are phase diagrams showing the relationship between two components as a function of temperature. The second variable, pressure, is usually set at 1 atm. In this way a relatively complex three-dimensional representation is avoided. “The tem componem is often used to denote elements and compound ofthis type interchange A ar B Fig. 22. Binary eutectic phase diagram. Figure 2.2 shows one of the many different types of binary diagrams that are encountered in practice. Here, the abscissa represents various compositions of two components A and B, usually specified in atom percent, mole fraction cor weight percent. Each end represents a pure component, which may be an element or a compound. 2.2.1 The Lever Rule At any temperature, the equilibrium composition of the two single phases L and 8, which coexist to make up a two-phase region, may be determined as follows (see Figure 2.2): Consider a melt of initial composition Cyy (the mole fraction of B in the melt), Let this melt be cooled from some temperature 7) to a temperature T2, corresponding to a point in the two-phase region. Let N= number of moles of liquid (L, for this example) at this temperature N= number of moles of solid (in the f phase, for tis example) s = composition of the liquid and solid respectively (mole fraction of B) CL. Then N;C;, and NsCy are the number of moles of B in the liquid and solid, respectively. But the total number of moles of B is (Nz +Ns)Cy- Hence by the conservation of matter{2 PHASE DIAGRAMS AND SOLID SOLUBILITY Ns_Cu-Cx_1 : E 2.1 Ne Cs-Cu s ey where J and s are the length of the two lines shown in Fig. 2.2. This is known as the lever rule and can be used to analyze compositional changes during the freezing of a crystal from the melt. The line XY is commonly referred t0 as a tie line. 2.2.2 The Phase Rule The correct interpretation of phase diagrams is greatly helped by knowledge of the phase rule. This rule, which is based on thermodynamic considerations, states that for any system in thermal equilibrium, the sum of the number of phases (P) and the number of degrees of freedom (F) is related to the number ‘of components (C) by P+F=C+2 22) Here, the degrees of freedom are the number of variables which can be indepen- dently changed while still preserving a specific phase. For example, P-+F = 3 for «a single-component diagram of the type shown in Fig. 2.1. For water in its liquid phase (P= 1) we have 2 degrees of freedom; that is, either pressure or temper- ature (or both) can be changed independently of each other, and still maintain water in this liquid phase. Along OB, however, P = 2 (liquid and vapor) so that we have I degree of freedom. Now, either pressure or temperature (but not both) can be independently varied while still preserving this two-phase coexis- tence. At 0, P= 3 and F = 0; that is, there is a unique temperature-pressure combination where water coexists in all three phases. For a binary phase diagram such as that shown in Fig. 2.2, F+P = C+2=4. If we confine our discussions to systems at atmospheric pressure, then F = 3~P, since 1 degree of freedom is now preassigned, Furthermore, we note that composition is assigned a single degree of freedom, since X4 (the fraction of A) and Xp (the fraction of B) are related by Xq+X~ = 1 In Fig. 2.2, regions L, « and 8 are each one-phase regions, so that F = 2 (both temperature and composition can be varied independently of each other). In the two-phase regions L +a, +8, and a +8, we have F = 1, These are univariant regions; at any given temperature, for example, the compositions of both the liquid and solid phase are fixed by the lever rule, Thus, either temperature or composition can be varied independently in this region, but not both. At the point E, there are three phases, L, and 8, so that P = 3. Hence, there are 0 degrees of freedom; E is an invariant point, whose temperature and composition are both fixed. As a result of the phase rule, we note that a binary diagram can have only regions of one- and two-phase. (Degenerated three-phase regions, represented ‘22 BNARY DIAGRAMS =—73 by apoint such as £, are also permitted.) Furthermore, two-phase regions cannot, be next to each other. It follows that, in traversing a binary phase diagram from one side to another at any constant temperature, all single-phase regions are separated by two-phase regions as the composition is varied. By way of example, the phases that exist at T, are a,L + a,L,L +B, and B in succes. sion. On the other hand, the phases that are present at T, are a,c + 8, and 8, in succession. Various types of binary phase diagrams are encountered in practice, depending on the components involved and their degree of miseibility in the solid and liquid state, Some of these are now described. 2.2.3. Isomorphous Diagrams ‘The isomorphous diagram is characteristic of components that are completely soluble in each other. It has been empirically found that phase diagrams of this type are restricted to binary systems in which the components are within 15% of each other in atomic radius, have the same valence and crystal structure, and have no appreciable difference in electronegativity. As a consequence, only a few binary systems belong to this class; some examples are Cu-Ni, Ag-Pd, and ‘Au-Pt, Limited solubility of components is by far the more common occurrence in binary systems. Silicon and germanium are very similar in structure and atomic properties. As expected, they are completely miscible in both the liquid and solid phase, and are characterized by the isomorphous phase diagram of Fig. 2.3. Here, a represents the full range of solutions of germanium and silicon; a single-crystal, diamond lattice material can be grown for any composition. In this latice, how ever, atom sites will be randomly occupied by silicon and germanium, while preserving a specific overall composition ratio. It must be emphasized that this ‘material is quite different to a compound, such as GaAs, where lattice sites are specifically assigned to either gallium or arsenic. Mixtures of III/V compounds, such as GaAs and GaP, are also isomorphous in behavior, as seen in the GaAs-GaP phase diagram of Fig. 2.4 [5]. Solutions of this type are known as mixed compound semiconductors, ternary compounds, or ternary alloys. The ternary compound GaAs,P)-, consists of a solution of the binary compounds GaAs and GaP, in a y/(1~ y) ratio. Here, all group III sites are occupied by gallium atoms, whereas group V sites comprise randomly distributed arsenic and phosphorus atoms in this ratio. The lattice parameter of temary compounds is related linearly to that of its binary components (Vegard's law). For GaAs, a= 5.6532 A whereas a = 5.660 A for AIAs. Thus, there is a 0.12% mismatch between these extremes. As a result, all Al,Ga;-,As compositions are closely matched to each other, so that a single continuous crystalline structure can be grown with siccessive layers of different composition. In addition, bulk GaAs can be used as a substrate for this purpose. The AIAs-GaAs system is technologically very important forPHASE DIAGRAMS AND SOLID SOLUBILITY eit sn ee a ee ee foe eee ae eee amen an Dce T T TJ v0 {ij fy a | | ~m es < , i° | § | | pr gag crepe T é | a } | a 1 a | v0 — on || [aie our a a a & Tome sess ¢ Fig. 2.3. Binary isomorphous phase diagram: ‘The Ge-Si System. from Hansen and Anderko, Constiturion of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. 1600, 1500] war 1400 [= 900} 1109, GP 02 e068 OO ake Mole ration Gas Fig. 24 The GaAs-GaP system. From Antypas [5]. Reprinted with permission of the publisher, The Electrochemical Society, Inc 22 BINARY DIAGRAMS 75 this reason, and most modern GaAs-based semiconductor devices utilize the electronic properties of heterostructures which exploit this combination, The energy gap of most ternary alloy semiconductors also varies between the two extremes associated with its binary components. Here, the relationship is only approximately linear. For Al,Ga;_,As [6], the direct energy gap (I’ point) is given by Ep) = 1.424 + L087x +0438? 23) ‘The indirect gap (x point) for this system also varies monotonically, with Eyl) = 1.905 + 0.10x + 0.163 24) Combining these equations, itis seen that AlGay.,As is direct gap for x $0.43, but indirect gap at higher x values. This property is exploited in the use of indirect gap Al,Ga;-.As for optically transparent windows in GaAs detec. tors. Moreover, the surface recombination velocity of GaAs is greatly reduced When its surface dangling bonds are terminated by AIGAAS, which is grown as an extension of its crystal lattice. These advantages, taken together, have been exploited in the fabrication of high-efficiency GaAs solar cells and lasers. The temary alloy GaAsisPos is a direct gap material which is used in ted light emitting diodes. The lattice parameter of GaP is 5.4512 A, so that GaAs) Pa, is mismatched to gallium arsenide by 1.4%. As a consequence, device quality material cannot be grown on it directly. In practice, a 40-um. thick buffer layer, graded from x = 0 at the GaAs substrate to x ~ 0.4 at its top. is grown between the substrate and the active layer in order to relieve the misfit dislocations which would arise ifthe active layer were grown directly on the GaAs substrate More complex solutions of compound semiconductors can also be made. For example, quaternary alloys with compositions corresponding to MIMI ,VeV?.,, HIST? THE, ,V®, and IIVEVE VP, are also possible, and are used in some device applications. A discussion of these is beyond the scope of this book, 2.2.4 Eutectic Diagrams Eutectic diagrams result when the addition of either component to a melt lowers its overall freezing point, as shown in Fig. 2.2. Here the freezing point of the molten mixture has a minimum value Ts, below Ty and Tg. This minimum value is known as the eutectic temperature, and the corresponding mixture Cz is called the eutectic composition. Eutectic systems usually, occur when two Components are completely miscible in the liquid phase but are only partly soluble in the solid phase. Most semiconductor systems fall into this class. Referring to Fig. 2.2, consider the cooling of a melt of initial com-(‘76 PHASE DIAGRAMS AND SOLID SOLUBILITY position Cy. As the temperature is reduced below Ts, a solid of com- position ; first freezes out. With falling temperature, the liquid com- position moves. along the liquidus line, becoming richer in A, until the eutectic temperature Tr is reached. Simultaneously, S-phase material of varying composition freezes out, as the solid composition moves down the solidus line. At Ty, the melt is of eutectic composition Cr, and freezes isothermally to form the (a + 8) phase. Thus the final solid con- sists of clumps of -phase material in an (ce + B)-phase mixture of eutectic ‘composition. A solid of this type has a tendency to break along the boundaries of the B-phase clumps, if subjected to mechanical strain. A starting melt of eutectic composition, on the other hand, solidifies into a (a+) phase without any clumping, and is thus considerably stronger. Figure 2.5 shows the lead-tin system which exhibits this type of character- istic. Here the eutectic point has a 38% lead-62% tin composition by weight and a eutectic temperature of 183°C. On the other hand, the freezing points of pure lead and pure tin are 327°C and 232°C, respectively. Lead-tin combina- tions, of eutectic composition, are used routinely as solders in electronic circuit wiring. Variations of the eutectic diagram of Fig. 2.2 are often seen in practice, Temperature, *¢ x a a Sn ‘Nomis % leas °> Fig, 2.5 The lead-tin system. From Hansen and Anderko, Constitution of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. 2.2 BINARY DIAGRAMS = 77 depending on the nature of the terminal solid solutions. Thus in the Pb-Sn system the terminal solid solubility (atom fraction) of tin in lead is significant (29%). as is that of lead in tin (1.45%). In the Al-Si system, on the other hand, the terminal solid solubility of silicon in aluminum is 159%, while that of aluminum in silicon is $0 small (<0.1%) that the # phase cannot be indicated in this diagram. Figure 2.6 shows the phase diagram for this system, which is Weight % sion pp p os pe 9 1500 1409 nes | he B 8 Tenge 3 r “ i 5 ws i015, 1 Momic % Si | YT oft + + f | 4005 10 2 3040 50 60S «100 A Muon see ? 2.6 The aluminum-silicon system. From Hansen and Anderko, Constitution of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company.(#6 PHASE DIAGRAMS AND SOLID SOLUBILITY of importance in the fabrication of ohmic contacts* to p-type and degenerate type silicon ‘Aluminum is sometimes used for the fabrication of Al-Si Schottky diodes in high-speed digital logic circuits. Here, subsequent processing can alter the interface and cause changes in diode characteristics. Thus, the phase diagram gives vital information about potential problems which can arise during the fabrication of circuits incorporating these devices. ‘The Au-Si system is shown in Fig, 2.7, Here both terminal solid solubilities ‘are too small to be indicated on the diagram. The sharply depressed eutectic temperature of this combination leads to its widespread use in the die bonding of discrete silicon devices and microcircuits to substrates. An altemative com- bination, which provides a better wetting action and has a lower eutectic tem- perature, is gold and germanium, whose phase diagram is shown in Fig. 2.8. In this case, the resulting bond is a temary Au-Ge-Si alloy. Gold alloys formed with these systems are extremely hard and strong, and cannot be used in power devices which are subject to significant thermal cycling. Lead-tin solders are more suitable for these applications because of their plastic behavior. Gold~germanium alloys are extensively used in GaAs technology for making ohmic contacts to n-GaAs. Although a very small Ge fraction is necessary for this purpose, the eutectic composition is invariably used because of its depressed melting point. Occasionally, binary systems may exhibit an eutectic composition that is very close to one of the components. Figure 2.9 shows the Ga-Ge system which belongs to this class. Ge-Ga alloys are created by the heat treatment of Au-Ge eutectic with GaAs, during contact formation. Thus, this figure can be used 8 an indicator of problems during this process. The more detailed Ga~As-Ge temary phase diagram (Fig. 2.26) can be used for this purpose, as well. 2.2.5 Compound Formation In many complex systems, one or more intermediate compounds may be formed at specific temperatures and compositions. In contrast to mixtures, these inter mediate compounds are ordered on an atomic scale. They usually occur within an extremely narrow compositional range, corresponding to very small depar- {ures from stoichiometry. Consequently, they are indicated on the phase diagram in the form of discrete vertical lines, as shown for the Ga-As system of Fig, 2.10 at the 0% Ga-50% As composition. Since these lines appear to represent a change from one phase directly into another, without any apparent alteration in composition, they are sometimes called congruent transformations The formation of a congruently melted compound in this manner effectively isolates the system on each side of it. Thus, this figure can be considered as This topic is covered in Chapter 8. 2.2 BINARY DIAGRAMS 79 1600) ae 1400] p 1200f + pe 1000 A} — a 200 Temperature, 600 363! 2 woke V7 Sie a 4 wee eon e Fig. 2.7. The gold-siticon System, From Massalski [1]. Used with permission of ASM International. Weigt % germaniam 5 1 1 2% 0 0 6 10 | 1109 i Temperature, °C 200] 2005 1020 E) Cr 70 80 100 ” ce ‘Nome % germanium Fig. 2.8 The gold-germanium system, From Hansen and Anderko, Constitution of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company.80 PHASE DIAGRAMS AND SOLID SOLUBILITY Weight % germaniom m4 0 T me i a7. 78) 200| °o 70 40~=00SwSSCO o ‘Atomic % germaniom - Fig. 2.9 The germanium-gallium system. From Hansen and Anderko, Constitution of Binary Alloys, MeGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. Wish ani 10% 0 5060 70 09 rae 1200 ao Z 1000 PN = exo : ae exo 2 { i E cook : é 2 | Y | 3 “f +3} 200 } nas za 2 g 0 CO Atomic areeie Fig. 2.10 The gallium-arsenic system, From Hansen and Anderko, Constitution of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. 22 BINARY DIAGRAMS 81 separate Ga-GaAs and GaAs-As systems, each of which is seen to be eutectic in nature. In this manner it is possible to break up relatively complex phase diagrams into a number of simpler ones. A vertical line, drawn to indicate a congruently melted compound, is some- ‘what an oversimplification. In general, congruent melting will appear as a region of finite width if a sufficiently expanded compositional scale is used. In mate- rials such as GaAs, the presence of large concentrations of vacancies and inter stitals of both Ga and As (with their associated different free energies) results in melting at a point slightly removed from that of the ideal 1 : I stoichio- metric composition. A greatly expanded phase diagram [7] around this region is sketched in Fig. 2.11. We note from this diagram that the solidification of GaAs can occur in a region of excess gallium or arsenic, resulting in the for- mation of excess arsenic or gallium vacancies respectively. This represents the stoichiometry range of Gass, which is between 49.998 and 50.009 at.% of As. 1600 1500 1400 1000 00 1 L 4990 4995 50 5005 5010 ‘CONCENTRATION OF As (at %) Fig. 2.11 Details of the GaAs phase diagram. From Swaminathan and Macrander. ©1991 [6, p. 45] Prentice-Hall, Englewood Cliffs, New Jersey. Reprinted with per82 PHASE DIAGRAMS AND SOLID SOLUBILITY ‘As mentioned in Chapter 1, many of these excess vacancies can become ‘occupied by impurity atoms which are either intentionally or unintentionally present during crystal growth, with a resultant shift in the conductivity. Further- more, the amount of shift in conductivity, as well as its direction (ie., towards ‘p- oF n-type), will be determined by the temperature at which solidification ‘occurs from the melt. This has important consequences in crystal growth and epitaxy, as shown in Chapters 3 and 5, 2.2.6 Peritectic and Other Reactions ‘A peritectic reaction is an important pathway by which an intermediate com- pound can be formed in a binary system. By way of example, Fig. 2.12 shows the arsenic-silicon system, in which the compound SiAs> is formed by a peri- tectic reaction, between SiAs and a liquid. Note that both these compounds are depicted by vertical lines, since they occur within a narrow compositional range. A eutectic point also exists for the SiAs-As system, corresponding to a 96% As—4% Si composition by weight. Wong % arsenic on no 8 9% an 44 - we} fo) [ue | | soo clEe le _ 100 | oS 00 5 ‘ome % arsenic as Fig. 2.12 The arsenic-silicon system, From Hansen and Anderko, Constitution of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the ‘MeGraw-Hill Book Company. 22 BINARY DIAGRAMS = 83. Consider what happens if a mixture of 86% As-14% Si by weight (indicated bby an arrow in this figure) is cooled from some high temperature. At and below 1020°C, solid SiAS is precipitated from the melt, which becomes arsenic-rich until the temperature reaches 944°C. At this point, the liquid composition is 90% As-10% Si by weight. Further cooling results in a thermal arrest period at this temperature, during which time the solid SiAs combines with some of this excess liquid to form an (L + SiAs,) phase. At 786°C and lower, both the SiAs, and the 8 phase precipitate from the remainder of this excess liquid to form a solid (B + SiAs:) phase as shown. Cooling through a peritectic temperature causes the formation of a nonequi- librium structure by the process of “surrounding.” Here the SiAs> is formed by the surrounding of a solid SiAs core by the liquid. Under normal cooling conditions, this SiAs> layer creates a barrier to the diffusion of liquid to the SiAs, resulting in a reaction that proceeds at an ever-decreasing rate, Thus a peritectic reaction is usually accompanied by the formation of relatively large (micron-size) precipitates.* This is also true if the starting melt was of the exact composition as the peritectic compound—for example, a melt of Si:As in a 1:2 atomic ratio in the example shown in Fig. 2.12. Here, too, cooling the melt to 944°C results in the precipitation of solid SiAs and a liquid of 90% As-10% Si by weight, Under thermal equilibrium conditions, this liquid would react completely with the SiAs to form the SiAs:. In a practical situation, under ‘nonequilibrium conditions, this reaction would slow down with the formation ofa SiAs, skin surrounding each SiAs core, so that excess liquid would remain. This would eventually cool to form a solid (B + SiAs2) phase as before. Peritectic phases usually occur as part of more complex phase diagrams. Figure 2.13, for example, shows the phase diagram of the aluminum-gold system, which is of importance in evaluating the bonding of gold leads to alu- minum contact pads on microcircuits. Of the many possible intermetallic com- pounds that are indicated here, the most significant are AUAL; (a dark purple, strongly bonding, highly conductive compound) and AusAl (a tan-colored, brittle, poorly conducting compound). This latter compound** has a melting point of 624°C. Nevertheless, significant compound formation occurs at 300°C and higher. This is a serious cause for lead-attachment failure in microcircuits ‘which are stored for period of times at these high temperatures [8] Experiments have shown that the formation of Au>Al is enhanced by the presence of silicon, Although the temary AlAu-Si system has not been studied in detail, it can be expected that the effect of silicon addition to the AL-Au system produces simple eutectic lowering of its phase diagram [8]. Thus the formation of these compounds may be expected to be accelerated in the pres- cence of the silicon. This has been observed experimentally “The anomalous behavior of arsenic doping at high concentrations can be explained by the for- imation of As-Si clusters by this reaction, ‘For many years, the tan AuzAl was not noticed in the presence ofthe purple AUAlz, Thus the term purple plague was wrongly given to this phenomenon, and sill persists in the literature,84 PHASE DIAGRAMS AND SOLID SOLUBILITY Weight % gots 10.30 50 6 7 © 8 95 aes i = = 1200 — 1100 8 | i 8 5 \ we z 300) L oa a ‘mame % gold Fig. 2.13 ‘The aluminum-gold system. From Hansen and Anderko, Constituzion of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. Figure 2.14 shows the platinum-silicon system, and indicates the phases involved in the formation of a PtSi Schottky barrier layer on a silicon surface. Typically, a layer of platinum, 500 A thick, is deposited on the silicon which is then heated to about 600°C for 15 min. This suffices to complete* the reaction and form PtSi, even though the melting point of this compound is 129°C. This 1 should be emphasized that phase diagrams provide no information about the kinetics of & 22 BINARY DIAGRAMS — 85 Wight scan ee Sana pon a3 a rz Vi WV Toeel / 7 963 + 5 —_| S704" 9899 fl “38 ws ea a a0" 2 _| ‘aay w 203080 a) GO) 80100 s oh Atomic % icon Fig. 2.14 The platinum-silicon system. From Hansen and Andetko, Constitution of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. PASi layer serves as a base which is followed by successive layers of titanium, Platinum, and gold. This complex metallization scheme forms the basis of the beam lead system [9], which is deseribed in Chapter 8 ‘A common contacting scheme for n-type GaAs consists of depositing a layer of germanium, followed by a layer of gold to which leads can be readily86 PHASE DIAGRAMS AND SOLID SOLUBILITY bonded. Phase diagrams of the Ge~As system, shown in Fig. 2.15, together with those for the Ge-Ga system (Fig. 2.9) and the Au-Ga system of Fig. 2.16, are useful in evaluating potential problems here. The phase diagram for the ternary Ga-As-Au system is shown in Fig. 2.25. The Ga-As-Ge system is shown in Fig. 2.26, In addition to eutectic and peritectic behavior, a. number of other less ‘common reactions may occur in binary systems. Thus a single phase can cool to form two phases in one of three possible ways, as follows: (a) Monoectic: 1, a-+Ls (b) Eutectic: LS a+8 (©) Entectoid: ya +8 Here, L,L, and Ly represent liquid phases and ez B, and -y represent solid phases, including compounds. In addition, three possiblities occur when two phases react to form a third, different phase, as follows: G) Symes 1,443 (Pesta: La SB (©) Peritectoid: a +738 Weight arsenic m9 40 0 om cots “Temperature °C) r ya iL 0102030408 Aone ere Fig. 218 The germanium-arsenic system, From Hansen and Anderko, Constitution of Binary Alloys, McGraw-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. Weight atm 24681 1% 2% % 9 4% 0 60 70 50.00 i a +1100} ba — cy 10 1000 4 “00 om | 4 "7 20! (rs) ~20" 207° a ‘Ato % glo Go Fig. 2.16 ‘The gold-gallium system. From Hansen and Anderko, Constitution of Binary Alloys, MeGrav-Hill, New York (1958) [2]. Used with permission of the McGraw-Hill Book Company. Examples of some of these reactions are shown in the phase diagrams of Figs. 2.12 to 2.16, 2.2.7 Phase Diagrams for Oxide Systems Phase diagrams involving oxide systems are especially important in both sil- icon and GaAs technology, Thus, boron doping of silicon is carried out from aSeUSesEeREEE Ee ESe eee Rs ee eee eee eee eee B,0s-SiO: source which is deposited on the silicon slice prior to diffusion, ‘The phase diagram of Fig. 2.17 is relevant 10 this process. Although of a relatively straightforward eutectic type, a number of structural phase change regions are seen here, as the SiO; goes through its cristobalite and tridymite phases {10} Figure 2.18 shows the phase diagram for the P,O.-SiO» system. Phosphosil cate glass (PSG) has considerable importance in device technology {11}, since itis used for phosphorus doping of silicon, for gettering to improve lifetime in silicon devices, as a passivation layer over silicon microcircuits, as a diffusion ‘mask for GaAs, and as a cap for open tube diffusions in GaAs [12] 2.3 SOLID SOLUBILITY It has been noted that many binary systems exist in which the terminal solid solubility of one component in the other is extremely small. This is usually the case for donor and acceptor impurities in silicon. As a consequence, it is necessary fo expand greatly the scale of the phase diagram in order to show this important region. Figure 2.19 shows this part of the phase diagram, and is typical of most impurities in silicon. The solid solubility of these impurities s Seen to increase with temperature, reach a peak value, and fall off rapidly as the melting point of the silicon is approached. This is commonly referred 1800, 1600] | L cvstbalte 1400 1200} 1000 | e+ yt | bau i 00 t | oo 1+ quarts 300) ea S10; + 8:05 ° L 20a 00 3102 8,05 Weant & 2.17 The By0s-SiO» system, From Rockett and Foster {10}, Reprinted with per. mission from the American Ceramic Society. 23 SOLID SOLUBILITY = 89 (20s: $102) 1— Low-temperature phase (05-510, ) h— High-temperature phase i) ; 1700] — + 0s 280, 1600 | | sco | 2 0 | 2 1300 per —— F ro \ T+ 605 S09 \ 1100) (F205 * Si0)h + +8, Robe 2 oO, 1000 SSS (0s: 80D seo oho 28% 802+ 04280] “Fro 75, 800 L a ot 0, Mole % 205-02 405-80, Fig. 2.18 The P205-SiO2 system. From Tien and Hummel [11]. Reprinted with per- mission from the American Ceramic Society. euia haere —_ —4 | a Fig, 2.19, Retrograde solubility characteristic.PHASE DIAGRAMS AND SOLID SOLUBILITY 00 a TT? Tamoerre Fig. 2.20 The solid solubility of impurities in silicon. 24 TERNARY DIAGRAMS — 91 to as a retrograde solid-solubility characteristic. Figure 2.20 shows values for various commonly used dopants in undoped silicon (13, 14]. Note that nearly all of these elements indicate a retrograde behavior in their solubility charac- teristics. Finally, it must be emphasized (see Chapter 1) that the solid solubility of dopants exhibiting multiple charge states is a function of the background concentration—that is, a function of the fermi level 2.4 TERNARY DIAGRAMS TTemary phase diagrams are required for systems with three components. They are of special use in the study of the behavior of III-V semiconductors such as GaAs, in the presence of an additional component. Very few systems of this type have been studied in detail. However, even fragmentary information, which is available for many such systems is useful in evaluating the potential problems which can arise during device processing. Fig. 221a The temary phase diagram (a) Isometric construction, From Rhines, Phase Diagrams for Metallurgy McGraw-Hill, New York (1956) [15]. Used with permission of the McGraw-Hill Book Company,32 PHASE DIAGRAMS AND SOLID SOLUBILITY wo Fig. 2.21 The temary phase diagram. (b) Isothermal sections. From Rhines, Phase Diagrams for Metallurgy McGraw-Hill, New York (1956) [15]. Used with permission of the McGraw-Hill Book Company. 24 TERNARY DIAGRAMS 93 Fig. 2.22 Compositions in the ternary phase diagram. ‘A temary system, where all alloys solidify eutectically, is shown in Fig. 2.21a and illustrates many of the characteristics of these diagrams [15]. We note that this is a three-dimensional plot, and is rather complex to construct, even for such a simple situation. The base of this diagram is an equilat- eral triangle with sides of unit length, as shown in Fig. 2.22, with each side corresponding to a binary composition, usually on an atom fraction. basis. Any line parallel to a side of this triangle represents compositions in which the fraction of the component in the opposite vertex is held constant (for ‘example, all compositions with 25% A are represented by the line XY in Fig. 2.22). Any line through a vertex represents all compositions with a fixed ratio of the components at the other two vertices. Thus, compositions Where B : C= 3 : 1 are represented by the line AZ. The composition at 0 is thus 25% A, 56.25% B, and 18.75% C. Another interesting property of the equilateral triangle is seen by dropping Perpendiculars to the three sides from the point O. Let the length of these Perpendiculars be a,b,c drawn as shown to the sides opposite the vertices A,B,C respectively. Then the composition represented by the point O is given by A:B:C = a:b: c. Furthermore, a+b-+¢ = sin60". For this example, 4 = 0.25 sin 60°,b = 0.5625 sin 60°, and c = 0.1875 sin 60°, so that the compo- sition defined by O is 25% A, 56.25% B, and 18.75% C as before. 2.4.1 Isothermal Sections ‘Temary phase diagrams of the type shown in Fig. 2.21a are usually drawn in simplified form as a series of isothermal sections taken at different temperatures of interest [16]. Sections of this type are shown in Fig. 2.21 and correspond to the temperatures indicated in Fig. 2.214. Very few such systems have been completely determined. Nevertheless, many sections can be drawn qualitatively from a knowledge of the behavior of the individual binary systems A~B, B~C, and C-A94 PHASE DIAGRAMS AND SOLID SOLUBILITY ‘A study of isothermal sections of this type shows the following: 1. All two-phase regions are enclosed by four boundaries. Two opposite boundaries are adjacent to three-phase regions, or may be boundaries of the phase diagram. The other two opposite boundaries separate this region from one-phase regions. In addition, contact is made with two-phase regions at each vertex. 2. All three-phase regions are triangular, bounded by two-phase regions on three sides. In addition, they are in contact with one-phase regions at each vertex. 2.4.2 Congruently Melting Compounds ‘These are always present in the Ga-As-impurity system. Examples are binary compounds such as GaAs or Zn3Asa (in the Ga-As-Zn system). The presence of congruently melting compounds of this type serves to divide the ternary system. into subsidiary eutectic systems. 2.4.3. Degrees of Freedom In temary systems, F + P = 3+2= 5, Since I degree of freedom is usually assigned to pressure, F +P = 4 under ordinary circumstances. In addition, we note that two compositions must be assigned in order to determine the third, since X4+Xp-+Xc = 1. For any isothermal section, the temperature is also preassigned, so that F = 3~P. In a one-phase region as shown in Fig. 2.23 (such as L,a.8,7) Fig. 2.23. Diagram illustrating regions of one, two and three phases, Seeeees ee eee eee eeeee eens there are 2 degrees of freedom. Both X, and Xq (and hence Xc) can be varied independently over this region. For a two-phase region (L+a,L+B,L+}.a-+8, etc.), only 1 degree of freedom is possible. Thus, only one of the components can be varied. This is illustrated in Fig. 2.23. Here, a given value of X4 results in a liquid of composition X” along the boundary ab. This fixes, via a tie line, the composition of the solid solution 6 at X” so that the system is fully defined. In temary diagrams, these tie lines may be straight or curved, and must be determined experimentally. In general, however, their positions are usually ‘estimated by noting that they vary gradually from one boundary to the other, without crossing each other. Furthermore, they must run between two one-phase regions. A series of such tie lines is shown in this figure. Figure 2.23 also shows a three-phase region, L + 8+. This is an invariant region, with no degrees of freedom. For this temperature, the composition of the liquid and solid phases (L,8, and 4) is fixed at the values given by the vertices of the triangle bounding this region. Thus, the partial pressure of these three components is fixed by temperature alone. Compositions of this type are par- ticularly useful as diffusion sources for this reason. The application of teary considerations to diffusion will be considered in Chapter 4. 2.4.4 Some Ternary Systems of Interest It is customary to show these systems in the form of a contour map, looking down on the composition triangle, with isotherms as contour lines. Also indi- cated on these diagrams are unique features (eutectics, peritectics, compounds, etc.) which aid in constructing specific isothermal projections as required. The valleys of the liquidus are also projected on to the composition triangle, with arrows indicating decreasing temperature. ‘The diagrams for GaAs, with Ag, Au, Ge, S, Sn, Te, or Zn as the third com: ponent are shown in Figs. 2.24 to 2.30, respectively [16-18]. Most of these dia- grams are incomplete, with many lines estimated from the appropriate binary diagrams, Nevertheless, they are useful for assessing problems which might arise during the growth or alloying of GaAs [19], and also for evaluating con- ditions during diffusion in GaAs [20]. This latter topic is taken up in Chapter 4, where a series of isothermal sections are shown for the Ga-As-Zn and Ga-As-S. systems.Aya ° " Mh) KAN‘98 PHASE DIAGRAMS AND SOLID Fig. 2.28 The temary system Ga-As-Sn. From Alper, Ed., Phase Diagrams, Vol. IIL (1970) [16]. Reprinted with permission of Academic Press, In. Fig. 2.29 The temary system Ga-As—Te. From Alper, Ed, Phase Diagrams, Vol. IL (1970) [16]. Reprinted with permission of Academic Press, Inc REFERENCES 99 sae oe Gay nore? 1238" cd ig. 2.30 The temary system Ga-As-Zn. From Alper, Ed., Phase Diagrams, Vol. I (1970) [16]. Reprinted with permission of Academic Press, Inc. REFERENCES ‘A large collection of phase diagrams for binary alloys may be found in Ref. 1 as well as in Ref. 2, with its more up-to-date supplemeat (3]. A compendium of phase diagrams for refractory oxides may be found in Ref. 4. Phase diagrams for temary systems of interest io Gas processing technology are scattered throughout the technical literature. 1. T. B. Massalski, Ed., Binary Alloy Phase Diagrams, 2nd edition, ASM Interna tional, New York, 1990, 2. M, Hansen and K. Anderko, Constitution of Binary Alloys, McGraw-Hill, New York, 1958, 3. R.P. Elliot, Constitution of Binary Alloys (A supplement to Ref. 1), MoGraw-Hill, New York, 1965, 4. E, M. Levin, C. R, Robbins and H. F. MeMurdie, Phase Diagrams for Ceramists, American Ceramics Society, Columbus, OH (1964) G. A. Antypas, The GaP-GaAs Temary Phase Diagram, J, Electrochem. Soc. 7, 700 (1970), 6. V. Swaminathan and A. T. Macrander, Materials Aspects of GaAs and InP-Based Siructures, Prentice-Hall, Englewood Cliffs, NJ, 1991‘100 PHASE DIAGRAMS AND SOLID SOLUBILITY 7. C. D, Thurmond, Phase Equilibria in the GaAs and the GaP Systems, J. Phys: Chem. Solids 26, 785 (1965) 8, B, Selikson and T. Longo, A Study of Purple Plague and Its Role in Integrated Circuits, Proc. IEEE 52, 1638 (1964), 9. J.H. Forster and J. B. Singleton, Bearm-Lead Sealed Junction in Integrated Circuits, Bell Lab Record 44, 312 (1966). 10. T. J. Rockett and W. R. Foster, Phase Relations in the System Boron Oxide-Silica, J.Am, Ceram. Soc. 48, 75 (1965), 11, T. ¥. Tien and R. A. Hummel, The System SiO2-P20s. J. Am. Ceram. Soc. 48, 422 (1962). 12, B, J. Baliga and S. K. Ghandhi, PSG Masks for Diffusion in Gallium Arsenide, IEEE Trans. Electron Dev. ED-19, 761 (1972). 13. F. A. Trumbore, Solid Solubility of Impurity Elements in Germanium and Silicon, Bell Syst. Tech. J. 39, 205 (1960), 14, G. L. Viek and K. M. Whittle, Solid Solubility and Diffusion Coefficients of Boron in Silicon, J. Electrochem. Soc. 116, 1142 (1965). 15. F.N. Rhines, Phase Diagrams in Metallurgy, McGraw-Hill, New York, 1956, 16. H. C. Yeh, Interpretation of Phase Diagrams, in Phase Diagrams, Vol. 1, A. M Alper, Ed., Academic Press, New York, 1970. 17. H., Matino, Reproducible Sulfur Diffusions in GaAs, Solid Stare Electron 17, 35, (1974), 18, M. B. Panish, Temary Condensed Phase Systems of Gallium and Arsenic with Group 1B Elements, J. Electrochem. Soc. 114, 516 (1967), 19. M. B. Panish, The Gallium-Arsenic-Tin and Gallium-Arsenic-Germanium Temary Systems, J. Less-Common Metals, 10, 416 (1966). 20. H.C, Casey, Jr. and M. B. Panish, Reproducible Diffusion of Zine into GaAs: Applications of the Temary Phase Diagram and the Diffusion and Solubility Anal- ryses, Trans. Met. Soc, AIME 242, 406 (1968), PROBLEMS 1. You are provided with a phase diagram of the type shown in Fig, 2.2, where the abscissa is a linear scale based on wt. %. Develop the lever rule for this situation, 2. The latice parameters of GaAs, InAs and InP are 5.6532 A, 6.0883 A and 58687 A respectively. Determine the value of + for which a Ga,InAs layer is exactly latice matched to an InP substrate. Indicate this composition in Fig. 2. PROBLEMS 101 Assuming that the energy gap is given by E(x) = 0.356 + 0.7x + 0.4x7 calculate the wavelength corresponding to the lattice matched condition, . Assuming Vegard’s law, show that the lattice parameter of the quarternary alloy Ga,Iny_.AsyP).y is given by: (Garin, ,As,P)-y xyla(GaAs)] +x(1 ~ y){a(GaP)] +1 = x)la(InAs)] + (1 =.) — y)factnPy] Can you suggest a reason why anyone would want to use a quatemary alloy of this type in preference 0 a temary? The lattice parameters of GaAs, InAs, GaP and InP are 5.6532 A, 6.0583 A, 5.4512 A and 5.8687 A respectively. Determine the composition of GalnAsP which can be grovn lattice matched to InP substrates, for phosphorus frac- tions of 0.15 and 0.5. Assuming Vegard’s law, determine the (approximate) energy gap for these compositions. Assume that the energy gaps for GaAs, MAS, GaP, and InP are 1.42 eV, 0.36 eV, 2.26 eV and 1.35 eV. respectively, From a study of Fig. 2.12, can you determine a simple criterion for differ entiating a peritectic compound from a congruent transformation?CHAPTER 3 —_——_—_$ $$$ CRYSTAL GROWTH AND DOPING Demands placed on the quality of starting materials have become more severe as device dimensions have shrunk and packing densities have increased. Today, the requirements for very-large-scale integration (VLSI) circuits necessitate large- diameter crystals, virtually free of dislocations and variations in radial and axial resistivity. These goals have not been achieved; however, progress in this area has been very rapid. This chapter describes common techniques for growing single-crystal silicon and GaAs of « quality suitable for commercial device and microcireuit fabrication. Doping of the starting materials in the melt is also considered, followed by a discussion of the properties of material grown by these methods. Semi-insulating (SI) GaAs is of high commercial importance, since it is the starting material for integrated circuits made with this semiconductor. Details of its methods of growth and the properties of the resulting materials will also be covered in this chapter. Relevant tables are collected at the end ofthis chapter 3.1 STARTING MATERIALS Polycrystalline silicon is used as the starting material from which device- quality, single-crystal silicon is grown. Silicon is commercially synthesized by heating silica, which is widely present in the earth's surface, and carbon, in an electric furnace with a reducing gas ambient. The resulting material is only 95-97% pure, Further purification is usually carried out by converting it 10 trichlorosilane and chemically processing this compound until it is 99.99999% (seven nines) pure. Semiconductor-grade polycrystalline silicon is made by its 102 3.1 STARTING MATERIALS 103 thermal decomposition in a hydrogen atmosphere, at a temperature of around 1100°C. This is used as the starting material for the manufacture of single- crystal silicon. The impurity content of polycrystalline silicon, produced by this, process, as well as that of single-crystal silicon which is made from it by melting and recrystallization, is listed in Table 3.1 [1]. Additional impurities become incorporated in this material during crystal growth, as well as during the various processing sequences which are used to form the final microcircuit. Gallium, which is a relatively scarce material, is found in nature as a trace element in germanite ore, from which it can be purified. Arsenic, on the other hand, is quite abundant. It is found in ores in the form of sulfides and arse- nates, but most commonly in arsenopyrite from which it can be extracted by heating. Both gallium and arsenic, upon subsequent purification to a seven nines (99.99999%) level, are used as the starting materials for the synthesis of poly. crystalline GaAs. The formation of GaAs, with near-perfect stoichiometry, is complicated by the highly different vapor pressures of its individual compo- nents, Moreover, the formation reaction is exothermic, and proceeds with con- siderable violence, GaAs must be synthesized in an overpressure of arsenic in order 10 avoid simultaneous decomposition into its separate constituents. The appropriate arsenic pressure over molten GaAs is seen from Fig. 1.19 to be about 1.0 atm, This pressure can be established by conducting the reaction in a scaled tube maintained slightly above 1238°C, with a precisely measured quantity of arsenic. A more practical approach is to provide what is essentially an infinite supply of arsenic which is maintained at a lower temperature. For this situation, the pressure in the tube is approximately equal to the equilibrium vapor pres. Sure of the volatile component (arsenic) at the lower temperature. Values for these vapor pressures arc displayed in a pressure-temperature (P_T) diagram [2], as shown in Fig. 3.1. Here the solid curve shows the pressure of gaseous arsenic over GaAs, which is necessary to prevent decomposition of the com- pound, as a function of the temperature at which the compound is maintained. ‘The dashed curve in this figure shows the pressure of gaseous arsenic over Solid arsenic for this same temperature range, as obtained from standard vapor Pressure tables. From these curves it is seen that the required arsenic over- Pressure to avoid decomposition can be achieved by keeping the ele- mental arsenic at about 600-620°C, while the GaAs is maintained at around 1240-1250°C. Figure 3.2 shows an evacuated quartz sealed-tube configuration which can be used for the synthesis of GaAs, in a furnace with two temperature zones. ‘The boats in this figure are usually made of quartz, and sometimes of graphite, because of its closer thermal expansion match to GaAs. Increasingly, however, Pyrolytic boron nitride (PBN) boats are used to meet the purity requirements of modem devices and integrated circuits, In operation, one boat is loaded with a charge of pure gallium, with the arsenic kept in a separate boat. A plug of quartz wool is often placed between these boats to act as a diffuser. Next, the tube is evacuated, sealed, and brought104 CRYSTAL GROWTH AND DOPING leper er pram pwn pop epee oC 7 ‘ 4 —_\\ _ | \ 4 \, | 4 NO] 4 » \ S-ENE-48—8 4-8-8 tits ot 4 Li L tid sey, — Fig. 3.1 PT projection of the system G: permission from Philips Research Reports ‘As, From Boomgaard and Scholl (2). With up to system temperature, as shown in Fig. 3.2. This results in the transport of arsenie vapor to the gallium, with its conversion into GaAs in a slow, controlled ‘manner. Such a process typically takes many hours to accomplish, for a starting charge of a few kilograms of gallium. A pressure-composition (Px) diagram can also be drawn by combining the P-T diagram with the phase diagram (Tx) for the gallium-arsenic system (Figs. 2.10 and 2.11). This diagram is shown in Fig. 3.3 and illustrates the necessity for maintaining extremely close control of the arsenic overpressure in order to avoid departures from stoichiometry in the resulting GaAs. This is Tht ott tt 600-620" 1240-1260°C ig. 32 Sealed-tube system for gallium arsenide synthesis ‘3.1 STARTING MATERIALS = 105, SET ons Atti 10 20 30 40 50 60 70 Ge Axomie % atenie—> Fig. 3.3 Px diagram for gallium arsenide. From Boomgaard and Scholl [2]. With permission from Philips Research Reports usually done by selecting the precise arsenic temperature by a trial-and-error Process, Polycrystalline GaAs, formed in this manner, is often used as the starting ‘material for single-crystal growth. It is also possible to convert gallium and arsenic directly into single-crystal GaAs by a process known as in situ, or direct, ‘compounding. This is carried out by reacting these elements in a pressurized vessel, ata temperature of around 700°C, which is well below the melting point of 1238°C, Alternatively, the reaction can be carried out at high temperatures in low-pressure vessel, provided this is done is a very slow, controlled manner. ‘These processes will be described in Section 3.2.1.2. The impurity content of typical undoped GaAs, as measured [3] by spark Source mass spectrometry, is listed in Table 3.2 at the end of this chapter.‘106 CRYSTAL GROWTH AND DOPING 3.2 GROWTH FROM THE MELT Single crystals can be grown by controlled freezing of a melt in a boat or ampoule. This approach has the disadvantage of possible adhesion of the freezing melt to the walls. Contact of this type can initiate the formation of dislocations, and special care must be taken to minimize this effect. Altemative approaches, such as the Czochralski (CZ) and float zone (FZ) techniques, allow the crystal to be grown with a free surface and thereby avoid this problem, Silicon is almost universally grown by these methods, and in particular by the CZ technique. This technique is increasingly used for GaAs as well; however, boat-grown material has some important advantages, and is used in a number of applications. 3.2.1 The Czochralski Technique Figure 3.4 shows the schematic of a CZ system which can be used for both silicon [4] and GaAs [5] crystal growth. Here, the melt is contained in a crucible and kept in a molten condition by heating. A seed crystal, suitably oriented, is, suspended over the crucible in a chuck. For growth, the seed is inserted into the ‘melt until its end is molten. It is now slowly withdrawn, resulting in a single crystal which grows by progressive freezing atthe liquid-solid interface. A pull rate of about 50-100 mm/hr is typical for both silicon and GaAs. Provisions are also made to rotate the crystal, and sometimes the crucible as well, during the pulling operation. A series of annular heat shields are provided between the growth region and the walls of the reactor, in order to control radial thermal gradients during the solidification process, For silicon the entire assembly is enclosed within an envelope which is water-cooled and flushed with an inert gas. With GaAs, on the other hand, itis important to prevent decomposition of the melt during crystal growth by main- taining an overpressure of about 1.0 atm of arsenic. In principle, this can be done by maintaining the entire chamber at high temperature (600-620°C), 10 prevent arsenic condensation on its walls. In practice, however, this is extremely difficult to accomplish because of the highly corrosive nature of arsenic at these temperatures. Modified approaches, to be described later, are used for this pur- pose Most modem crystal pullers of the CZ type are resistively heated, and use replaceable crucible liners. Direct-current heating is generally used to prevent induced movement in the melt by eddy currents. In some systems, three-phase ac. has been used to set up contra-rotation of the melt in order to control the growth conditions. Carbon contamination occurs in both silicon and GaAs CZ. systems. Gener- aily, this comes about because of the reaction of moisture with hot carbon com- ponents and fittings, such as susceptors, crucible supports, and heaters, which ‘are within the growth chamber. This produces carbon monoxide, which is sub- | 3.2 GROWTH FROM THE MELT 107 Thermocouple — power (or Crucitie et Graphite 7 a, or quant Gas N To contoter cutet Fig. 34 Czochralski crystal-growing apparatus Sequently incorporated into the melt. Some carbon is also present in the starting ‘materials, as a contaminant. Fused quartz crucibles are used for silicon growth, Considerable dissolution Of this vessel takes place by the corrosive action of the molten silicon, resulting in the formation of SiO [6]. A large amount of this material is incorporated as dissolved oxygen in the crystal, with some evaporation of SiO from the melt into the ambient. In addition, impurities such as iron and carbon are incorpo- tated from the silica crucible, which is usually 99.6% pure. The incorporation of these materials increases with spin rate. As a result, silicon crystals are rotated very slowly (=1—10 rpm) during CZ. growth, Fused silica cannot be used for the growth of GaAs since silicon isa shallow donor and oxygen is a deep donor (see Section 1.5.1.3). Here, materials such as ‘graphite, graphite coated with pyrolytic graphite, alumina, and PBN have been used; of these, PBN has been found to give a two-decade reduction in impu- rity incorporation over other materials (7], and is the universal choice today.(108 = CRYSTAL GROWTH AND DOPING GaAs, grown in these crucibles, is weakly p-type because of residual carbon incorporation, ‘An inert gas ambient is used in CZ crystal growth, sometimes at slightly reduced pressure, to promote the evaporation of contaminants. In silicon crystal pullers, provision is sometimes made for operation at 2-50 torr to promote the ‘evaporative loss of SiO, and thus reduce the amount of dissolved oxygen in the crystal. Both argon and nitrogen gas have been used for GaAs growth. Recent work [8] has shown that the use of krypton gas results in material of higher purity than is obtained with either of these gases. It has been proposed that this improvement comes about because krypton has the lowest heat transfer coefficient of these gases, and thus reduces temperature gradients in the grown crystal. It is necessary that the latent heat of fusion be removed from the crystal-melt system during the growth process. This heat is lost by radiation from the crystal surface and by thermal conduction along the crystal axis. A detailed treatment of crystal growth, based on the interaction of these terms, is beyond the scope of this book. However, we can arrive at a number of important conclusions based con some simplifying assumptions. For example, since growth is accomplished by withdrawal of a solidified crystal, it follows that the maximum pull rate is limited by the rate at which the crystal can freeze (i, by the axial thermal gradient in the solid) near the growing interface. Analysis has shown that this thermal gradient is inversely proportional to the square root of the crystal dia- meter [9]. This result has also been experimentally verified {10}. If A; is the rate of heat input to the system, and H, is the rate of heat loss, then the difference H,, ~ H; is largely accounted for by the latent heat of erys- tallization, L. Writing p as the density and A as the cross section of the growing crystal, respectively, the heat balance equation based on this assumption is Hy ~ Hy = ALp(ds/dt) Bn) where dx/dr is the pull rate. From this equation, it can be seen that the erystal diameter can be controlled by adjusting the heat input and/or the pull rate, In 2 practical situation, this type of control is used in the early phases of growth to expand the seed to the required crystal diameter, and also during growth to maintain this diameter within process tolerances. Once a steady-state dia: meter is achieved, a feedback control system is necessary to hold the temper- ature within 49.5°C, even though thermal conditions are continually changing as the melt becomes depleted. Usually, the diameter of the growing crystal is optically measured by a remote video camera, or a sensitive load cell is used to measure variations in its weight. Diameter adjustments can be made during crystal growth, using the information derived in this manner. With GaAs, dia- meter control can be achieved by means of a disc of SisNs, with a hole of the appropriate size. This disc, known as a coracle, floats on the molten liquid and defines the resulting crystal dimension. This technique has been found 10 be (3.2 GROWTH FROM THE MELT = 109 suitable for growth in the (111) directions, but causes problems with twinning during (100) growth, Both techniques allow diameter control to within 42%, Thermal stresses are created during cool down of the crystal as it is pulled in ‘the CZ apparatus. In GaAs, these stresses can cause the crystal to shatter during subsequent slicing into wafers, or in subsequent processing. A long, slow anneal at around 950°C in an evacuated, sealed ampoule is necessary after growth to relieve these stresses and to homogenize defects in the material. This also improves the uniformity of electrical parameters such as resistivity and mobility over the entire crystal. Similar heat treatments are often given to silicon as well, although its surface fracture strength is about three times that of GaAs. In this case, their primary function is to homogenize the dissolved oxygen in the crystal 3.2.1.1 Liquid Encapsulation Czochralski growth of GaAs is seriously hampered by the need for maintaining an arsenic overpressure of about 1.0 atm during growth, This can be done by Keeping the entire chamber hot, at about 600-620°C, Unfortunately, arsenic is highly reactive at these temperatures, thus greatly restricting the choice of materials for this purpose, The liquid encapsulated Czochralski (LEC) technique hhas been developed to avoid these problems, and consists of using a cap layer of an inert liquid to cover the melt (I1, 12]. This cap prevents decomposition of the Gas as long as the pressure on its surface is 1.0 atm or more. This pressure can be readily provided by means of an inert gas such as helium, argon, or nitrogen. Requirements on this cap are that it float on the GaAs surface without mixing, be chemically stable, and have a low vapor pressure at the melting point of GaAs. In addition, it should be optically transparent so that the crystal can be viewed during growth, and impervious to the diffusion of arsenic (which is the volatile component). Although success has been obtained with materials such as BaCl and CaCl, BOs is most commonly used for this purpose. BOs has a density of 1.5 g cm” as compared to 5.71 g cm™ for GaAs, Moreover, its vapor pressure at the melting point of GaAs is below 0.1 torr, although it melts at 450°C. Cap layer thicknesses of BO; range from 5 to 10 mm; some ‘work [13] has indicated that the use of thicker cap layers (19-27 mm) reduces the etch pit density by a factor of 5. ‘The LEC technique is found to result in almost no oxygen contamination of the GaAs. Typically, the incorporated boron content is in the 10" to 10"°-em-> range. Furthermore, it has been observed that impurities initially present in the B.O; cap remain preferentially in this layer, rather than becoming incorporated into the GaAs, The residual contamination in this material is usually carbon, which is p-type The presence of the BO; cap modifies thermal conditions in the freezing crystal, since the heat transfer coefficients of this layer are 10-20 times larger ‘than that of the gas ambient. This introduces large thermal gradients as the110 CRYSTAL GROWTH AND DOPING: freezing crystal emerges from the cap. One approach to circumventing this problem is to use a thick cap layer, and to limit the growth to a short crystal which is grown entirely under the cap layer. This approach [14], known as the liquid encapsulated Kryopoulos (LEK) technique, results in crystals with a lower dislocation content. However, it has not received significant attention, because of its higher cost as compared to the LEC method. 3.2.1.2 Direct Compounding ‘There is considerable economic advantage to combining, in a single system, (a) the synthesis of Gas from its elements and (b) the growth of the single-crystal material. Moreover, many of the contaminants in GaAs are incorporated during the compound formation operation described in Section 3.1, Thus the avoidance of this step, by in situ compounding in a CZ. system, is highly desirable. ‘The vapor pressure of arsenic (over arsenic) at the melting point of GaAs is about 60 atm. Initially, this has prevented direct compounding. However, the availability of crystal pullers which can operate at as high as 150 atm, in com- bination with the liquid encapsulation technique, makes this process feasible. Here, high-purity gallium and arsenic, in near-stoichiometric proportion, are placed in a PBN crucible liner within a heated graphite container [15]. Vacuum- baked BOs, with a controlled amount of water added, is placed on its surface and the system pumped down to remove volatile oxides. The system is now pressurized to 3 atm of nitrogen and heated to 450°C, so that the BO; melts. Next the pressure is raised to about 60 atm and the crucible heated slowly 10 700°C, at which point the reaction of gallium with arsenic takes place. Once complete, the pressure is reduced to about 2 atm and the crucible temperature raised so as to be slightly above the melting point of GaAs (1238°C). A single crystal is grown by inserting a seed crystal in the melt, and pulling in the manner described earlier. High-purity material can be grown by this approach [16] ‘The high-pressure LEC technique (HPLEC) described here is routinely used in the manufacture of GaAs crystals up to 75-100 mm in diameter. Methods have also been developed for compounding GaAs at low pressures (LPLEC) using an injection system, by which arsenic can be added to a melt of gallium in a slow, controlled fashion [17] Pethaps the greatest advantage of the LPLEC method is a commercial one, in that it allows the use of low-pressure (1-5 atm) crystal pullers of the type commercially used for the growth of silicon, with only minor modifications to improve the thermal shielding [18]. These machines have benefited from many years of operational experience, so that their use should result in rapid reductions in the cost of single-crystal GaAs slices. 3.2.2 Gradient Freeze Techniques Both silicon and GaAs can be grown by gradient freeze methods; in fact, early efforts [19, 20] concentrated on this approach for growing single-crystal mate- 9.2 GROWTH FROM THE MELT = 111 rials. Even today, this technique is used to produce material with the lowest dislocation densities. In one approach, the polycrystalline starting material is loaded into a long, horizontal boat, and melted. The melt is now cooled from ‘one end, which is usually necked down in order to restrict nucleation to a (hope- fully) single event during freezing. This allows a single grain to propagate at the iquid-solid interface. Eventually the melt is frozen to take up this crystalline structure, A boat that is suitable for crystal growth by this technique has a seed crystal placed in the narrow end in order to establish a specific crystallographic orientation, ‘An alternative approach is t0 use a vertical ampoule, which is necked down at the bottom end in which a single-crystal seed is placed. Again, the melt is, progressively cooled from this end until the single-crystal growth propagates over the entire volume of the semiconductor. Gradient freeze techniques can be implemented by moving the boat or ampoule in an appropriate temperature gradient, by moving the furnace as shown in Fig. 3.5 [21]. Yet another approach is to use a furnace which has a large number of narrow heat zones (22), which can be separately computer controlled in order to dynamically alter the temperature gradient profile during crystal growth, ‘The range of techniques outlined here can be described generically as gra- dient freeze (GF) methods. These include horizontal gradient freeze (HGF) and vertical gradient freeze (VGF), depending on the orientation of the semicon. ductor material during crystal growth. Silicon is rarely grown by GF techniques. In the HGF process, the GaAs boat, which is typically 50-100 em long and 100-50 mm wide, is sealed in a long quartz ampoule, with a suitable amount of high-purity (99.99999%) arsenic placed at one end. A loose plug of quartz ‘wool is placed between the boat and the arsenic source, The arsenic is held at a temperature of 617°C + 1°C throughout the growth run so as to maintain an As overpressure of about I atm in the system. Typical values for the temperature gradient are 10°C/em, with a heater travel of 15-20 mm/hr. Seal erystal Gall rene (et) 1240 - 1260" I Temperature 610-620" ‘irecton of fester tava —— Fig. 35. Gradient freeze system.‘112 CRYSTAL GROWTH AND DOPING During a typical growth run, an initial temperature profile is set up so that the GaAs charge is in a molten state, at 1241°C, and the arsenic is at 617°C. Next, the temperature profile is retracted slightly (towards the left in Fig. 3.5) in order to back up onto the seed. This is done by moving the furnace or by controlling its heater windings, and serves to establish a molten interface between the seed and the charge. Next, the profile is moved forward slowly (to the right in Fig, 3.5) to allow the solidification of single-crystal GaAs to occur. Simultaneously, the temperature of the solid GaAs is lowered to 129°C, and held at this value across the entire solidified length in order to minimize thermal gradients in the grown crystal. A similar approach is used in the case of VGF growth ‘The boat or ampoule used in these systems must fulfill two requirements. First, it must be of high purity to prevent crystal contamination, Next. it should not touch the growing crystal at any point, since twinning can be nucleated at points of adhesion between it and the freezing melt. Carbon-coated quartz, Vitreous carbon, and lately PBN are in use today. PBN is the material of choice because its purity level is considerably higher than that of quartz or vitreous. carbon. Often, these are provided with a rough, sandblasted finish to minimize the possiblity of contact with the melt. A woven quartz pad is sometimes placed in the container, with the melt floating on its surface by surface tension. Crystal growth of GaAs by the GF technique is usually carried out in the (111) direction which is the preferred direction for low defect growth, although the (110) orientation is sometimes used. Most device applications require (100) ‘material, as pointed out in Section 1.4.2. Consequently, the D-shaped ingot resulting from the HGF process must be sawed at an angle 10 its growth axis (54.74° for (111)), or along the axis if the crystal is grown on in the (110) direction. Any variation in doping along the erystal growth axis will thus show up as a variation across the resulting slice. Crystals grown in this manner are sometimes sold “as is.” or are cut to a circular profile before sale. Although HGF material is grown in a hot wall furnace, vertical temper ture gradients of about +0.5°C are still present [23], due to gravitational effects which create convection currents in the melt. These, as well as axial gradients (of about £0.1°C), can be minimized in modem faraces which have multiple quadrant as well as axial heat zones. Using these systems, itis possible to grow crystals, 57.5 cm wide, with dislocation densities under 5000/em Liquid encapsulation can also be used with the VGF method [24], as shown schematically in Fig. 3.6. Here, a PBN ampoule, which is open at the top, serves to confine the crystal, This crucible is tapered at the bottom in order to hold the seed crystal. The ampoule is held in a pressurized furnace with muliple heater windings which are computer-controlled to adjust the temperature gra dient during crystallization. As before, special care must be taken to prevent sticking of the melt to the crucible walls at any point, to avoid dislocation for- mation, Both radial and axial thermal gradients in VGF systems are lower than in HGF systems, Consequently, the resulting GaAs has a lower dislocation content. Here, 5 to 7.5-cm-diameter crystals have been grown, with dislocation densities 3.3. CONSIDERATIONS FOR PROPER CRYSTAL GROWTH = 113 O— mitveenens ter Weng (00000000000000 000 We 8 8 8 8 8 8 8 3 8 8 8 8 8 8 0000001 Fig. 3.6 Vertical gradient freeze apparatus as low as 100-3000/em*. Again, the (111) growth direction is favored, so that (100) material is obtained by slicing the boule at $4.74°C to its growth axis. 3.3 CONSIDERATIONS FOR PROPER CRYSTAL GROWTH The problems of growing large area silicon and GaAs crystals are essentially similar, except that they differ in degree. The critical resolved shear stress of silicon is about four to five times that of GaAs. At the same time, the stacking fault energy is about 50% larger, so that the tendency for dislocation formation is much lower. On the other hand, industry requirements are for silicon crystals whose diameter is larger than that of GaAs by a factor of 2-3. With GaAs, smali departures from stoichiometry can greatly alter its mechanical strength, with a resultant increase in the defect density in the grown crystal. This problem does. not arise with silicon, which is an elemental semiconductor. In this section we describe the various factors which must be taken into account in order to grow single crystals which are relatively free from defects. Many of the consider- ations outlined here apply to both CZ and GF growth techniques. However, the emphasis will be on the CZ approach because of its greater commercial importance, 3.3.1 The Role of Point Defects In Chapter 1, it was shown that the concentration of point defects in silicon and GaAs is an exponential function of the crystal temperature. The equilib-