Scribd
Upload
55 views

PROJECT #1: SRAM Design and Layout: EE 7325 Advanced VLSI Design

This document provides details for Project #1 of the EE 7325 Advanced VLSI Design course at Spring 2012. Students are tasked with designing and laying out a 512-bit or larger SRAM using the IBM 90nm process with specific design tools. The project will be graded based on memory cell size, area per bit, read time, write time, report clarity, and a demonstration to the TA. The report must include waveform demonstrations, layout with sizing, DRC and LVS reports, memory cell area, overall area, and area per bit.

Uploaded by

Nandeesh Gowda
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
55 views

PROJECT #1: SRAM Design and Layout: EE 7325 Advanced VLSI Design

This document provides details for Project #1 of the EE 7325 Advanced VLSI Design course at Spring 2012. Students are tasked with designing and laying out a 512-bit or larger SRAM using the IBM 90nm process with specific design tools. The project will be graded based on memory cell size, area per bit, read time, write time, report clarity, and a demonstration to the TA. The report must include waveform demonstrations, layout with sizing, DRC and LVS reports, memory cell area, overall area, and area per bit.

Uploaded by

Nandeesh Gowda
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

EE 7325 Advanced VLSI Design

Spring 2012 Prof. Carl Sechen

PROJECT #1: SRAM Design and Layout


Due: Wednesday March 21 (4 pm) Project Description Design and layout a 512 or more bit SRAM using the IBM 90nm process. The key design tools you will use are Cadences Virtuoso for layout editing, Calibre DRC (for design rule checking), Calibre LVN (layout versus netlist, for verifying that the layout matches the schematic netlist) and circuit simulation (for measuring the read/write times). Use an output capacitance of 30fF for all your outputs when simulating for delays. All input signals, and clocks (if used), are provided by inverters sized: pMOS=0.75um and nMOS=0.25um. In other words, measure the delay from the output of this fixed size inverter. Two points: 1) obviously you do NOT layout this inverter since it just simulates the fact that the inputs invariably come from fixed drivers, and 2) you may use two of these inverters back-to-back to form a buffer, so you dont have to worry about inversion of signals; in this case, measure input arrival from the output of the buffer (2 nd inverter). NOTE: you may input an ideal step function into this inverter (or buffer). Grading Criteria (Competitive) 1. Memory cell size 2. Area/bit 3. Read time 4. Write time 5. Report clarity 6. Demo to the TA Report includes at least the following: 1) A cover page containing all the following information. Name, student number (netID), EE7325, and project title 2) Show waveforms that demonstrate the worst-case read time and worst-case write time 3) Show evidence that the SRAM operates correctly 4) Print out of the complete layout with rulers clearly showing sizes 5) DRC and LVS reports 6) Memory cell area 7) Overall SRAM area 8) Area/bit

You might also like