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Department CSE, SCAD CET

The document discusses potential race conditions that can occur with shared memory access between threads. It provides examples where the final value of a shared variable accessed by multiple threads can depend on thread timing and ordering. Even single instruction access by each thread could cause interleaving. Data races can also occur from synchronized access that is synchronized at too low a level, such as simultaneously inserting the same key into a list. Building locks into low-level components is often unnecessary overhead since higher-level components will require their own higher-level locks.

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19 views

Department CSE, SCAD CET

The document discusses potential race conditions that can occur with shared memory access between threads. It provides examples where the final value of a shared variable accessed by multiple threads can depend on thread timing and ordering. Even single instruction access by each thread could cause interleaving. Data races can also occur from synchronized access that is synchronized at too low a level, such as simultaneously inserting the same key into a list. Building locks into low-level components is often unnecessary overhead since higher-level components will require their own higher-level locks.

Uploaded by

bsgindia82
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© © All Rights Reserved
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Download as DOC, PDF, TXT or read online on Scribd
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The example shows two threads trying to add to a shared variable x, which has an initial value of 0.

Depending upon the relative speeds of the threads, the final value of x can be 1, 2, or 3. pdate operations such as !" are normally #ust shorthand for temp " x$ x "temp!1 , and hence can result in interleaving. %ometimes the shared location is accessed by different expressions. %ometimes the shared location is hidden by function calls. &ven if each thread uses a single instruction to fetch and update the location, there could be interleaving, because the hardware might brea' the instruction into interleaved reads and writes. (ntel Thread )hec'er is a powerful tool for detecting potential race conditions.

Department CSE, SCAD CET

example, threads may be reading a location that is updated asynchronously with a latest current value.(n such a situation, care must be ta'en that the writes and reads are atomic. *or example, reads and writes of structure types are often done a word at a time or a field at a time. Types longer than the natural word si+e, such as ,0-bit floating-point, might not be read or written atomically, depending on the architecture. Data races can arise not only from unsynchroni+ed access to shared memory, but also from synchroni+ed access that was synchroni+ed at too low a level. (f two threads both attempt to insert the same 'ey at the same time, they may simultaneously determine that the 'ey is not in the list, and then both would insert the 'ey.

./igher-0evel 1ace )ondition &xample.

2uilding loc's into low-level components is often a waste of time, because the high-level components that use the components will need higher-level loc's anyway.

The lowerlevel loc's then become pointless overhead. *ortunately, in such a scenario the high-level loc'ing causes the low-level loc's to be uncontended, and most loc' implementations optimi+e

Department CSE, SCAD CET

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