A

Compal Confidential
KALG1 M/B Schematics Document
2

Intel Penryn Processor with Cantiga + DDRIII + ICH9M

2009-03-02
REV 02
3

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Page
Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
E

of

45

Compal Confidential
Model Name : KALG1
File Name : LA-5271P

Intel Penryn Processor

Fan Control

Thermal Sensor

Clock Generator

EMC 1402

ICS9LPRS387

page 4

uPGA-478 Package
(Socket P) page

LCD Conn.

page 24

page 16

4,5,6

FSB

667/800/1066MHz

H_A#(3..35)

HDMI Conn.

page 4

H_D#(0..63)

CRT Conn.

page 17

TMDS

page 18

LVDS
HDMI
ASM1442T

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

Intel Cantiga

LVDS

Dual Channel
1.5V DDRIII 800

uFCBGA-1329
PCI-Express

page 14,15

BANK 0, 1, 2, 3

page 7,8,9,10,11,12,13

page 24

DMI

USB conn x3

C-Link

USB port 0, 1, 6
2

page 29

PCI-Express

Intel ICH9-M

3.3V 48MHz

Bluetooth
Conn

LAN(GbE)

MINI Card x1

ATHEROS AR8131

AES1610

NEW Card

page 29

USB
HD Audio

BGA-676

Card Reader
RTS5159-GR

page 20,21,22,23

page 25

WLAN

ESATA
Conn.
page 29

CDROM
Conn.
page 23

GMCH HDA

port 0

RJ45
page 27

page 28

port 1

page 28

port 2

page 26

Finger Print

page 17

page 29

3.3V 24.576MHz/48Mhz
S-ATA

LS-4494P

CMOS
Camera

page 08

MDC 1.5
Conn
page 32

SATA HDD
Conn.
page 23

HDA Codec
ALC888S-VC
page 33

Audio AMP
APA2051

page 34

LPC BUS

Phone Jack x3

ENE KB926

page 34

page 30

RTC CKT.
page 20

Int.KBD

Touch Pad

page 31

page 31

Power On/Off CKT.

page 32

DC/DC Interface CKT.

page 37

BIOS

CIR

page 31

page 30

Power Circuit DC/DC

page 38,39,40,41,42,43
2008/11/10

Issued Date

POWER SW

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Page 36

Date:

Block Diagrams
Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
E

of

45

SIGNAL

STATE

Voltage Rails

Full ON

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S5

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

N/A

N/A

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

N/A

N/A

ON

OFF

OFF

ON

OFF

OFF

1.05V switched power rail

ON

OFF

OFF

1.5V power rail for HDA

ON

ON

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.8V

1.8V power rail for NB(LVDS)

ON

ON

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

Vcc
Ra/Rc/Re

Power Plane

Description

S1

S3

VIN

Adapter power supply (19V)

N/A

B+

AC or battery power rail for power circuit.

N/A

+CPU_CORE

Core voltage for CPU

+0.75VS

0.75VS power rail for DDR3 terminator

+1.05VS
+1.5V

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Board ID / SKU ID Table for AD channel

+3V_LAN

3.3V power rail for LAN

ON

ON

ON

Board ID

+3V

3.3V power rail for SB

ON

ON

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5V

5V power rail for SB

ON

ON

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

0
1
2
3
4
5
6
7

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0

V AD_BID min
0 V

V AD_BID typ
0 V

V AD_BID max
0 V

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table
Board ID
0
1
2
3
4
5
6
7

External PCI Devices

Device

IDSEL#

EC SM Bus1 address
3

Device

Address

Smart Battery

0001 011X b

REQ#/GNT#

Interrupts

EC SM Bus2 address
Device

BTO Option Table

BTO Item
GL40
GM45

Address
1001 100X b

EMC1402

PCB Revision
PCB 08Y LA-5271P REV0 M/B

BOM Structure
GL40@
GM45@

BOM Configuration Table

Project
KALG1-GM45
KALG1-GL40

ICH9M SM Bus address

Device

Address

Clock Generator
(ICS9LPRS387, SLG8SP556V)

1101 001Xb

DDR3 DIMMA

1001 000Xb

DDR3 DIMMB

1001 010Xb

BOM Configuration
GM45@/KALG1@/KAL90_G0_90+@
GL40@/KALG1@/KAL90_G0_90+@

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Notes List
Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
E

of

45

[7]

H_A#[3..35]

H_A#[3..35]

H_REQ#[0..4]

[7] H_REQ#[0..4]
[7]

H_RS#[0..2]

H_RS#[0..2]

FAN1 Conn
+5VS

JCPU1A

A20M#
FERR#
IGNNE#

[20]
[20]
[20]
[20]

H_STPCLK#
H_INTR
H_NMI
H_SMI#

D5
C6
B4
A3

STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

IERR#
INIT#

D20
B3

C1
F3
F4
G3
G2

HIT#
HITM#

G6
E4

1
EN_DFAN1

H_IERR#

1
H_INIT#

[20]
0.1U_0402_16V4Z

H_LOCK# [7]
H_RESET#
H_RS#0
H_RS#1
H_RS#2

+VCC_FAN1
2 R43
1
300_0402_5%

D16
1SS355_SOD323-2

8
7
6
5

GND
GND
GND
GND

C73

[7]

H_HIT#
H_HITM#

[7]
[7]

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_BPM#5
XDP_TCK
XDP_TDI

PROCHOT#
THERMDA
THERMDC

D21
A24
B25

H_PROCHOT#
H_THERMDA
H_THERMDC

THERMTRIP#

BAS16_SOT23-3
C88
10U_0805_10V4Z
1
2

H_RESET# [7]

H_TRDY#

D15

APL5605KI-TRL SOP 8P

+3VS

C82
1000P_0402_50V7K
1
2

H4

[30]

VEN
VIN
VO
VSET

R46
10K_0402_5%

40mil
2

LOCK#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

[7]

JP27

+VCC_FAN1

1
2
3

[30] FAN_SPEED1
+1.05VS

XDP_TMS
XDP_TRST#
XDP_DBRESET#

ACES_85205-03001
CONN@

C83
1000P_0402_50V7K

XDP_DBRESET# [21]

C7

H_THERMTRIP# [8,20]

A22
A21

CLK_CPU_BCLK [16]
CLK_CPU_BCLK# [16]

OCP#

[21]

Q5
MMBT3904_SOT23-3
@

+1.05VS

XDP_TDI

R108 1

54.9_0402_1%

XDP_TMS

R109 1

54.9_0402_1%

XDP_BPM#5

R117 1

54.9_0402_1%

H_PROCHOT#

R53

56_0402_5%

H_IERR#

R52

56_0402_5%

XDP_TRST#

R107 2

54.9_0402_1%

XDP_TCK

R116 1

54.9_0402_1%

H CLK
BCLK[0]
BCLK[1]

2
R48 @
56_0402_5%

THERMAL

ICH

ADDR GROUP_1

M4
N5
T2
V3
B2
D2
D22
D3
F6

H_BR0#

U4

1
2
3
4

A6
A5
C4

F1

H_A20M#
H_FERR#
H_IGNNE#

H_DEFER# [7]
H_DRDY# [7]
H_DBSY# [7]

+5VS

10U_0805_10V4Z
2

[20]
[20]
[20]

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

H5
F21
E1

[7]
[7]
[7]

H_ADSTB#1

[7]

CONTROL

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

BR0#

H_ADS#
H_BNR#
H_BPRI#

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

K3
H2
K2
J3
L1

DEFER#
DRDY#
DBSY#

C81

H1
E2
G5

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

ADS#
BNR#
BPRI#

XDP/ITP SIGNALS

H_ADSTB#0

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

RESERVED

[7]

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP_0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

left NC if no ITP
@

39Ohm

Layout Note:
H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil

Penryn
CONN@

+3VS
C90
0.1U_0402_16V4Z
1
2
U5
H_THERMDA

C92

2200P_0402_50V7K
2

BSEL2

BSEL1

BSEL0

BCLK

266

200

166

H_THERMDC

VDD

SMCLK

DP

SMDATA

DN

ALERT#

THERM#

GND

EC_SMB_DA2 [30,31]

2
R49
10K_0402_5%

+3VS

EMC1402-1-ACZL-TR_MSOP8

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/11/10

Issued Date

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

EC_SMB_CK2 [30,31]

Title

Penryn (1/3) & FAN Conn

Size
B
Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
1

of

45

H_D#[0..63]

H_D#[0..63]

[7]
[7]
[7]

H_DSTBN#0
H_DSTBP#0
H_DINV#0

+1.05VS

R385
1K_0402_1%

R386
2K_0402_1%

R54
R55

H_DSTBN#1
H_DSTBP#1
H_DINV#1

2
2
C457 1

@
@
@

1
1
T28
T31

GTL_REF0
1K_0402_5%
TEST1
1K_0402_5%
TEST2
@
TEST3
PAD
0.1U_0402_16V4Z TEST4
TEST5
@
PAD

Width=4 mil ,
Spacing: 15mil
(55Ohm)

Trace Close CPU < 0.5'

[7]
[7]
[7]

[16] CPU_BSEL0
[16] CPU_BSEL1
[16] CPU_BSEL2

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Penryn

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

DATA GRP 2

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

DATA GRP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

DATA GRP 3

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP 0

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

JCPU1C

[7]
+CPU_CORE

JCPU1B

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DSTBN#2 [7]
H_DSTBP#2 [7]
H_DINV#2 [7]

H_DSTBN#3 [7]
H_DSTBP#3 [7]
H_DINV#3 [7]
COMP0
COMP1
COMP2
COMP3

R51
R50
R105
R106

1
1
1
1

H_PW RGOOD
H_CPUSLP#

2
2
2
2

27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%

H_DPRSTP# [8,20,43]
H_DPSLP# [20]
H_DPW R# [7]
H_PW RGOOD [20]
H_CPUSLP# [7]
PSI#
[43]

CONN@

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 16mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VSSSENSE

AE7

VSSSENSE

+CPU_CORE
D

+1.05VS

20mils
+1.5VS
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
1
R88

C426
[43]
[43]
[43]0.01U_0402_16V7K
2
2
[43]
[43]
10U_0805_10V4Z
[43]
[43]

2
100_0402_1%

+CPU_CORE

VCCSENSE [43]
VSSSENSE [43]

CONN@
R89

1
C425

2
100_0402_1%

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Penryn (2/3)
Size
B
Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
1

of

45

JCPU1D

1 2
+

C145
900P_PFAF250E128MNTTE_2.5VM

3 4

+CPU_CORE

C447

C448

C428

C429

10U_0805_6.3V6M

10U_0805_6.3V6M

C446

10U_0805_6.3V6M

10U_0805_6.3V6M

C445

10U_0805_6.3V6M

10U_0805_6.3V6M

C430

C431

+1.05VS
PVT

CONN@

C444

1
C440
2

C427

C449

C441

0.1U_0402_16V4Z

C182

0.1U_0402_16V4Z

330U_D2_2.5VY_R9M

0.1U_0402_16V4Z

1
.

0.1U_0402_16V4Z

Penryn

0.1U_0402_16V4Z

+CPU_CORE

0.1U_0402_16V4Z

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

10U_0805_6.3V6M

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

10U_0805_6.3V6M

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

C432

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/11/10

Issued Date

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Penryn (3/3)
Size
B
Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
1

of

45

[5]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+1.05VS

R349
221_0402_1%

H_SW ING
H_RCOMP

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C5
E3

R351
24.9_0402_1%

[4]
[5]

H_RESET#
H_CPUSLP#

H_RESET#
H_CPUSLP#

C12
E11

H_AVREF

A11
B11

width:spacing=10mil:20mil (<0.5")
1

R352
2K_0402_1%

H_SWING
H_RCOMP

width=10mil

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_CPURST#
H_CPUSLP#

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPW R#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

J8
L3
Y13
Y1

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

L10
M7
AA5
AE6

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L9
M8
AA6
AE5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

B15
K13
F13
B13
B14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

0.1U_0402_16V4Z

C409

100_0402_1%

R350

R353
1K_0402_1%

width=10mil

+1.05VS

H_A#[3..35]

U21A

H_D#[0..63]

HOST

H_AVREF
H_DVREF
CANTIGA B3_FCBGA1329

C413@
0.1U_0402_16V4Z

[4]

H_ADS#
[4]
H_ADSTB#0 [4]
H_ADSTB#1 [4]
H_BNR# [4]
H_BPRI# [4]
H_BR0#
[4]
H_DEFER# [4]
H_DBSY# [4]
CLK_MCH_BCLK [16]
CLK_MCH_BCLK# [16]
H_DPW R# [5]
H_DRDY# [4]
H_HIT#
[4]
H_HITM# [4]
H_LOCK# [4]
H_TRDY# [4]

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

[5]
[5]
[5]
[5]

[5]
[5]
[5]
[5]
B

H_DSTBP#0 [5]
H_DSTBP#1 [5]
H_DSTBP#2 [5]
H_DSTBP#3 [5]
H_REQ#[0..4]

H_RS#[0..2]

[4]

[4]

GM45@

within 100mil to Ball A11,B11

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Cantiga GMCH(1/7)-GTL
Size
B
Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
1

of

45

DDR3
+1.5V

MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_9
MCH_CFG_10

Use VGATE for GMCH_PWROK

VGATE

@
1
R101
ICH_PWROK 1
R100

[16,21,43] VGATE
[21] ICH_PWROK

GMCH_PWROK
2
0_0402_5%
2
0_0402_5%

MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

CFG

2 PM_EXTTS#0
10K_0402_5%
2 PM_EXTTS#1
10K_0402_5%
2 MCH_CLKREQ#
10K_0402_5%

1
R94
1
R84
1
R93

+3VS

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

BG22
BH21

SMRCOMP
SMRCOMP#

BF28
BH28

SM_RCOMP_VOH
SM_RCOMP_VOL

AV42
AR36
BF17
BC36

DDR3_SM_PWROK
SM_REXT
R338 1
SM_DRAMRST#

B38
A38
E41
F41

CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#

F43
E43

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AE41
AE37
AE47
AH39

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AE40
AE38
AE48
AH40

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

AE35
AE43
AE46
AH42

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

AD35
AE44
AF46
AH43

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

M_ODT0
M_ODT1
M_ODT2
M_ODT3
R340 1
R339 1

2
B
E

80 Ohm

R341

DDR3

[14]
[14]
[15]
[15]

+1.5V

+1.5V

2 80.6_0402_1%
2 80.6_0402_1%

Q6
MMBT3904_SOT23-3

Q7
MMBT3904_SOT23-3

1
C384
2

20mil

SM_VREF

DDR3

DDR3_SM_PWROK [32]
2
499_0402_1%
SM_DRAMRST# [14,15]
CLK_DREF_96M [16]
CLK_DREF_96M# [16]
CLK_DREF_SSC [16]
CLK_DREF_SSC# [16]

DDR3

@
1
R104

CLK_MCH_3GPLL [16]
CLK_MCH_3GPLL# [16]

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

[21]
[21]
[21]
[21]

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

[21]
[21]
[21]
[21]

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

[21]
[21]
[21]
[21]

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

[21]
[21]
[21]
[21]

CFG9

1 = iTPM Host Interface is Disabled

0 = Lane Reversal Enable
1 = Normal Operation * (Default)

CFG10

0 = PCIe Loopback Enable

1 = Disable * (Default)
00
01
10
11

CFG[13:12]

CL_RST#0 [21]

CL_VREF

CANTIGA B3_FCBGA1329

MISC

N28
M28
G36
E36
K36
H36

SDVO_SCLK
SDVO_SDATA
MCH_CLKREQ#

TSATN#

B12

MCH_TSATN#

B28
B30
B29
C29
A28

HDA_BITCLK_MCH
HDA_RST_MCH#
HDA_SDIN2_MCH
HDA_SDOUT_MCH
HDA_SYNC_MCH

HDA_BITCLK_MCH [20]
HDA_RST_MCH# [20]

1
HDA_SDOUT_MCH [20]R356
HDA_SYNC_MCH [20]

1
C164
SDVO_SCLK [24]
SDVO_SDATA [24]
MCH_CLKREQ# [16]
MCH_ICH_SYNC# [21]

DDPC_CTRLDATA

0 = Digital DisplayPort Disable

* (Default)
1 = Digital DisplayPort Device Present

MCH_CFG_5
MCH_CFG_6

R98

MCH_CFG_7
MCH_CFG_9
MCH_CFG_10
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16

2
33_0402_5%

(Default)

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled * (Default)
0 = Normal Operation
*(Default)
1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
* (Default)
1 = PCIE/SDVO are operating simu.

L_DDC_DATA

ME

ICH_PWROK

= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation *

*(Default)

0 = No SDVO Card Present

* (Default)
1 = SDVO Card Present
0 = LFP Disable
* (Default)
1 = LFP Card Present; PCIE disable

C34

CL_CLK0 [21]
CL_DATA0 [21]

* (Default)

0 = iTPM Host Interface is enabled

CFG6

R97

0 = DMI x 2
1 = DMI x 4

CFG5

CFG20
(PCIE/SDVO select)

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

011 = FSB667
010 = FSB800
000 = FSB1067

CFG[2:0]

B33
B32
G33
F33
E33

AH37
AH36
AN36
AJ35
AH34

1
C385

Strap Pin Table

+1.05VS

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

R102
1K_0402_1%

C171
0.1U_0402_16V4Z
2

SDVO_CTRLDATA
GFX_VR_EN

2
0_0402_5%

CFG19
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

C386

R103
1K_0402_1% +V_DDR3_DIMM_REF

0.1U_0402_16V4Z

2
E

330_0402_5%

2
B
3

2
1

R58
MCH_TSATN#

MCH_TSATN_EC# [30]
1

R57
1K_0402_5%
R61
54.9_0402_1%

R56
1K_0402_5%

+1.05VS

HDA

+3VS

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

NC

+3VS

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

C387

SM_RCOMP_VOL

For Cantiga

SM_RCOMP_VOH
SM_RCOMP_VOL

[14]
[14]
[15]
[15]

SM_RCOMP
SM_RCOMP#

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

R342

SM_DRAMRST# would be
needed for DDR3 only

0.01U_0402_16V7K

M_ODT0
M_ODT1
M_ODT2
M_ODT3

[14]
[14]
[15]
[15]

SM_RCOMP_VOH
1

0.01U_0402_16V7K

BD17
AY17
BF15
AY13

SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

BA17
AY16
AV16
AR13

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

2
1
3.01K_0402_1%

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

R343
1K_0402_1%

[14]
[14]
[15]
[15]

2
1
1K_0402_1%

BC28
AY28
AY36
BB36

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

[14]
[14]
[15]
[15]

[19,26,30] PLT_RST#
[4,20] H_THERMTRIP#
[21,43] PM_DPRSLPVR

R62 1
R70 1
R111 1

R29
B7
N33
P32
AT40
AT11
T20
R32

PM

[21] PM_SYNC#
[5,20,43] H_DPRSTP#
[14] PM_EXTTS#0
[15] PM_EXTTS#1

PM_SYNC#_R
PM_DPRSTP#_R
PM_EXTTS#0
PM_EXTTS#1
GMCH_PWROK
2 100_0402_5% MCH_RSTIN#
THERMTRIP#_R
2 0_0402_5%
DPRSLPVR_R
0_0402_5%
2
2 0_0402_5%
2 0_0402_5%

AR24
AR21
AU24
AV20

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

CFG16

R110 1
R64 1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GRAPHICS VID

[16] MCH_CLKSEL0
[16] MCH_CLKSEL1
[16] MCH_CLKSEL2

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

DMI

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

RSVD22
RSVD23
RSVD24
RSVD25

CLK

BG23
BF23
BH18
BF18

RSVD20

AP24
AT21
AV24
AU20

1K_0402_1%

AY21

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

511_0402_1%

RSVD15
RSVD16
RSVD17

RSVD

B31
B2
M1

All RSVD balls on GMCH should be left No

Connect.

DDR CLK/ CONTROL/

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

COMPENSATION

U21B
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

DDR3

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

HDA_SDIN2 [20]

2
R355
2
R77
2
R78
2
R66
2
R67
2
R69
2
R71
2
R68

@
@
@
@
@
@
@
@

1
2.21K_0402_1%
1
4.02K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
1
2.21K_0402_1%
A

MCH_CFG_19

2 @
R86

MCH_CFG_20

2 @
R87

Notice: Please check HDA power rail to select HDA controller.

1
4.02K_0402_1%
1
4.02K_0402_1%

+3VS

GM45@

2008/11/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

Cantiga GMCH(2/7)-DMI/DDR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

of

45

[15] DDR_B_D[0..63]
U21E
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

BB20
BD20
AY20

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_RAS# [14]
DDR_A_CAS# [14]
DDR_A_WE# [14]

DDR_A_DM[0..7]

MEMORY

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

CANTIGA B3_FCBGA1329

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

DDR_A_MA[0..14]

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

[14]
[14]
[14]

[14]

[14]

[14]

[14]

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SA_RAS#
SA_CAS#
SA_WE#

BD21
BG18
AT25

MEMORY

SA_BS_0
SA_BS_1
SA_BS_2

SYSTEM

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SYSTEM

U21D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

DDR

[14] DDR_A_D[0..63]

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

CANTIGA B3_FCBGA1329

BC16
BB17
BB33

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

AU17
BG16
BF14

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

[15]
[15]
[15]

DDR_B_RAS# [15]
DDR_B_CAS# [15]
DDR_B_WE# [15]

DDR_B_DM[0..7]

[15]

DDR_B_DQS[0..7]

[15]

DDR_B_DQS#[0..7]

DDR_B_MA[0..14]

[15]

[15]

GM45@

GM45@

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/11/10

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Cantiga GMCH(3/7)-DDR
Size
C
Date:

Document Number

Rev
0.1

KALG1
Sheet

Tuesday, March 24, 2009

1

of

45

U21C

LVDS_IBG
2.37K_0402_1%
2
1
R91
0_0402_5%

C44
B43
E37
E38

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

GMCH_TXCLKGMCH_TXCLK+

C41
C40
B37
A37

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

H47
E46
G40
A40

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

H48
D45
F40
B40

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

A41
H38
G37
J37

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

B42
G38
F37
K37

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

[17] GMCH_LCD_CLK
[17] GMCH_LCD_DATA
[17] GMCH_ENVDD

R92
100K_0402_5%

R357

[17] GMCH_TXCLK[17] GMCH_TXCLK+

[17] GMCH_TXOUT0[17] GMCH_TXOUT1[17] GMCH_TXOUT2[17] GMCH_TXOUT0+

[17] GMCH_TXOUT1+
[17] GMCH_TXOUT2+

LVDS

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LCTLA_CLK
LCTLB_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA

GRAPHICS

ENBKL

Change to 0Ohm when use PM chip

GMCH_TV_COMPS
GMCH_TV_LUMA

R75
R76
75_0402_1% 75_0402_1%

R74
75_0402_1%

Change to 0Ohm when use PM chip

[18] GMCH_CRT_B
R80

[18] GMCH_CRT_G

R82

H24

TV_RTN

C31
E32

TV_DCONSEL_0
TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

150_0402_1%

J28

CRT_RED

150_0402_1%

G29

CRT_IRTN

H32
J32
J29
E29

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF

L29

CRT_VSYNC

150_0402_1%

GMCH_CRT_CLK
GMCH_CRT_DATA

[18] GMCH_CRT_CLK
[18] GMCH_CRT_DATA
[18] GMCH_CRT_HSYNC

CRT_IREF

[18] GMCH_CRT_VSYNC

PEG_COMP

PEG_COMPI
PEG_COMPO

T37
T36

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3

10mils

R96

49.9_0402_1%

+1.05VS

TMDS_B_HPD#

TMDS_B_HPD# [24]

1
C176
1
C401

2
0.1U_0402_16V7K
1
C403
2
0.1U_0402_16V7K
1
C177

HDMI_PCIE_MTX_C_GRX_N0
HDMI_PCIE_MTX_C_GRX_N1
HDMI_PCIE_MTX_C_GRX_N2
HDMI_PCIE_MTX_C_GRX_N3

2
0.1U_0402_16V7K
2
0.1U_0402_16V7K

HDMI_PCIE_MTX_C_GRX_N[0..3]

CLOSE SPLIT POINT

1
C175
1
C402

2
0.1U_0402_16V7K
1
C406
2
0.1U_0402_16V7K
1
C178

2
2

HDMI_PCIE_MTX_C_GRX_P[0..3]

0.1U_0402_16V7K

HDMI_PCIE_MTX_C_GRX_N[0..3]

[24]

HDMI_PCIE_MTX_C_GRX_P[0..3]

[24]

HDMI_PCIE_MTX_C_GRX_P0
HDMI_PCIE_MTX_C_GRX_P1
HDMI_PCIE_MTX_C_GRX_P2
HDMI_PCIE_MTX_C_GRX_P3

0.1U_0402_16V7K
B

+3VS

VGA

R73

[18] GMCH_CRT_R

TVA_DAC
TVB_DAC
TVC_DAC

TV

GMCH_TV_CRMA

F25
H25
K25

PCI-EXPRESS

[30]

L32
G32
M32
M33
K33
J33
M29

[17] DPST_PW M

ENBKL

2 2.2K_0402_5%

GMCH_LCD_CLK

R81

2 2.2K_0402_5%

GMCH_LCD_DATA

R95

2 10K_0402_5%

LCTLB_DATA

R85

2 10K_0402_5%

LCTLA_CLK

R440 1

2 2.2K_0402_5%

GMCH_CRT_CLK

R447 1

2 2.2K_0402_5%

GMCH_CRT_DATA

R79
1K_0402_1%

CANTIGA B3_FCBGA1329

GM45@

R83

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/11/10

Issued Date

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Cantiga GMCH(4/7)-VGA/LVDS/TV
Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

10

of

45

U21F

+1.05VS

+1.5V

VCC_AXG_SENSE
VSS_AXG_SENSE

U21G
C151

C132

C135

1
C134

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C106

10U_0805_10V4Z

10U_0805_10V4Z

C133

1U_0402_6.3V6K

0.47U_0603_16V4Z

C147

1
+
2

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

POWER

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33

330U_D2_2.5VY_R9M

PVT

+1.05VS

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

Place close to the GMCH

NCTF

1
C155

VCC

1
C156

DDR3
0.1U_0402_16V4Z

C157

10U_0805_10V4Z

10U_0805_10V4Z

C168

PVT

VCC_SM: 2600mA
(330UF*1, 22UF*2, 0.1UF*1)
330U_D2_2.5VY_R9M

+1.5V

Place on the edge

Reference PILLAR_ROCK CRB Rev1.0

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
1
C115

GM45@

1
C165
@ 2

0.1U_0402_16V7K

1
C137
@ 2

0.1U_0402_16V7K

1
C125
@ 2

0.1U_0402_16V7K

1
C104
@ 2

0.1U_0402_16V7K

1
C114
@ 2

0.1U_0402_16V7K

VCC_SM_BA36
VCC_SM_BB24
VCC_SM_BD16
VCC_SM_AW16
VCC_SM_AT13

CANTIGA B3_FCBGA1329
C113

C105

C136

C166

C167

C170

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

GM45@

Compal Electronics, Inc.

Compal Secret Data

2008/11/10

Issued Date

VCC_AXG: 6326.84mA
(330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

Security Classification

[email protected]
GRATIS - FOR FREE

C163

0.1U_0402_16V4Z

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

10U_0805_10V4Z

220U_D2_4VY_R15M

C152

Cavity Capacitors

2
CANTIGA B3_FCBGA1329

C162

1U_0402_6.3V6K

AJ14
AH14

1U_0402_6.3V6K

VCC_AXG_SENSE
VSS_AXG_SENSE

0.47U_0603_16V4Z

PAD
PAD

+ C93

C123

GFX

@
T4
@
T3

+1.05VS

+1.05VS

0.22U_0402_6.3V6K

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

Cavity Capacitors

VCC

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

VCC: 1930.4mA (GMCH), 1210.34mA (MCH)

(270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)

+1.05VS
PVT

0.22U_0402_6.3V6K

+1.05VS

Place close to the GMCH

0.1U_0402_16V7K

VCC_SM_AT13

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC

VCC_SM_AW16

BA36
BB24
BD16
BB21
AW16
AW13
AT13

POWER

VCC_SM_BA36
VCC_SM_BB24
VCC_SM_BD16

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

0.1U_0402_16V7K

GFX NCTF

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC CORE

SM

Pins BA36, BB24, BD16,

BB21, AW16, AW13, AT13
could be left NC for DDR2
board.

VCC

Reference PILLAR_ROCK CRB Rev1.0

2600mA
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC SM LF

AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

2008/11/24

Deciphered Date

Title

Cantiga GMCH(5/7)-VCC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

11

of

45

+1.05VS_HPLL
+1.05VS_DPLLA

C418

PVT
C424

0.1U_0402_16V4Z

C417

AD1

VCCA_HPLL

+1.05VS_MPLL

AE1

VCCA_MPLL

1000P_0402_50V7K
2

VCCA_LVDS: 13.2mA
(1000PF*1)

J48

+1.05VS

220U_D2_4VY_R15M
2

2
1
C399
10U_0805_6.3V6M

Close to Ball A26, B27

+1.05VS_A_SM

1
2
R63
0_0805_5%

C124

+
PVT C94
@
220U_D2_4VY_R15M
2

VCCA_DAC_BG: 2.6833333mA
(0.1UF*1, 0.01UF*1)
1

+3VS

C116

+1.05VS_A_SM_CK
+3VS_DACBG

2
C416

C423

C138
4.7U_0805_10V4Z
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V6K

1
2
R99
0_0603_5%

+1.05VS

L10
MBK1608221YZF_0603 1
C415

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_0805_6.3V6M
2
2
2
0.01U_0402_16V7K

VCCA_SM_CK: 24mA
(22UF*1, 2.2UF*1, 0.1UF*1)

1
1
C148
C153
C154
@
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
2
2
2
22U_0805_6.3V6M

NO_STUFF

Close to Ball A25

+3VS

VCCD_HDA: 50mA
(0.1UF*1)
+1.5VS_HDA

L11 1
2
MBK1608221YZF_0603
C130

C131

B24
A24

+3VS_TVDAC

+3VS_TVDAC

180Ohm@100MHz

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

VCCA_TV_DAC: 40mA (0.1UF*1,

0.01UF*1 for each DAC)

+1.5VS

1
2
R359
0_0402_5%

0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K

C420

A32

0.1U_0402_16V4Z
2

M25

+1.5VS_TVDAC

L28

+1.5VS_QDAC

AF1

+1.05VS_HPLL
+1.05VS_PEGPLL

+1.5VS

1
2
L13
MBK1608221YZF_0603

C146

C149

M38
L37

VCCD_PEG_PLL: 50mA
(0.1UF*1)

Also power for internal

Thermal Sensor

0.1U_0402_16V4Z
2
2
0.022U_0402_16V7K

+1.8V

+1.5VS

1
2
R90
100_0603_1%

180Ohm@100MHz

C150

C160

VCCA_PEG_PLL

480mA

1
C101
2

VCC_AXF: 321.35mA
(10UF*1, 1UF*1)

1
C422
@
10U_0805_6.3V6M
2

1
2
R354
0_0603_5%

1
C414

+1.05VS

1U_0402_6.3V6K
2

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

118.8mA
VCC_TX_LVDS

105.3mA
VCC_HV_1
VCC_HV_2
VCC_HV_3

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

50mA

456mA

VCC_HDA

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

58.696mA
VCCD_TVDAC

48.363mA

VCCD_QDAC

157.2mA
VCCD_HPLL
VCCD_PEG_PLL

1uH 30%

B22
B21
A21
1

BF21
BH20
BG20
BF20

60.31mA

1
2
L12
MBK1608121YZF_0603

2
10U_0805_6.3V6M

+1.8V_TX_LVDS

0.1uH 20%
1
1

C407

C411

2
R358
0_0603_5%

+1.8V

1000P_0402_50V7K
2
2 10U_0805_10V4Z

VCC_HV: 105.3mA
+3VS
1

C419
0.1U_0402_16V4Z

+1.05VS_PEG: 1782mA +1.05VS_PEG

(220UF*1, 22UF*1, 4.7UF*1)

V48
U48
V47
U47
U46

1
1

PVT
+ C184

C169

10U_0805_10V4Z
2

1
2
R112
0_0805_5%

+1.05VS
B

220U_D2_4VY_R15M
+1.05VS

AH48
AF48
AH47
AG47

+1.05VS_DMI

VCC_DMI: 456mA
(0.1UF*1)

2
VTTLF1
VTTLF2
VTTLF3

1 R72
2
1
1_0402_1% C140

0.1U_0402_16V4Z

K47

C35
B35
A35

+1.5V

C139

+1.8V_TX_LVDS: 118.8mA
(22UF*1, 1000PF*1)

1782mA

87.79mA
VCCA_TV_DAC_1
VCCA_TV_DAC_2

VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)

1
2
R345
0_0805_5%
C392
0.1U_0402_16V4Z

VTTLF_CAP1
A8
VTTLF_CAP2
L1
AB2 VTTLF_CAP3
C102

GM45@

C404

C412

0.47U_0603_16V4Z
0.47U_0603_16V4Z
2
2
2
0.47U_0603_16V4Z

C161

1U_0402_6.3V6K
2
+1.05VS

VCCD_LVDS: 60.311111mA
(1UF*1)

0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K

+1.05VS_AXF

2008/11/10

Issued Date

+3VS

10_0603_5%
CH751H-40PT_SOD323-2

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R65

D17

1
C122

0.47U_0603_16V4Z

2.2U_0603_6.3V6K

1
C397

4.7U_0805_10V4Z

4.7U_0805_10V4Z

24mA

VCCD_LVDS_1
VCCD_LVDS_2

1
C400

+1.5V_SM_CK

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

50mA

+
2

POWER

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

PVT
C396

220U_D2_4VY_R15M

CRT
VTT

50mA

CANTIGA B3_FCBGA1329

10U_0805_6.3V6M
2

VCCD_QDAC: 48.363mA +1.5VS_QDAC

(0.1UF*1, 0.01UF*1)

VCCA_PEG_BG

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

+1.8V_LVDS

1
2
R348
0_0603_5%
C398

AA47

+1.5VS_TVDAC

VSSA_LVDS

Close to A32

VCCD_HPLL: 157.2mA (0.1UF*1)

VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)

13.2mA
VCCA_LVDS

VCCA_PEG_PLL: 50mA
(0.1UF*1)

VCCA_SM:
(22UF*2, 4.7UF*1, 1UF*1)

+1.05VS

AD48

AA48

+1.05VS_PEGPLL
1
C394

L30 1
2
MBK1608121YZF_0603
1
2
R347
1_0402_1%

139.2mA

0.414mA

VCCA_PEG_BG: 0.414mA
(0.1UF*1)

C395

0.1U_0402_16V4Z
2

24mA

+1.05VS_HPLL
1

J47
1

0.01U_0402_16V7K
2

VCCA_DPLLB

VCCA_DPLLA

AXF

+3VS_CRTDAC

+VCCA_PEG_BG

R346
0_0402_5%
1
2

+1.5VS

L32 1
2
MBK1608301YZF_0603
1

L48

+1.8V_TX_LVDS
C410

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

F47

+1.05VS_DPLLB

HV

C389
22U_0805_6.3V6M
2

64.8mA

+1.05VS_DPLLA

PEG

C408
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z

VSSA_DAC_BG

DMI

C405

VCCA_DAC_BG

B25

VTTLF

A25

PLL

2
0.1U_0402_16V4Z

+3VS_DACBG

2.69mA

A PEG A LVDS

1
L31
0_1210_5%

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

SM CK

R344
0.5_0603_1%

VTT: 852mA
(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)

+1.05VS

852mA

73mA

A CK

C103

B27
A26

+3VS_CRTDAC

+1.05VS_DPLLB

L28 1
2
MBK1608121YZF_0603

+3VS

U21H

A SM

120Ohm@100MHz

VCCA_MPLL: 139.2mA
(22UF*1, 0.1UF*1)

C174

220U_D2_4VY_R15M 2
VCCA_DPLLA
2
0.1U_0402_16V4Z
VCCA_DPLLB: 64.8mA
(220UF*1, 0.1UF*1)

+1.05VS_MPLL
D

PVT
C183

TV

4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z

HDA

C393

1
L14
0_1210_5%

+1.05VS

D TV/CRT

(4.7UF*1, 0.1UF*1)

LVDS

L29 1
2
MBK1608121YZF_0603
1
C391
VCCA_HPLL: 24mA

+1.05VS

Deciphered Date

2008/11/24

Title

Crestline GMCH (6/7)-VCC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

12

of

45

VSS

CANTIGA B3_FCBGA1329

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

BA16

VSS_235

AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

VSS

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

VSS_351
VSS_352
VSS_353
VSS_354
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS NCTF

U21J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

VSS SCB

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

NC

U21I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

GM45@

CANTIGA B3_FCBGA1329

U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

GM45@

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

Cantiga GMCH(1/7)-GTL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

13

of

45

+1.5V
+V_DDR3_DIMM_REF

[9] DDR_A_DQS#[0..7]

JDIMM1

[9] DDR_A_D[0..63]
+1.5V +V_DDR3_DIMM_REF

[9] DDR_A_DM[0..7]

DDR_A_D0
DDR_A_D1

[9] DDR_A_DQS[0..7]

DDR_A_DM0

R123

[9] DDR_A_MA[0..14]

1K_0402_1%
2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

R122
DDR_A_DQS#1
DDR_A_DQS1

1K_0402_1%
2

C188

2.2U_0805_16V4Z

C181
0.1U_0402_16V4Z

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

Layout Note:
Place near JP4

DDR_CKE0_DIMMA

[8] DDR_CKE0_DIMMA

Layout Note: Place these 4 Caps near Command

and Control signals of DIMMA

DDR_A_BS2

[9] DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

C108

C126

C118

C107

330U_D2_2.5VY_R9M

DDR_A_MA3
DDR_A_MA1

1
+

C95

C97

C117

0.1U_0402_16V4Z

C110

0.1U_0402_16V4Z

C127

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C142

DDR_A_MA8
DDR_A_MA5

10U_0603_6.3V6M

10U_0603_6.3V6M

C141

+1.5V

M_CLK_DDR0
M_CLK_DDR#0

[8] M_CLK_DDR0
[8] M_CLK_DDR#0

2 PVT

DDR_A_MA10
DDR_A_BS0

[9] DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

[9] DDR_A_WE#
[9] DDR_A_CAS#

DDR_A_MA13
DDR_CS1_DIMMA#

[8] DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

Layout Note:
Place near JP4.203 & JP4.204

DDR_A_DM5
1

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

C48

C46

C47

C45

C49

10U_0805_6.3V6M

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

DDR_A_D40
DDR_A_D41

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1 R39
2
10K_0402_5%

Security Classification

R37
10K_0402_5%
2
1

0.1U_0402_16V4Z

C44

C69
2.2U_0603_6.3V4Z

+3VS

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
D

DDR_A_D12
DDR_A_D13
DDR_A_DM1
SM_DRAMRST#

SM_DRAMRST# [8,15]

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA [8]
C

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1

M_CLK_DDR1 [8]
M_CLK_DDR#1 [8]
DDR_A_BS1 [9]
DDR_A_RAS# [9]
DDR_CS0_DIMMA# [8]
M_ODT0 [8]
M_ODT1

DDR_VREF_CA_DIMMA
DDR_A_D36
DDR_A_D37

R59

+V_DDR3_DIMM_REF

[8]

2
0_0402_5%

DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5

1
B

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0
CLK_SMBDATA
CLK_SMBCLK

PM_EXTTS#0 [8]
CLK_SMBDATA [15,16]
CLK_SMBCLK [15,16]

+0.75VS

+0.75VS

Compal Secret Data

2007/09/29

Issued Date

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C98

DDR_A_D34
DDR_A_D35

+0.75VS

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

0.1U_0402_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2.2U_0603_6.3V4Z
C109

DDR_A_DQS#4
DDR_A_DQS4

+1.5V

2008/11/24

Deciphered Date

DDR3 SO-DIMM A
REVERSE
Compal Electronics, Inc.

Title

DDRIII-SODIMM SLOT1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

14

of

45

[9] DDR_B_DQS#[0..7]

+1.5V

[9] DDR_B_D[0..63]

+1.5V

+V_DDR3_DIMM_REF

[9] DDR_B_DM[0..7]

JDIMM2

[9] DDR_B_DQS[0..7]
DDR_B_D0
DDR_B_D1

[9] DDR_B_MA[0..14]

DDR_B_DM0
1

DDR_B_D2
DDR_B_D3

C190

C191

0.1U_0402_16V4Z

2.2U_0805_16V4Z

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2

Layout Note:
Place near JP5

DDR_B_D18
DDR_B_D19

Layout Note: Place these 4 Caps near Command

and Control signals of DIMMB

DDR_B_D24
DDR_B_D25

+1.5V

DDR_B_DM3

C112

C129

C128

C143

C120

1
+

2 PVT

DDR_CKE2_DIMMB

[8] DDR_CKE2_DIMMB

DDR_B_BS2

[9] DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

Layout Note:
Place near JP5.203 & JP5.204

M_CLK_DDR2
M_CLK_DDR#2

[8] M_CLK_DDR2
[8] M_CLK_DDR#2
+0.75VS

DDR_B_MA10
DDR_B_BS0

[9] DDR_B_BS0

C55

DDR_B_WE#
DDR_B_CAS#

[9] DDR_B_WE#
[9] DDR_B_CAS#

10U_0805_6.3V6M

C51

1U_0603_10V4Z
C52

1U_0603_10V4Z
C53

1U_0603_10V4Z
C54

1U_0603_10V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_B_MA13
DDR_CS3_DIMMB#

[8] DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13
DDR_B_DM1
SM_DRAMRST#

SM_DRAMRST# [8,14]

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7

C70

C50

2
2

0.1U_0402_16V4Z

+3VS
A

2.2U_0603_6.3V4Z

DDR_B_D58
DDR_B_D59
1 R40
2
10K_0402_5%
1

2
R38
10K_0402_5%

205

G2

206

G1

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB [8]

DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 [8]
M_CLK_DDR#3 [8]

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 [9]
DDR_B_RAS# [9]

DDR_CS2_DIMMB#
M_ODT2

DDR_CS2_DIMMB# [8]
M_ODT2 [8]

M_ODT3

M_ODT3

DDR_VREF_CA_DIMMB

R60
1

+V_DDR3_DIMM_REF

[8]

2 0_0402_5%

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#1
CLK_SMBDATA
CLK_SMBCLK

PM_EXTTS#1 [8]
CLK_SMBDATA [14,16]
CLK_SMBCLK [14,16]

+0.75VS

2008/11/24

Deciphered Date

Title

Date:

DDR_B_D52
DDR_B_D53

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

DDR_B_D46
DDR_B_D47

Compal Secret Data

2007/09/29

Issued Date

DDR_B_DQS#5
DDR_B_DQS5

+0.75VS

Security Classification

C100

DDR_B_D40
DDR_B_D41

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

C96

DDR_B_D34
DDR_B_D35

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

0.1U_0402_16V4Z

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

2.2U_0603_6.3V4Z

DDR_B_DQS#4
DDR_B_DQS4

[email protected]
GRATIS - FOR FREE

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C91

C99

330U_D2_2.5VY_R9M

C119

0.1U_0402_16V4Z

C121

0.1U_0402_16V4Z

C144

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0805_6.3V6M

10U_0603_6.3V6M

C111

DDR_B_D26
DDR_B_D27
1

DDR3 SO-DIMM B
REVERSE
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
1

15

of

45

266

100

33.3

200

100

33.3

166

100

33.3

Control

C285

C272

C273

C288

C282

C286

U12
1

+CLK_VDD

Free-Run

ICS9LPRS387, PN:SA000020H10
SLG8SP556V, PN:SA000020K00

CLK_SMBDATA

SCLK

10

CLK_SMBCLK
CLK_CPU_BCLK

SDATA

VDDREF

CLK_SMBDATA [14,15]
CLK_SMBCLK [14,15]

PCIEX10

PCIEX0

19

CR#_6(MCH)

PCIEX6

PCIEX1

72

VDDCPU

CPUT0_LPR_F

71

CR#_4(NEW CARD)

PCIEX4

12

VDDPCI

CPUC0_LPR_F

70

CLK_CPU_BCLK#

CR#_9(MINI CARDII)

PCIEX9

27

VDDPLL3

SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable]

55

VDDSRC

VDD48

52

+CLK_VDDSRC

38

CLK_PCI2
2
10K_0402_5%

62

CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed)

CPUT1_LPR_F

68

CLK_MCH_BCLK

67

CLK_MCH_BCLK#

SRCT0_LPR/DOTT_96_LPR

24

CLK_DREF_96M

SRCC0_LPR/DOTC_96_LPR

25

CLK_DREF_96M#
CLK_DREF_SSC

mount to Enable ITP_CLK

2
10K_0402_5%

1
R280

2
10K_0402_5%

+3VS
CLK_PCI5

R268 @
10K_0402_5%

CLK_PCI5=0, Pin63,64 is SRC_CLK

CLK_PCI5=1, Pin63,64 is ITP_CLK
CLK_PCI4
2
10K_0402_5%

2
10K_0402_5%

[21] H_STP_CPU#
[21] H_STP_PCI#

CK505_PW RGD

CK_PW RGD

2
G
Q28
@
2N7002_SOT23

CLK_PCI_LPC

[30] CLK_PCI_LPC

R276 2

C315 1

For EMI

C311
1

1
R247
0_0402_5%

0_0402_5% 2
0_0402_5% 2

1 R239
1 R240

27P_0402_50V8J
2

R245 @
56_0402_5%
R246
1K_0402_5%
1
2

C310
27P_0402_50V8J
1
2

[21] CLK_ICH_48M
CPU_BSEL0 [5]
[25] CLK_SD_48M

1
R241
1
R242
R273 2

CLK_SD_48M
CLK_ICH_14M

3
S

2
G
MCH_CLKSEL1 [8]

1
R292
0_0402_5%

35

CLK_PCIE_ICH

36

CLK_PCIE_ICH#
CLK_PCIE_CARD

SRCT4_LPR

40

CLK_PCIE_CARD#

CLK_PCI3

15

PCI3

57

16

SRCT6_LPR

CLK_MCH_3GPLL

CLK_PCI4

PCI4/27_SELECT
SRCC6_LPR

56

CLK_MCH_3GPLL#

17

CK505_PW RGD1

SRCT7_LPR

61

SRCC7_LPR

60

CK_PWRGD/PD#

X1

CPUT2_ITP_LPR/SRCT8_LPR

64

X2

CPUC2_ITP_LPR/SRCC8_LPR

63

11

NC

SRCT9_LPR

44

CLK_PCIE_MINI2

SRCC9_LPR

45

CLK_PCIE_MINI2#

CLKSEL0

20

USB_48MHz/FSLA

CLKSEL1

FSLB/TEST_MODE

CLKSEL2

FSLC/TEST_SEL/REF0

PAD
T27 @

REF1

69

GNDCPU

+3VS

50
51

SRCT11_LPR

48

CLK_PCIE_LAN

SRCC11_LPR

47

CLK_PCIE_LAN#

GNDREF

CR#3

37

GNDPCI

CR#4

41

22

GND48

CR#6

58

30

GND

CR7#

65

GND

CR#9

43

GNDSRC

CR10#

49

GNDSRC

CR#11

46

CR#A

21

59

CLK_SMBCLK

SRCT10_LPR
SRCC10_LPR

18

34

42
73

[28]

CLK_PCIE_CARD#

PVT

[28]

CLK_MCH_3GPLL [8]
CLK_MCH_3GPLL# [8]

PCI_F5/ITP_EN

26

[21]

CLK_PCIE_CARD

+3VS

[21]

CLK_PCIE_ICH#

SRCC4_LPR

CLK_PCI5

[8]

CLK_PCIE_SATA# [20]
CLK_PCIE_ICH

PCI2/TME

CLK_SMBDATA

R282
4.7K_0402_5%
1
2

SRCT3_LPR
SRCC3_LPR

[8]

CLK_DREF_SSC#

CLK_PCIE_SATA [20]

PCI1

Q23
2N7002_SOT23

CLK_PCIE_SATA#

14

[21,28] ICH_SMBCLK

R293 @
1K_0402_5%
R278
1K_0402_5%
1
2

33

CLK_PCI2

+3VS

2
1
R291 @
0_0402_5%

R274
10K_0402_5%
CLKSEL2 1
2

32

SRCC2_LPR/SATAC_LPR

39

Q29
2N7002_SOT23

CPU_BSEL1 [5]

+1.05VS
4

SRCT2_LPR/SATAT_LPR

CLK_PCIE_SATA

CLK_XTALOUT

2
22_0402_5%
2
22_0402_5%
1 33_0402_5%

R294
4.7K_0402_5%
1
2

2
G

1
R270
0_0402_5%

VDD96_IO

13

+3VS

R271 @
1K_0402_5%

1
2

23

CLK_DREF_SSC

@ T26
PAD

Y2
14.31818MHz_20P_FSX8L14.318181M20FDB

CLK_ICH_48M

[21,28] ICH_SMBDATA

1
R272 @
0_0402_5%

CLK_DREF_SSC#

CLK_XTALIN

+1.05VS

R269
1K_0402_5%
1
2

29

MCH_CLKSEL0 [8]

[21] CLK_ICH_14M

CLKSEL1

27MHz_SS/SRCC1_LPR/SE2

PCI_STOP#

1 33_0402_5%

2
1

1
2
R244 @
1K_0402_5%

R279 2

[21] CK_PW RGD

[8,21,43] VGATE

+1.05VS

R243
2.2K_0402_5%
CLKSEL0 1
2

CLK_PCI_ICH

[19] CLK_PCI_ICH

10P_0402_50V8J CLK_PCI_ICH

27MHz_NonSS/SRCT1_LPR/SE1

VDDCPU_IO

54

10P_0402_50V8J CLK_PCI_LPC

VDDPLL3_IO

H_STP_PCI#

C314 1

CLK_DREF_96M# [8]

66

CPU_STOP#

1 33_0402_5%

CLK_DREF_96M [8]

28

53

CLK_MCH_BCLK# [7]

VDDSRC_IO

H_STP_CPU#

CLK_ENABLE# [43]

CLK_CPU_BCLK# [4]
CLK_MCH_BCLK [7]

31

CLK_PCI4=0, Pin28, 29 is SRC_CLK

Pin24, 25 is DOT96_CLK
@
1
R238

VDDSRC_IO

1
R277

VDDSRC_IO

@
1
R281

CLK_CPU_BCLK [4]

CPUC1_LPR_F

+3VS

Clock Generator

L21
2
1
KC FBM-L11-201209-221LMAT_0805
1
1
1
1
1
1
1
1
C271
C300
C281
C312
C313
C301
C287
C266
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

CR#_10(WLAN)

1
R275

+CLK_VDD
+3VS

Table : ICS9LPRS387
CLK_REQ#

+CLK_VDDSRC
L22
2
1
KC FBM-L11-201209-221LMAT_0805
1
1
C274
C267
10U_0805_10V4Z
2
2

+1.05VS

0.1U_0402_16V4Z

PCI
MHz

0.1U_0402_16V4Z

SRC
MHz

0.1U_0402_16V4Z

CPU
MHz

0.1U_0402_16V4Z

FSLA

0.1U_0402_16V4Z

FSLB

CLKSEL2 CLKSEL1 CLKSEL0

0.1U_0402_16V4Z

FSLC

10U_0805_10V4Z

GNDSRC
GND_THERMAL_PAD

CLK_PCIE_MINI2

[28]

CLK_PCIE_MINI2#

[28]

CLK_PCIE_LAN [26]
CLK_PCIE_LAN# [26]

1
R482

2
10K_0402_5%

EXP_CLKREQ# [28]
MCH_CLKREQ# [8]

(Pull High to +3VS at GMCH side)

1
R195

1
R32

2
10K_0402_5%

2
10K_0402_5%

PVT

+3VS

+3VS
MINI2_CLKREQ#

[28]

+3VS
LAN_CLKREQ# [26]
4

SATA_CLKREQ# [21]

(Pull High to +3VS at ICH side)

ICS9LPRS387BKLFT_MLF72_10x10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

MCH_CLKSEL2 [8]

2008/11/10

Deciphered Date

CPU_BSEL2 [5]

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

Clock Generator (CK505)

Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

G

Sheet

16

of
H

45

LCD POWER CIRCUIT

+LCDVDD

+3VS

+3V

3 2

R22
100K_0402_5%
2

2
3
Q1A

[10] GMCH_ENVDD

2N7002DW-T/R7_SOT363-6

4.7U_0805_10V4Z

+LCDVDD

W=60mils
1

C14

4.7U_0805_10V4Z
2

C13
0.1U_0402_16V4Z

R12
100K_0402_5%

C18

Q2
AO3413_SOT23-3

C12

1
1K_0402_5%

2
R21

0.047U_0402_16V7K

2N7002DW-T/R7_SOT363-6

Q1B

W=60mils
R11
300_0603_5%

+3VS

+INVPWR_B+

B+

DAC_BRIG
R10

W=40mils

[30]

BKOFF#

BKOFF#

L1
2
1
KC FBM-L11-201209-221LMAT_0805
C5

DISPOFF#

220P_0402_50V7K

C8
DISPOFF#

D6

L2
2
1
KC FBM-L11-201209-221LMAT_0805

1
C7

INVTPWM
4.7K_0402_5%

220P_0402_50V7K

C9

220P_0402_50V7K

CH751H-40PT_SOD323-2

C6

680P_0402_50V7K 68P_0402_50V8J
2
2

5
A

DPST_PWM [10]

U1
INVTPWM

NC

+3VS

NC7SZ14P5X_NL_SC70-5

2
G

LCD/PANEL BD. Conn.

+INVPWR_B+

[10] GMCH_LCD_CLK
[10] GMCH_LCD_DATA

R13
[21]
[21]

USB20_N3
USB20_P3

R14

41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

+3VS

DAC_BRIG
INVTPWM
DISPOFF#

DAC_BRIG [30]

INVTPWM

1
D

JLVDS1
42
GND GND
40
40
39
38
38
37
36
36
35
GMCH_LCD_CLK
34
34
33
GMCH_LCD_DATA
32
32
31
30
30
29
28
28
27
26 26
25
24 24
23
22 22
21
20 20
19
18 18
17
16
16
15
14
14
13
12
12
11
10
10
9
8
8
7
0_0402_5%
6
6
5
4
1
2 USB20_CMOS_N3
4
3
2
1
2 USB20_CMOS_P3
2
1
0_0402_5%
+3VS

R20

@
3
S

10K_0402_5%
Q3
2N7002_SOT23

+LCDVDD

For GMCH DPST

W=60mils
GMCH_TXOUT0GMCH_TXOUT0+
GMCH_TXOUT1GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TXOUT2GMCH_TXCLKGMCH_TXCLK+

GMCH_TXOUT0- [10]
GMCH_TXOUT0+ [10]
GMCH_TXOUT1- [10]
GMCH_TXOUT1+ [10]

+3VS

GMCH_TXOUT2+ [10]
GMCH_TXOUT2- [10]
GMCH_TXCLK- [10]
GMCH_TXCLK+ [10]

+LCDVDD

C15
0.1U_0402_16V4Z

C11
10U_0805_10V4Z

C10
0.1U_0402_16V4Z

+3VS

ACES_88242-4001
A

CMOS Camera

CONN@

2008/11/24

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/28

Deciphered Date

Title

LVDS & Camera Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

17

of

45

CRT Connector

PVT

D14

D13

PSOT24C-LF-T7_SOT23-3

W=40mils

D11

+5VS

+R_CRT_VCC

+CRT_VCC

D10

DAN217_SC59 DAN217_SC59 DAN217_SC59

2

F1
1

2
1.1A_6VDC_FUSE
1

C56
0.1U_0402_16V4Z
2

RB491D_SC59-3

W=40mils

+3VS
PVT
CRT_R_2

0_0805_5%
2

L6 FCM2012C-800_0805
CRT_G_1
1
2

CRT_G_2

CRT_B_2
1

L42 1
2
MBK1608301YZF_0603
L41 1
2
MBK1608301YZF_0603

+CRT_VCC
2
R446

R41

U26
Y

CRT_HSYNC_1

SUYIN_070546FR015S263ZR
CONN@

C517

2
+CRT_VCC

U25
Y

CRT_VSYNC_1

5
P
2

OE#

GMCH_CRT_VSYNC

Place closed to chipset

2
0.1U_0402_16V4Z

+3VS

R464
4.7K_0402_5%
2
G

DSUB_12

2
G

Q39
2N7002_SOT23
DSUB_15

GMCH_CRT_DATA [10]

R465
4.7K_0402_5%

74AHCT1G125GW_SOT353-5

[10] GMCH_CRT_VSYNC

GND
GND

DSUB_15

3
3

16
17

1
100K_0402_5%

74AHCT1G125GW_SOT353-5
+CRT_VCC

1
C494

RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND

DSUB_12

C518
C519
10P_0402_50V8J
10P_0402_50V8J
2
2

1
10K_0402_5%

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_DET# [21]
CRT_VSYNC_2
1
1

C516

+CRT_VCC
2

CRT_HSYNC_2

C520

OE#

P
GMCH_CRT_HSYNC

C77
10P_0402_50V8J

[10] GMCH_CRT_HSYNC

2
0.1U_0402_16V4Z
5

1
C493

68P_0402_50V8J

68P_0402_50V8J

C78

100P_0402_50V8J

C86

C72

C80

FCM2012C-800_0805
1
2
10P_0402_50V8J

CRT_B_1

10P_0402_50V8J

10P_0402_50V8J

C87

150_0402_1%

R42
2

150_0402_1%

R45
2

1
R47
2

150_0402_1%

10P_0402_50V8J

GMCH_CRT_B

[10] GMCH_CRT_B
2

L3

C85

0_0805_5%
1
2
C79

R474

10P_0402_50V8J

22P_0402_50V8J

R473
GMCH_CRT_G

[10] GMCH_CRT_G

22P_0402_50V8J

[10] GMCH_CRT_R

JCRT1
L8 FCM2012C-800_0805
CRT_R_1
1
2

C71

GMCH_CRT_R

0_0805_5%
1
2

22P_0402_50V8J

R472

GMCH_CRT_CLK [10]

Q38
2N7002_SOT23

2008/11/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CRT Connector
Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
E

18

of

45

DMI for ESI-compatible operation

+3VS

PCI_GNT#1
RP3
PCI_TRDY#
PCI_FRAME#
PCI_REQ#1
PCI_REQ#2

8
7
6
5

U22B

8.2K_1206_8P4R_5%

D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

RP7

1
2
3
4

PCI_PLOCK#
PCI_IRDY#
PCI_PERR#
PCI_PIRQB#

8
7
6
5
8.2K_1206_8P4R_5%

+3VS
RP6

1
2
3
4

PCI_PIRQG#
PCI_REQ#0
PCI_PIRQH#
PCI_PIRQE#

8
7
6
5
8.2K_1206_8P4R_5%
RP2

1
2
3
4

PCI_PIRQF#
PCI_SERR#
PCI_PIRQA#
PCI_PIRQC#

8
7
6
5
8.2K_1206_8P4R_5%
RP4

PCI_DEVSEL#
PCI_REQ#3
PCI_STOP#
PCI_PIRQD#

8
7
6
5

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3

PAD

T32
@

PAD

T13
@

C/BE0#
C/BE1#
C/BE2#
C/BE3#

D8
B4
D6
A5

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PAD
PAD
PAD
PAD

T12
@
T35
@
T19
@
T18
@

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

C14
D4
R2

PLT_RST#
CLK_PCI_ICH

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PCI

@
PAD
T17
PCI_RST# [28]
PVT

PLT_RST# [8,26,30]
CLK_PCI_ICH [16]

Place closely pin B10

CLK_PCI_ICH

1
2
3
4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

F1
G4
B6
A7
F13
F12
E6
F6

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

8.2K_1206_8P4R_5%

J5
E1
J6
C4

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

H4
K6
F2
G2

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

R421
10_0402_5%
@
C476
10P_0402_50V8J
@

1
2
3
4

Low= DMI for ESI-compatible operation

High= Default* (Internal pull-up)

A16 Swap Override Strap

Low= A16 swap override Enable
High= Default*

PCI_GNT#3
R422

2 1K_0402_5% PCI_GNT#3

SPI

PCI

LPC*

R175

2 1K_0402_5% PCI_GNT#0

R382

2 1K_0402_5%

R228
100K_0402_5%
@

PLT_RST_BUF# [28]

R394
100K_0402_5%

Y
A

NC7SZ08P5X_NL_SC70-5

Boot BIOS Loaction

SPI_CS#1

PCI_GNT#0

U23
2 B

PLT_RST#

Boot BIOS Strap

+3VS

SPI_CS#1 [21]

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

ICH9M(1/4)-PCI
Size

Document Number

Rev
0.1

KALG1
Date:

Tuesday, March 24, 2009

Sheet
1

19

of

45

OUT

NC

IN

PVT
C437
12P_0402_50V8J
2
1

+RTCVCC

1
2
R376
20K_0402_5%

+RTCVCC

close to RAM door

R383
332K_0402_1%

+RTCVCC

close to RAM door

1
2
R337 @
10K_0603_5%

1
2
R336 @
10K_0603_5%

1
2
1U_0603_10V6K
C450

1
2
1U_0603_10V6K
C248

R399
10K_0402_5%
@

2
PROJECT_ID2

[32] HDA_BITCLK_MDC

R151

[32] HDA_SYNC_MDC

R365

R397
10K_0402_5%

R149

[32] HDA_RST_MDC#

R152

1
1
1

RTCRST#
SRTCRST#
INTRUDER#

ICH_INTVRMEN

B22
A22

INTVRMEN
LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14
G13
D14

LAN_RXD0
LAN_RXD1
LAN_RXD2

D13
D12
E13

LAN_TXD_0
LAN_TXD_1
LAN_TXD_2

B10

GPIO56

B28
B27

GLAN_COMPI
GLAN_COMPO

AF6
AH4

HDA_BIT_CLK
HDA_SYNC

[32] HDA_SDOUT_MDC

R150

HDA_SDOUT_ICH
33_0402_5%

R144

[36] SATA_LED#

10K_0402_5%

SATA for HDD

[23] SATA_DTX_C_IRX_N0
[23] SATA_DTX_C_IRX_P0

SATA_LED#

SATA for ODD

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDOUT

AG7
AE8

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

SATA_LED#

AG8

SATALED#

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

AJ16
AH16
AF17
AG17

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

[23] SATA_DTX_C_IRX_N1
[23] SATA_DTX_C_IRX_P1

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

K5
K4
L6
K2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4/LFRAME#

K3

LPC_FRAME#

LDRQ0#
LDRQ1#/GPIO23

J3
J1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

2
2

56_0402_5%
56_0402_5%

[30]
[30]
[30]
[30]

LPC_FRAME# [30]

R166 2

A20GATE
A20M#

N7
AJ27

EC_GA20
H_A20M#

DPRSTP#
DPSLP#

AJ25
AE23

DPRSTP# R375 1
DPSLP#
R158 1

1 10K_0402_5%

+3VS

EC_GA20 [30]
H_A20M# [4]

FERR#

AJ26

FERR#

CPUPWRGD

AD22

H_PW RGOOD

IGNNE#

AF25

H_IGNNE#

INIT#
INTR
RCIN#

AE22
AG25
L3

H_INIT#
H_INTR
EC_KBRST#

NMI
SMI#

AF23
AF24

H_NMI
H_SMI#

STPCLK#

AH27

H_STPCLK#

THRMTRIP#

AG26

THRMTRIP_ICH#

TP12

AG27

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AH11
AJ11
AG12
AF12

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AH9
AJ9
AE10
AF10

SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS

AH18
AJ18
AJ7
AH7

HDA_RST#

AG5

+3VS

AE7
AF4
AG4
AH3
AE5

[33] HDA_SDIN0
[32] HDA_SDIN1
[8] HDA_SDIN2

+1.05VS
H_DPRSTP#
R371
H_DPSLP#
R160

U22A

RTCX1
RTCX2

GLAN_COMP
2
24.9_0402_1%
HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%

Keep ME RTC Registers OPEN

A25
F20
C22

PROJECT_ID2
+1.5VS_PCIE_ICH

OPEN

C23
C24

+3V

Keep CMOS

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

ICH_INTVRMEN

High = Internal VR Enable

R336

Reset r1290 for power on then shut down issue

ICH_RTCX2

1
2
R180
20K_0402_5%

TPM Settings

0_0402_5% H_DPRSTP#
0_0402_5% H_DPSLP#

2
2

1
R374

H_DPRSTP# [5,8,43]
H_DPSLP# [5]

H_FERR#

2
56_0402_5%

H_FERR# [4]

H_PW RGOOD [5]

H_IGNNE#
H_INIT#
H_INTR

2
R370

1
56_0402_5%

2
R168

1
10K_0402_5%

+1.05VS

[4]
[4]
[4]

+3VS
EC_KBRST# [30]

H_NMI
H_SMI#

[4]
[4]
C

H_STPCLK# [4]
R373 1

2 54.9_0402_1%

H_THERMTRIP#

2
R372

H_THERMTRIP# [4,8]

1
56_0402_5%

+1.05VS

R372 need to place within 2" of ICH9M

R373 must be place within 2" of R372 w/o stub.

MAINPW ON [38,39]

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AH13
AJ13
AG14
AF14

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA_DTX_C_IRX_N5
SATA_DTX_C_IRX_P5
SATA_ITX_DRX_N5
SATA_ITX_DRX_P5

SATA_DTX_C_IRX_N5 [29]
SATA_DTX_C_IRX_P5 [29]

R369 @
330_0402_5%
1
2

+1.05VS

CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS

2
B
E

CLK_PCIE_SATA# [16]
CLK_PCIE_SATA [16]
R401 1

NC

Clear ME RTC Registers SHORT

LPC

SM_INTRUDER#

SHORT

CPU

32.768KHZ_12.5P_MC-306

R337

Clear CMOS

RTC

1M_0402_5%

CMOS Settings

LAN / GLAN

X2

R363
10M_0402_5%
2
1

R391

ICH_RTCX1

IHDA

PVT C438
12P_0402_50V8J
2
1

+RTCVCC

SATA

2 24.9_0402_1%

Q34
2SC2411K_SOT23
@

H_THERMTRIP#

10mils width less than 500mils

ICH9-M ES_FCBGA676
PROJECT_ID
ID1

ID2

KAL90

KAL90+

KALG1

KALG0

[33] HDA_BITCLK_AUDIO
[33] HDA_SYNC_AUDIO

HDA for AUDIO

[33] HDA_RST_AUDIO#
[33] HDA_SDOUT_AUDIO

[8] HDA_BITCLK_MCH
[8] HDA_SYNC_MCH

HDA for GMCH

[8] HDA_RST_MCH#
[8] HDA_SDOUT_MCH

1
R423
1
R424
1
R425
1
R409
1
R142
1
R140
1
R143
1
R141

HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%

close ICH9
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

SATA_ITX_DRX_N5
SATA_ITX_DRX_P5

+VCC_HDA_ICH

1
C202
1
C203

SATA_ITX_C_DRX_N0
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P0
2
0.01U_0402_16V7K

1
C201
1
C200

SATA_ITX_C_DRX_N1
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P1
2
0.01U_0402_16V7K

C199 KAL90_90+@
SATA_ITX_C_DRX_N5
1
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P5
1
2
C198
0.01U_0402_16V7K
KAL90_90+@
PVT

SATA_ITX_C_DRX_N0 [23]
+RTCBATT

SATA_ITX_C_DRX_P0 [23]

SATA_ITX_C_DRX_N1 [23]
SATA_ITX_C_DRX_P1 [23]

ID0

HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%

R304
1K_0402_5%
SATA_ITX_C_DRX_N5 [29]

1 1

SATA_ITX_C_DRX_P5 [29]

D30 BAS40-04_SOT23-3

+CHGRTC

HDA_SDOUT_ICH
ICH_TP3

Flash Descriptor Security Override Strap

[21]

XOR Chain Entrance Strap

R388
1K_0402_5%
@

ICH_TP3

HDA_SDOUT

GPIO33
Description

RSVD

Enter XOR Chain

Normal Operation

Set PCIE port config bit 1

4

Low= Descriptor Security override

High= Default* (Internal pull-up)

2008/11/10

Issued Date

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

C331
0.1U_0402_16V4Z

RTC Conn

Compal Electronics, Inc.

Compal Secret Data

Security Classification

+RTCVCC
R404
1K_0402_5%
@

Title

ICH9M(2/4)-LAN,IDELPC,RTC
Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

20

of

45

+3VS

Place closely pin B2

L4
E20
M5
AJ23

1 ICH_VGATE
0_0402_5%
ICH_TP11

2
R231
OCP#
CRT_DET

OCP#

CP_PE#
ICH_GPIO17
ICH_GPIO18
ICH_GPIO20
ICH_GPIO27
ICH_GPIO28
SATA_CLKREQ#
ICH_GPIO38
ICH_GPIO39
ICH_GPIO48
ICH_GPIO49
ICH_GPIO57

ICH_GPIO57
[33]
SB_SPKR
[8] MCH_ICH_SYNC#
R402
[20]
ICH_TP3
@
100K_0402_5%
T7
@
T5
@
T6

SB_SPKR
ICH_TP8
ICH_TP9
ICH_TP10

PAD
PAD
PAD

SMBALERT#/GPIO11
STP_PCI#
STP_CPU#
CLKRUN#
WAKE#
SERIRQ
THRM#
VRMPWRGD

A20

TP11

M7
AJ24
B21
AH20
AJ20
AJ21

GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5

For Wireless LAN

[28]
[28]
[28]
[28]

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2

For PCIE LAN

[26]
[26]
[26]
[26]

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3

C1586
C1587

SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
0.1U_0402_16V7K PCIE_ITX_PRX_N1
2KAL90_H0_90+@
1
0.1U_0402_16V7K PCIE_ITX_PRX_P1
2KAL90_H0_90+@
1

C251 2
C252 2

C258 2
C259 2

2
Q13G
2N7002_SOT23

R3

PBTN_OUT#

D20

LAN_RST#

2
100_0402_5%

2
10K_0402_5%

No used Integrated LAN,

connecting LAN_RST# to GND

SB_RSMRST#

R6

ICH_PWROK

B16

PM_SLP_M#

T30

1
2
2
10K_0402_5%

EC_PWROK

1
R384

2
10K_0402_5%

CL_DATA0
CL_DATA1

CL_DATA0 [8]

U10
ICH_PWROK

CL_VREF0_ICH
CL_VREF1_ICH

N29
N28
P27
P26
L29
L28
M27
M26

1
1

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
0.1U_0402_16V7K
PCIE_ITX_PRX_P3
0.1U_0402_16V7K

J29
J28
K27
K26

PERN3
PERP3
PETN3
PETP3

G29
G28
H27
H26

PERN4
PERP4
PETN4
PETP4

PERN2
PERP2
PETN2
PETP2

E29
E28
F27
F26

SPI_CS#1

PERN5
PERP5
PETN5
PETP5

USB_OC#4
USB_OC#8
USB_OC#9
USB_OC#10

D23
D24
F23

SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6

[29] USB_OC#6

10K_1206_8P4R_5%

Internal TPM Strap

Low= Disable*
High= iTPM enable by MCH strap

USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

USBRBIAS
2
1
R413
Within 500 mils
22.6_0402_1%

PVT

DMI Termination Voltage

GPIO49

Low= Desktop used

High= Mobile* (Internal pull-up)

SPI_MOSI
SPI_MISO

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

EC_PWROK

VGATE

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47

AG2
AG1

SPI
USB

PAD T21
@

2
1
+3V
R209
100K_0402_5%
2
1
ACIN
D26
CH751H-40PT_SOD323-2

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

Y27
Y26
W29
W28

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB27
AB26
AA29
AA28

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI_CLKN
DMI_CLKP

SB_RSMRST#
[30,35,36,37,40]

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

ICH9-M ES_FCBGA676

EC_RSMRST# [30]

1
R361

2
4.7K_0402_5%

+3V

D31A
6

BAV99DW-7_SOT363
D31B
4
3
5
BAV99DW-7_SOT363

DMI_MTX_IRX_N2 [8]
DMI_MTX_IRX_P2 [8]
DMI_ITX_MRX_N2 [8]
DMI_ITX_MRX_P2 [8]
DMI_MTX_IRX_N3 [8]
DMI_MTX_IRX_P3 [8]
DMI_ITX_MRX_N3 [8]
DMI_ITX_MRX_P3 [8]

AF29
AF28

DMI_IRCOMP

R360
2.2K_0402_5%

+3VS

CLK_PCIE_ICH# [16]
CLK_PCIE_ICH [16]
R362 24.9_0402_1%
1
2

USB20_N0
USB20_P0
USB20_N1
USB20_P1

USB20_N0
USB20_P0
USB20_N1
USB20_P1

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10

R219
3.24K_0402_1%

Within 500 mils

+1.5VS_PCIE_ICH
[29]
[29] USB/B
[29]
[29] USB\ESATA

CL_VREF0_ICH
R220
453_0402_1%

0.1U_0402_16V4Z
2

[17]
[17] CMOS Camera
[25]
[25] Cardreader
[28]
New Card PVT
[28]
[29]
[29] USB CONN

USB20_N8 [29]
USB20_P8 [29]
USB20_N9 [29]
USB20_P9 [29]
USB20_N10 [28]
USB20_P10 [28]

C280

+3V

R390
3.24K_0402_1%

Bluetooth
Finger Print

CL_VREF1_ICH

Mini Card(WLAN)
1

C456

No Reboot Strap

R389
453_0402_1%

0.1U_0402_16V4Z
2

Low= Default*
High= "No Reboot"

Compal Electronics, Inc.

Compal Secret Data

2008/11/10

DMI_MTX_IRX_N1 [8]
DMI_MTX_IRX_P1 [8]
DMI_ITX_MRX_N1 [8]
DMI_ITX_MRX_P1 [8]

SB_SPKR

Security Classification

1 0_0402_5%

CLK_PCIE_ICH#
CLK_PCIE_ICH

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

@
1 Q33

DMI_MTX_IRX_N0 [8]
DMI_MTX_IRX_P0 [8]
DMI_ITX_MRX_N0 [8]
DMI_ITX_MRX_P0 [8]

T26
T25

USBRBIAS
USBRBIAS#

Issued Date

EC_PWROK [30,32]

R367 2
PAD T29 @

V27
V26
U29
U28

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI_ZCOMP
DMI_IRCOMP

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

D25
E23
[29] USB_OC#0
[29] USB_OC#1

CL_RST#0 [8]
ICH_GPIO24
ICH_GPIO10
ICH_ACIN
ICH_GPIO9

A16
C18
C11
C20

PERN1
PERP1
PETN1
PETP1

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2

[19]

NC7SZ08P5X_NL_SC70-5

F21
D18

1 0_0402_5%

R366
10K_0402_5%

0.1U_0402_16V7K
0.1U_0402_16V7K

PVT

@
+3VS

CL_CLK0 [8]

MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

1
R179

F24
B19

CL_RST0#
CL_RST1#

ICH_PWROK

R232 2
PAD

F22
C19
C25
A19

CK_PWRGD [16]

CL_CLK0
CL_CLK1

CL_VREF0
CL_VREF1

C472
10P_0402_50V8J
@

PM_DPRSLPVR [8,43]

PBTN_OUT# [30]
1
R213

CK_PWRGD

R5

C197
10P_0402_50V8J
@

ICH_PWROK [8]

B13

1
1

CRT_DET#

[18]

10K_1206_8P4R_5%

PM_SLP_S3# [30]
PM_SLP_S4# [30,32]
PM_SLP_S5# [30]

1
R417
PM_BATLOW#

D22

RSMRST#

C29
C28
D27
D26

USB_OC#3
USB_OC#2
USB_OC#0
USB_OC#5

[email protected]
GRATIS - FOR FREE

PWRBTN#
LAN_RST#

1
1

R387
10K_0402_5%

SPI_MOSI

BATLOW#

SLP_M#

2
RP5

DPRSLPVR

CLPWROK

+3VS

CRT_DET
1
2 USB_OC#11
R207
10K_0402_5%
1
2 USB_OC#7
R206
10K_0402_5%

8
7
6
5

ICH_PWROK

M2

DPRSLPVR/GPIO16

For Express Card

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

PVT

High: CRT Plugged

1
2
3
4

S4_STATE#

G20

T34

U22D
[28]
[28]
[28]
[28]

PVT

+3V

RP1

C10

PWROK

CK_PWRGD

8
7
6
5

S4_STATE#/GPIO26

PAD

ICH9-M ES_FCBGA676

PROJECT_ID0
1
2
R156 @ 10K_0402_5%
1
2
R146
10K_0402_5%
1
2
R381
10K_0402_5%
PROJECT_ID1
1
2
R380 @
10K_0402_5%
PM_DPRSLPVR
1
2
R436 @
100K_0402_5%
ICH_GPIO49
1
2
R378 @
1K_0402_5%

1
2
3
4

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

PMSYNC#/GPIO0

D21

AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8

EC_SMI#

EC_SMI#
EC_SCI#
CP_PE#

@
T20 PAD
@
T14 PAD
[16] SATA_CLKREQ#

1
2

PM_CLKRUN#

PAD

T23

R403
10K_0402_5%
@

A14
E19

SUS_CLK

SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

R420
10_0402_5%
@

[4]

+3V

VGATE

VGATE
@

H_STP_PCI#
H_STP_CPU#

ICH_PCIE_WAKE#
SERIRQ
EC_THERM#

[28] ICH_PCIE_WAKE#
[30]
SERIRQ
[30] EC_THERM#
[8,16,43]

A17

P1
C16
E16
G17

SUS_STAT#/LPCPD#
SYS_RESET#

R148
10_0402_5%
@

CLK_ICH_14M [16]
CLK_ICH_48M [16]

MMBT3906_SOT23-3 C
2
B
E

[30] PM_CLKRUN#

EC_LID_OUT#

CLK_ICH_14M
CLK_ICH_48M

[16] H_STP_PCI#
[16] H_STP_CPU#

M6

H1
AF3

R4
G19

CLK14
CLK48

SUS_STAT#
XDP_DBRESET#
PM_SYNC#

[30] EC_LID_OUT#

PAD

[8] PM_SYNC#

+3V
ICH_SMBCLK
2
2.2K_0402_5%
ICH_SMBDATA
2
2.2K_0402_5%
EC_SWI#
2
10K_0402_5%
ICH_SMLINK0
2
10K_0402_5%
ICH_SMLINK1
2
10K_0402_5%
LINKALERT#
2
10K_0402_5%
XDP_DBRESET#
2
10K_0402_5%
2 ICH_PCIE_WAKE#
1K_0402_5%
PM_BATLOW#
2
8.2K_0402_5%
EC_LID_OUT#
2
10K_0402_5%
ICH_GPIO10
2
10K_0402_5%
CP_PE#
2
10K_0402_5%
S4_STATE#
2
10K_0402_5%

SATA
GPIO

@
T10
[4] XDP_DBRESET#

[30]
[30]
[28]
PVT
1
R176
1
R396
1
R230
1
R211
1
R392
1
R210
1
R177
1
R178
1
R398
1
R393
1
R212
1
R214
1
R208 @

clocks

RI#

F19

CLK_ICH_14M

EC_SWI#

2 10K_0402_5%

EC_SWI#

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

CLK_ICH_48M

[30]

SMB

PROJECT_ID1
PROJECT_ID0
R159 1

Direct Media Interface

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

[16,28] ICH_SMBCLK
[16,28] ICH_SMBDATA

AH23
AF19
AE21
AD20

PCI - Express

G16
A13
E17
C17
B18

Power MGT

Place closely pin AC1

U22C
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

SYS / GPIO

SERIRQ
2
10K_0402_5%
PM_CLKRUN#
2
8.2K_0402_5%
EC_THERM#
2
8.2K_0402_5%
H_STP_PCI#
2
10K_0402_5%
H_STP_CPU#
2
10K_0402_5%
SB_SPKR
2
1K_0402_5%
ICH_SPI_MOSI
2
1K_0402_5%
OCP#
2
10K_0402_5%
ICH_GPIO17
2
10K_0402_5%
ICH_GPIO18
2
10K_0402_5%
ICH_GPIO20
2
10K_0402_5%
SATA_CLKREQ#
2
10K_0402_5%
ICH_GPIO38
2
10K_0402_5%
ICH_GPIO39
2
10K_0402_5%
ICH_GPIO48
2
10K_0402_5%

MISC
GPIO
Controller Link

1
R167
1
R169
1
R379
1
R395
1
R229
1
R170
1
R377
1
R145
1
R154
1
R419
1
R153
1
R418
1
R155
1
R147
1
R157

2008/11/24

Deciphered Date

Title

ICH9M(3/4)-USB,GPIO,PCIE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

21

of

45

+ICH_V5REF_SUS

+ICH_V5REF
C464
1U_0402_6.3V6K

+3V
2

+5V
2

+5VALW
2

D33
CH751H-40PT_SOD323-2
1

R416
R415
@ 100_0402_1%
10_0402_5%

+ICH_V5REF_SUS

C470
1U_0402_6.3V6K
+1.5VS_PCIE_ICH

L33
2
1
KC FBM-L11-201209-221LMAT_0805
1

+1.5VS

C434

(220UF*1, 22UF*2, 2.2UF*1)

C250

C249

C243

PVT
220U_D2_4VY_R15M
10U_0805_10V4Z
2
2
2
10U_0805_10V4Z
2.2U_0603_6.3V6K

+1.5VS_SATAPLL_ICH

L35 1
2
MBK1608301YZF_0603

+1.5VS

(10UF*1,

C453
C454
10U_0805_10V4Z
2
2
1UF*1)
1U_0402_6.3V6K

AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

VCCRTC
V5REF
V5REF_SUS
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

VCCA3GP

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
V_CPU_IO[1]
V_CPU_IO[2]
VCC3_3[01]
VCC3_3[02]
VCC3_3[07]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

G
1

Q36
AO3413_SOT23-3

0.1U_0402_16V4Z
2

1
C460

C471

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

+5V

AC9
AC18
AC19
AC21
G10
G9
AC12
AC13
AC14

close to AC7

AJ5

+1.5VS
1

0.1U_0402_16V4Z
2

1
AA7
AB6
AB7
AC6
AC7

close to AJ5
2
0.1U_0402_16V4Z
2
1 +VCCLAN1_05_INT_ICH
C463
0.1U_0402_16V4Z
+VCCLAN_ICH

R400

0_0603_5%
C461

A10
A11
A12
B12

2
0.1U_0402_16V4Z

+1.5VS

+VCC_GLANPLL_ICH
R368

0_0603_5%
1

A27

C442

D28
D29
E26
E27

C443

(10UF*1, 2.2UF*1)10U_0805_10V4Z
2
2.2U_0603_6.3V6K
+1.5VS

A26

+VCCGLAN_ICH
R364

(4.7UF*1)

0_0603_5%
C439

VCCSUS1_5[2]

C235

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

+1.5VS_DMIPLL_ICH
L34 1
2
MBK1608301YZF_0603

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

VCCSUS3_3[05]

C435
C436
10U_0805_10V4Z
2
0.01U_0402_16V7K

+1.05VS

(4.7UF*1)

4.7U_0805_10V4Z
2

R29
W23
Y23
AB23
AC23

+1.05VS
C242

AG29
AJ6
AC10

C206

C236

(4.7UF*1, 0.1UF*2)

4.7U_0805_10V4Z

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

AD19
AF20
AG24
AC20

close to AG29

close to AD19

C433

C462

C205

close to AJ6

C279

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCUSBPLL

VCCLAN1_05[1]
VCCLAN1_05[2]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

VCCCL1_05
VCCCL1_5

VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN3_3

C253

VCCCL3_3[1]
VCCCL3_3[2]

close to B9

C245

close to K7

+VCC_HDA_ICH

AJ4

R408

0_0603_5%

AJ3
1
AC8 TP_VCCSUS1_05_ICH_1
F17 TP_VCCSUS1_05_ICH_2
AD8 TP_VCCSUS1_5_ICH_1
F18

PAD
PAD

@
T8
@
T15

PAD

T9

R407

0_0603_5%

R411

A18
D16
D17
E22

C254
0.1U_0402_16V4Z

0_0603_5%

R410

0_0603_5%

+3V
+1.5V

C468
0.1U_0402_16V4Z

AF1

+3V
C234

C233

0.1U_0402_16V4Z
2
2
0.022U_0402_16V7K

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22
G23

+1.5VS

0.1U_0402_16V4Z

+VCCSUS_HDA_ICH

+VCCSUS1_5_ICH_INT_2
1

+3VS

C466

0.022U_0402_16V7K

VCC1_5_A[20]

VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

close to G6
+3VS

B9
F9
G3
G6
J2
J7
K7

C455

VCC1_5_A[18]
VCC1_5_A[19]

+1.5VS

(10UF*1, 0.01UF*1)

VCC1_5_A[17]

GLAN POWER

C465

VCCSUS1_5[1]

USB CORE

C204

VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

VCCSUS1_05[1]
VCCSUS1_05[2]

ATX

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]

ARX

C458

VCCPSUS

+1.5VS

[35] SBPWR_EN#

VCCSUSHDA

U22E

+1.05VS
C247

VCCSATAPLL

VCCPUSB

AJ19

+5VALW

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C246

VCCHDA

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
2
1U_0402_6.3V6K

A6

0.1U_0402_16V4Z

+ICH_V5REF

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C451

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C452
D32
CH751H-40PT_SOD323-2

CORE

A23

+RTCVCC
R405
100_0402_1%

U22F

VCCP_CORE

PCI

+3VS

+5VS

close to A18

(0.1UF*1, 0.022UF*2)

close to T1

+VCCCL1_05_INT_ICH
+VCCCL1_5_INT_ICH
C256
@
1U_0402_6.3V6K

A24
B24

+3VS

C257
@

C255

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

2
0.1U_0402_16V4Z

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

(0.1UF*1)

2
0.1U_0402_16V4Z

ICH9-M ES_FCBGA676
A

(1UF*1, 0.1UF*1)

ICH9-M ES_FCBGA676

4.7U_0805_10V4Z

2008/11/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

+3VS

2008/11/24

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

Title

ICH9M(4/4)-POWER&GND
Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

22

of

45

SATA HDD Conn.

JSATA1
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

[20] SATA_ITX_C_DRX_P0
[20] SATA_ITX_C_DRX_N0
D

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

[20] SATA_DTX_C_IRX_N0
[20] SATA_DTX_C_IRX_P0

C376 1
1
C377

2 0.01U_0402_16V7K
2
0.01U_0402_16V7K

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

C374
10U_0805_10V4Z

C378
0.1U_0402_16V4Z

+5VS
C379
1000P_0402_50V7K

C380
10U_0805_10V4Z

C382
0.1U_0402_16V4Z

+3VS
C381
1000P_0402_50V7K

+5VS

1
2
3
4
5
6
7

GND
HTX+
HTXGND
HRXHRX+
GND

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
GND
VCC12
GND

24
23

OCTEK_SAT-22SU1G_NR
CONN@

SATA ODD Conn.

JSATA2

SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1

[20] SATA_ITX_C_DRX_P1
[20] SATA_ITX_C_DRX_N1

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1

[20] SATA_DTX_C_IRX_N1
[20] SATA_DTX_C_IRX_P1

C265
C264

1
1

2 0.01U_0402_16V7K
2
0.01U_0402_16V7K

SATA_DTX_IRX_N1
SATA_DTX_IRX_P1
R174 1

2 1K_0402_1%
+5VS

C241

C240

10U_0805_10V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

+5VS

C239

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

GND
GND

16
17

OCTEK_SLS-13DB1G_NR

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

HDD & ODD Connector

Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

23

of

45

+HDMI_5V_OUT

close to U1 VCC (+3VS) pins (one Pin one Capacitor)

+3VS

D20

C467

PVT

+3VS

+3VS

2 4.7K_0402_5%

2 4.7K_0402_5%
PVT
1
R126

2
3.6K_0402_5%

[10] TMDS_B_HPD#

To GMCH
8

SDVO_SCLK

SDVO_SCLK

9
R511 1

+3VS

VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V

SCL_SINK
SDA_SINK
HPD_SINK
DDC_EN

3
4

SDVO_SDATA

[8] SDVO_SDATA
[8]

2 4.7K_0402_5%

R125
47K_0402_5%

R124
47K_0402_5%

R127 1

OE*
2
11
15
21
26
33
40
46

2 4.7K_0402_5%

R431 1

R432 1

+3VS

2 4.7K_0402_5%

10

UMA_DVI_TXCUMA_DVI_TXC+

13
14

UMA_DVI_TXD1UMA_DVI_TXD1+

16
17

UMA_DVI_TXD2+
UMA_DVI_TXD2-

19
20

UMA_DVI_TXD0+
UMA_DVI_TXD0-

22
23

FUNCTION1
FUCNTION2

FUNCTION3
FUNCTION4

25

HDMI_DET#

R448

+3VS

HDMI_SCLK

28

HDMI_SDATA

29

R115
2.2K_0402_5%

30

HDMI_DET

32

R435 1

2 4.7K_0402_5%

+3VS

34
35

R434 1

@ 2 4.7K_0402_5%

+3VS

R433 1

@ 2 4.7K_0402_5%

R414 1

@ 2 4.7K_0402_5%

R412 1

@ 2 4.7K_0402_5%

ANALOG1(REXT)
HPD_SOURCE

HDMI_DET#

HDMI_DET

SDA_SOURCE
SCL_SOURCE
ANALOG2

Trace

AS Short PASS

OUT_D4+
OUT_D4-

IN_D4+
IN_D4-

OUT_D3+
OUT_D3-

IN_D3+
IN_D3-

OUT_D2+
OUT_D2-

IN_D2+
IN_D2-

OUT_D1+
OUT_D1-

IN_D1+
IN_D1THERMAL_GND

1
5
12
18
24
27
31
36
37
43

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

48
47

HDMI_PCIE_MTX_C_GRX_N3
HDMI_PCIE_MTX_C_GRX_P3

45
44

HDMI_PCIE_MTX_C_GRX_N1
HDMI_PCIE_MTX_C_GRX_P1

42
41

HDMI_PCIE_MTX_C_GRX_P0
HDMI_PCIE_MTX_C_GRX_N0

39
38

HDMI_PCIE_MTX_C_GRX_P2
HDMI_PCIE_MTX_C_GRX_N2

Q12
2N7002_SOT23

For Power Saving Application

When Plug-in HDMI
HDMI_HPD=High OE#=Low Enable Level Shift
When Plug-out HDMI
HDMI_HPD=Low OE#=High Disable Level Shift

HDMI_PCIE_MTX_C_GRX_N[0..3]
HDMI_PCIE_MTX_C_GRX_P[0..3]

49

2
G

+3VS

PVT
C

+HDMI_5V_OUT

R449

R128 1

1
C172
0.1U_0402_16V4Z

PSOT24C-LF-T7_SOT23-3

U7

+3VS

W=40mils

C474

1.1A_6VDC_FUSE

C475

C487

0.1U_0402_16V4Z

R441
1
2
100K_0402_5%

C486

2.2K_0402_5%

+HDMI_5V

RB491D_SC59-3

2.2K_0402_5%
1
2
2
1

C473
@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C485
@

0.1U_0402_16V4Z

10U_0805_10V4Z

C484
@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C469
@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

F2

+5VS

+3VS

HDMI_PCIE_MTX_C_GRX_N[0..3]

[10]

HDMI_PCIE_MTX_C_GRX_P[0..3]

[10]

20071031:
Add U1. 49 (THERMAL_GND) to GND Plane

ASM1442T QFN 48P

PVT
UMA_DVI_TXC-

1
R130

4
1
B

2
0_0402_5%

L15 @

HDMI_R_CK-

3
2
B

WCM-2012-900T_0805

UMA_DVI_TXC+

1
R131

2
0_0402_5%

HDMI_R_CK+

UMA_DVI_TXD0-

1
R139

2
0_0402_5%

HDMI_R_D0-

+HDMI_5V_OUT
(pin 19) plug in 5V

JHDMI1

WCM-2012-900T_0805
2
2

L18 @
1

HDMI_DET

1
4

HDMI_SDATA
HDMI_SCLK

3
HDMI_R_CK-

UMA_DVI_TXD0+

1
R138

2
0_0402_5%

UMA_DVI_TXD1-

1
R132

2
0_0402_5%

HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2-

4
1

4
1
L16

UMA_DVI_TXD1+

1
R133

UMA_DVI_TXD2-

1
R137

L17
1
4

UMA_DVI_TXD2+

1
4

1
R136

3
2
@

HDMI_R_D2+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

Intel Cantiga TMDS Pin Definition

20
21
22
23

TYCO_1939864-1
CONN@

WCM-2012-900T_0805

DIP

2
0_0402_5%

TMDS_B_CLK
TMDS_B_CLK#

PEG_TXP_3
PEG_TXN_3

TMDS_B_DATA0
TMDS_B_DATA0#

PEG_TXP_2
PEG_TXN_2

TMDS_B_DATA1
TMDS_B_DATA1#

PEG_TXP_1
PEG_TXN_1

TMDS_B_DATA2
TMDS_B_DATA2#

PEG_TXP_0
PEG_TXN_0

TMDS_B_HPD#

PEG_RXP_3

2
0_0402_5%
@

WCM-2012-900T_0805
2
2
3

2
0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/10/16

Deciphered Date

2008/10/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HDMI ASM1442T
Size
C
Date:

Document Number

Rev
0.2

KALG1
Tuesday, March 24, 2009

Sheet
1

24

of

45

2
R303

1
0_0402_5%

U14

2
R265
2
R290

+3VS
+3VALW

2
C328

1
0_0603_5%
1
@ 0_0603_5%

1
0.1U_0402_16V4Z

+XDPWR_SDPWR_MSPWR

1
3
7
9
11
33

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

8
44
45
47
48

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

4
5
14

DM
DP
GPIO0

VREG
MS_D4
NC

10
22
30

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10
MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

XTAL_CTR
MS_D5

13
24

EEDO
EECS
EESK
SD_CMD

15
16
17
36

C309
4.7U_0603_6.3V6K

R306
100K_0402_5%

C326
0.1U_0402_16V4Z

RST#_L

2
R307

RST#
MODE_SEL
XTLO
XTLI

@
2

RST#
1
0_0402_5%

[21]
[21]
[36]

USB20_N4
USB20_P4
5IN1_LED#

USB20_N4
USB20_P4

Vender suggesttion
C335
1U_0402_6.3V4Z

MODE_SEL

R308
0_0402_5%

1/9
@

RREF
DGND
DGND

6
46

AGND
AGND

XDCLE
XDCE#
XDALE
SDDAT2_XDRE#
SDDAT3_XDWE#
XD_RDY
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK_L
SDDAT6_XDD7_MSD3
MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
XDD5_MSBS
XDD4_SDDAT1
SDCD
SDWP
XDCD
XTAL_CTR

2
R236

1
0_0603_5%

SDCLK_XDD1_MSCLK
1
0_0402_5%

2
R301

+3VS

XTAL_CTR
If Open , use 12MHz. crystal
If Pull high , use CLKGEN 48MHz.

R302
6.19K_0402_1%

SD_CMD

RTS5159-GR LQFP 48P

R309
0_0402_5%
Change to

RT5159-GR <SA00002YP00>

20081104

R312
33_0402_5%

@
1
C338

2
6P_0402_50V8D

R310
0_0402_5%

2
12
32

2
1U_0402_6.3V4Z

XTLI

2
0_0402_5%

1
R311

[16] CLK_SD_48M

@ C336
47P_0402_50V8J

1
C325

C339
22P_0402_50V8J

@ Y3
12MHZ_16PF_6X12000012
2

1
@

EMI

@
1
C337

2
6P_0402_50V8D

XTLO

+XDPWR_SDPWR_MSPWR

JREAD1

C299
0.1U_0402_16V4Z

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
XDALE
XDCD
XD_RDY
SDDAT2_XDRE#
XDCE#
XDCLE

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31

7IN1 GND
7IN1 GND

41
42

7 IN 1 CONN

SD-VCC
MS-VCC

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2
SD_CMD
SDCD

1
C297

32
10
9
8
7
6
5
4

10U_0805_10V4Z

1
R235
100K_0402_5%

+XDPWR_SDPWR_MSPWR

XD-VCC

SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT7_XDD2_MSD2
SDDAT1_XDD3_MSD1
XDD4_SDDAT1
XDD5_MSBS
SDDAT0_XDD6_MSD0
SDDAT6_XDD7_MSD3

SDWP
SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2
SDDAT6_XDD7_MSD3
MS_INS#
XDD5_MSBS

7IN1 GND
7IN1 GND

SDCLK_XDD1_MSCLK

3
B

R237
33_0402_5%

@
CONN@
2

TAITW_R015-B10-LM

1
@

C298
22P_0402_50V8J

1/5

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/11/10

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Card Reader Realtek5159

Size Document Number
Custom

Rev
0.1

KALG1

Date:

Sheet

Tuesday, March 24, 2009

1

25

of

45

+3VALW
+3V_LAN

C67

PVT
R471 0_0402_5%
1
2

0.1U_0402_16V4Z

C68

1U_0402_6.3V4Z

C74

10U_0805_10V4Z

C75

2
0_1206_5%
10U_0805_10V4Z

1
R44

60mil

D12
10/100_LINK_LED

1000_LINK_LED

Place Close to Pin 2

LAN_LINK# [27]

@
CHP202UPT_SOT323-3

+1.8_VDD/LX
+AVDD_CEN
L5
+1.8_VDD/LX
1
2
S INDUC_ 4.7UH +-20% SIA4012-4R7M
pin 1 = 1A
U3

31
33

SMCLK
SMDATA

25MHZ_20P
C39
33P_0402_50V8J

PVT
2

DVDDL0
AVDDL/DVDDL/DVDDL
DVDDL1
SPI_CLK/DVDDL/DVDDL

C33
33P_0402_50V8J
49

GND

12

SPI_DO/AVDDH/AVDDH
AVDDH0
AVDDH1

AR8131L-AL1E_QFN48_6X6

1
1

1
2

2 C24

0.1U_0402_16V4Z

2 C23

0.1U_0402_16V4Z

2 C22

0.1U_0402_16V4Z

C59

C63

C58

CTR12

PVT

SA000031Z00 S IC AR8131-AL1E QFN 48P E-LAN CTRL

R33
2.37K_0402_1%

+1.2_DVDDL
CTR12

C32

RBIAS

25
19
15

1
+1.2_AVDDL

+1.2_DVDDL

46
45
32
28

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 C25

+1.2_AVDDL
C64
0.1U_0402_16V4Z
1
2

C31

TESTMODE
NC

AVDDL0 42
AVDDL1 39
AVDDL2 36
DVDDL/AVDDL/AVDDL 22
AVDDL3 16
+AVDDVCO1
AVDDL4 11
8
AVDDL5 1.1V
regulator output

C66

34
35

AR8121/8131

0.1U_0402_16V4Z

XTLO
XTLI

Atheros

Y1
LAN_XTALO 2

9
10

1U_0402_6.3V4Z

R36
0_0402_5%

WAKEn
TX_N
TX_P
RX_N
RX_P

C35

XTALO
LAN_XTALI

VAUX_AVL/VBG1P18/VBG1P18

4
37
38
44
43

[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]

1U_0402_6.3V4Z

PCIE_PTX_IRX_N3
PCIE_PTX_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3

0.1U_0402_16V4Z

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

[21]
[21]
[21]
[21]

1
1

LAN_MIDI0LAN_MIDI0+
LAN_MIDI1LAN_MIDI1+
LAN_MIDI2LAN_MIDI2+
LAN_MIDI3LAN_MIDI3+

C65

7
C60
C61

CLK_PCIE_LAN# [16]
CLK_PCIE_LAN [16]
LAN_MIDI0LAN_MIDI0+
LAN_MIDI1LAN_MIDI1+
LAN_MIDI2LAN_MIDI2+
LAN_MIDI3LAN_MIDI3+

0.1U_0402_16V4Z

14
13
18
17
21
20
24
23

PERSTn

C62

TXN0/TXN0/TRXN0
TXP0/TXP0/TRXP0
RXN1/RXN1/TRXN1
RXP1/RXP1/TRXP1
NC/NC/TRXN2
NC/NC/TRXP2
NC/NC/TRXN3
NC/NC/TRXP3

[8,19,30] PLT_RST#

1000_LINK_LED

0.1U_0402_16V4Z

40
41

C36

REFCLKN
REFCLKP

[27]

LAN_CLKREQ# [16]

1
2
49.9_0402_1%
1
2
49.9_0402_1%
1
2
49.9_0402_1%
1
2
49.9_0402_1%
1
2
49.9_0402_1%
1
2
49.9_0402_1%
1
2
49.9_0402_1%
1
2
49.9_0402_1%

0.1U_0402_16V4Z

VDDLO/CTR12/CTR12

2
0_0402_5%

0.1U_0402_16V4Z

SPI_DI/NC/LED_Link1000n

26

LAN_ACTIVITY#
1
R35

C57

27

1U_0402_6.3V4Z

SPI_CS/LED_DUPLEXn/LED_DUPLEXn
VDD3V/VDDHO/VDDHO

0.1U_0402_16V4Z

CTR12
2
0.1U_0402_16V4Z

VDD3V

C34

C1977 close to Pin6

LAN_MIDI0+
R30
LAN_MIDI0R29
LAN_MIDI1+
R28
LAN_MIDI1R27
LAN_MIDI2+
R26
LAN_MIDI2R25
LAN_MIDI3+
R24
LAN_MIDI3R23

10/100_LINK_LED

0.1U_0402_16V4Z

C37
0.1U_0402_16V7K
2
1

TWSI_DATA
TWSI_CLK
LED_LINK10_100n
LED_ACTn

VDDHO/VDD18O/VDD18O

0.1U_0402_16V4Z

+AVDD_CEN

30
29
48
47

C30

C29

+3V_LAN

C38

[30]
EC_PME#
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3

Place Close to LAN chip

pin 1,2 60mil

0.1U_0402_16V4Z

C76

C84

10U_0805_10V4Z

0.1U_0402_16V4Z

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/04/16

Deciphered Date

2008/11/24

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Atheros AR8131
Rev
0.1

KALG1

Tuesday, March 24, 2009

D

Sheet

26

of

45

+AVDD_CEN

pull down circuit :

more power saving in
no-overclocking mode

T2
[26]
[26]

LAN_MIDI1+
LAN_MIDI1-

LAN_MIDI0+
LAN_MIDI0-

1
2
3
4
5
6
7
8

LAN_MIDI1+
LAN_MIDI1-

TD+
TDCT
NC
NC
CT
RD+
RD-

TX+
TXCT
NC
NC
CT
RX+
RX-

RJ45_MIDI0+
RJ45_MIDI0-

16
15
14
13
12
11
10
9

L_LAN_ACTIVITY#

1
R438
510_0402_5%

[26] LAN_ACTIVITY#

RJ45_MIDI1+
RJ45_MIDI1-

[26]
[26]

LAN_MIDI0+
LAN_MIDI0-

JLAN

C481
2
220P_0402_50V7K

BOTHHAND_NS0013LF

R437
5.1K_0402_5%

T1
[26]
[26]

[26]
[26]

LAN_MIDI2+
LAN_MIDI2-

LAN_MIDI2+
LAN_MIDI2-

1
2
3
4
5
6
7
8

LAN_MIDI3+
LAN_MIDI3-

LAN_MIDI3+
LAN_MIDI3-

TD+
TDCT
NC
NC
CT
RD+
RD-

TX+
TXCT
NC
NC
CT
RX+
RX-

RJ45_MIDI2+
RJ45_MIDI2-

16
15
14
13
12
11
10
9

Yellow LED+

PR4-

RJ45_MIDI3+

PR4+

RJ45_MIDI1-

PR2-

RJ45_MIDI2-

PR3-

RJ45_MIDI2+

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

2
R439

+3V_LAN

Yellow LED-

11

RJ45_MIDI3-

LAN_LINK#

[26] LAN_LINK#

12

10

SHLD2

14

SHLD1

13

Green LED-

1
510_0402_5%

Green LED+
SUYIN_100073FR012G101ZL

RJ45_MIDI3+
RJ45_MIDI3-

C483
220P_0402_50V7K

BOTHHAND_NS0013LF
RJ45_GND

1
2
C507
1000P_1206_2KV7K

R430

R429

R428

Place close to TCT pin

C515
4.7U_0805_10V4Z

L_LAN_ACTIVITY#
1
2
C480 @
68P_0402_50V8J
LAN_LINK#

C19

C479

0.1U_0402_16V4Z

2
75_0402_1%
2
75_0402_1%
1
75_0402_1%
1
75_0402_1%

0.1U_0402_16V4Z

C21

C26

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C20

+AVDD_CEN

40mil

R427

2
B

LANGND
1

RJ45_GND

1
2
C482 @
68P_0402_50V8J

40mil

For EMI

2008/11/10

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

LAN Magnetic & RJ45

Size
B
Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
1

27

of

45

For Wireless LAN

+3VS_WLAN

+3VS_WLAN
1

1
R329
R328 1
@

2
0_1206_5%
2 0_1206_5%

+1.5VS

1A

Mini Card Power Rating

1

+3VS

C358

+3V

4.7U_0805_10V4Z

0.1U_0402_16V4Z

ICH_PCIE_WAKE#1
WLAN_BT_DATA
WLAN_BT_CLK

[21] ICH_PCIE_WAKE#
[29] WLAN_BT_DATA
[29] WLAN_BT_CLK
[16] MINI2_CLKREQ#

C359

0.1U_0402_16V4Z

@
R326 2 0_0402_5%

[16] CLK_PCIE_MINI2#
[16] CLK_PCIE_MINI2

[21] PCIE_PTX_C_IRX_N2
[21] PCIE_PTX_C_IRX_P2
[21] PCIE_ITX_C_PRX_N2
[21] PCIE_ITX_C_PRX_P2
+3VS_WLAN

For MINICARD Port80 Debug

2

1 R321

2 0_0402_5% CL_RST#2_R

C362
4.7U_0805_10V4Z

C361
0.1U_0402_16V4Z

C360

Power

0.1U_0402_16V4Z

JMINI2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

(WAKE#)

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

Primary Power (mA)

2
4
6
8
10
12
14
16

+3VS_WLAN

Auxiliary Power (mA)

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

Normal

+1.5VS

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

WL_OFF#
PLT_RST_BUF#
+3V_WLAN
R323 1
R322 1
MINI2_SMBCLK R283 1
MINI2_SMBDATA R295 1

WL_OFF# [30]
PLT_RST_BUF# [19]

2 0_0603_5%
2 0_0603_5%

+3VS
+3V

2 0_0402_5% ICH_SMBCLK
2 0_0402_5% ICH_SMBDATA

@
@

ICH_SMBCLK [16,21]
ICH_SMBDATA [16,21]

USB20_N10 [21]
USB20_P10 [21]

(LED_WWAN#)
(LED_WLAN#)

MINI1_LED#

MINI1_LED# [31]

(9~16mA)

53
54
55
56

G1
G2
G3
G3

[30] E51TXD_P80DATA
[30] E51RXD_P80CLK

E51TXD_P80DATA
E51RXD_P80CLK

C357

FOX_AS0B226-S99N-7F

CONN@

New Card Power Switch

STBY#

NC

CPPE#
CPUSB#

GND
Thermal_Pad

+3VS

C1593

[21]
[21]

R484
10K_0402_5%
KAL90_H0_90+@

CLKREQ1#

2
+1.5VS

RCLKEN1 2
G

CP_USB#
ICH_SMBCLK
ICH_SMBDATA

+1.5VS_CARD
ICH_PCIE_WAKE#
PERST1#

+3VS_CARD
1

21

G577NSR91U_TQFN20_4x4

USB20_N5
USB20_P5

+3VALW_CARD

+3VS

RCLKEN

+3V

0.1U_0402_16V4Z

C1592

KAL90_H0_90+@

10U_0805_10V4Z

0.1U_0402_16V4Z

C1591

KAL90_H0_90+@

+3VS

KAL90_H0_90+@

PERST1#

16

C1590

KAL90_H0_90+@

10U_0805_10V4Z

19

C1589

JEXP1

Imax = 0.75A

C1594
KAL90_H0_90+@
0.1U_0402_16V4Z

Q42
2N7002_SOT23
KAL90_H0_90+@

CLKREQ1#
CP_PE#

[21] CP_PE#
[16] CLK_PCIE_CARD#
[16] CLK_PCIE_CARD

CP_PE#
10
(Internal Pull High to AUXIN)
CP_USB#
9
(Internal Pull High to AUXIN)
RCLKEN1
18

OC#
PERST#

G Vcc

SHDN#

+3VALW_CARD

C1588

SUSP#

SYSRST#

+3VS_CARD

40mil

KAL90_H0_90+@

20

15

Imax = 1.35A

0.1U_0402_16V4Z

SYSON

AUX_OUT

3
5

60mils

KAL90_H0_90+@

PCI_RST#

AUX_IN

3.3Vout
3.3Vout

Imax = 0.275A

+1.5VS_CARD

+1.5VS_CARD

[30,32,35,41] SUSP#

+3V

3.3Vin
3.3Vin

11
13

PCI_RST#

2
4
17

1.5Vout
1.5Vout

+3VS_CARD

[19]

[30,32,35,41] SYSON

+3VS

1.5Vin
1.5Vin

10U_0805_10V4Z

12
14

+1.5VS

New Card Socket (Left/TOP)

+3VALW_CARD

40mil

KAL90_H0_90+@

U28

EXP_CLKREQ# [16]

U29
KAL90_H0_90+@
NC7SZ32P5X_NL_SC70-5

[21] PCIE_PTX_C_IRX_N1
[21] PCIE_PTX_C_IRX_P1
[21] PCIE_ITX_C_PRX_N1
[21] PCIE_ITX_C_PRX_P1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

2008/11/10

Issued Date

2008/11/24

Deciphered Date

29
30

Date:

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

GND
GND

Compal Electronics, Inc.

Compal Secret Data

Security Classification

GND
GND

SANTA_131851-A_LT
CONN@

1
1
1
C1595
C1596
C1597
KAL90_H0_90+@
KAL90_H0_90+@
KAL90_H0_90+@
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
2
2
2

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

NEW CARD & MINI CARD-WLAN

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
E

28

of

45

+3V

+3VS

JUSB2

R135
0_0603_5%
KAL90_G0_90+@
JP16
6
5
4
3
2
1

R134
0_0603_5%
@
C196
KAL90_G0_90+@
0.1U_0402_16V4Z
2
1
USB20_N9
USB20_P9

[21] USB20_N9
[21] USB20_P9

+USB_VCCA
USB20_N1
USB20_P1

D23
SM05T1G_SOT23-3

G2
G1
4
3
2
1

Finger Print Conn.

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

SUYIN_020173MR004G565ZR
CONN@

PCB FootPrint :
"SUYIN_020173MR004G565ZR_4P-S"
only for CO- LAY JP17 USE

ACES_85201-04051
CONN@
1

1
2
3
4

ESATA CONN
+3VALW

+3VS
+USB_VCCA

C364
USB20_P1

Q31
AO3413_SOT23-3

+USB_VCCA

W=40mils

+BT_VCC
1

C366

Vp

CH4

Vn

CH1

220U_6.3*5.9_6.3VM

R327
300_0603_5%

Q32
2N7002_SOT23
3

R325 10_0402_5%2 @
1
2
R324 0_0402_5% @

1 KAL90_90+@ 0.01U_0402_16V7K SATA_IRX_DTX_N5

SATA_IRX_DTX_P5
1
KAL90_90+@ 0.01U_0402_16V7K

C158 2
2
C159

D19

+USB_VCCA

CONN@
ACES_87213-0800G
8
10
8 GND
7
7
6
6
5
5
4
4
3
3
2 2
1 1 GND 9

SATA_ITX_C_DRX_N5

CH3

Vp

CH4

KAL90_90+@
3
CH2

5
6
7
8
9
10
11

GND
A+
AGND
BB+
GND

Vn

CH1

PVT

USB
2

ESATA
12
13
14
15

SHIELD
SHIELD
SHIELD
SHIELD

TYCO_1909574-1
CONN@

TYCO_1759594-1_11P

SATA_IRX_DTX_N5

CM1293-04SO_SOT23-6

+3V

80mil

+5VALW

+USB_VCCA

R452
0_0402_5%
1
2

U27

C510

SYSON#

1
2
3
4

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

R450
100K_0402_5%

8
7
6
5

1
2
R451
10K_0402_5%

TPS2061DRG4_SO8
4.7U_0805_10V4Z

USB_OC#1 [21]

Bluetooth Conn.

PVT :Conn. reverse

VBUS
DD+
GND

SATA_ITX_C_DRX_P5

JP18
3

1
2
3
4

+BT_VCC

[28] WLAN_BT_DATA
[28] WLAN_BT_CLK

SATA_ITX_C_DRX_P5
SATA_ITX_C_DRX_N5

[20] SATA_DTX_C_IRX_N5
[20] SATA_DTX_C_IRX_P5

PVT
SATA_IRX_DTX_P5

USB20_P8
USB20_N8

USB20_N1
USB20_P1

USB20_N1
USB20_P1

[20] SATA_ITX_C_DRX_P5
[20] SATA_ITX_C_DRX_N5

2
G

C509

2
0.1U_0402_16V4Z

JESATA
[21]
[21]

4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z

USB20_N1

CM1293-04SO_SOT23-6

C365

[21]
[21]

C508

0.1U_0402_16V4Z
2

1000P_0402_50V7K
1

C495

2
10K_0402_5%
C368

1U_0603_10V4Z

1
R330

BT_ON#

[30]

0.1U_0402_16V4Z
2

W=60mils

+USB_VCCA

KAL90_G0_90+@
CH3
CH2 3

D18

C367

USB_OC#6 [21]
1

2
2

+USB_VCCA

C496
0.1U_0402_16V4Z

W=80mils
+USB_VCCA

220U_6.3*5.9_6.3VM

+
2

+USB_VCCA

Vp

CH4

Vn

CH1

USB20_N6
USB20_P6

USB20_N6
USB20_P6

1
2
3
4

1
2
3
4
5
6
7
8
GND
GND

JUSB1
[21]
[21]

5
6
7
8

USB20_N6

CM1293-04SO_SOT23-6

VCC
DD+
GND
GND1
GND2
GND3
GND4

+5VALW
SYSON#
USB20_N0
USB20_P0

+5VALW
SYSON#

[35,42]

USB20_N0 [21]
USB20_P0 [21]

C363

4.7U_0805_10V4Z
2

USB_OC#0 [21]

ACES_85201-08051

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/11/10

Issued Date

1
2
3
4
5
6
7
8
9
10

SUYIN_020173MR004G565ZR
CONN@

USB CONN.
[email protected]
GRATIS - FOR FREE

80mil

JP15

D21
USB20_P6

KAL90_G0_90+@
3
CH3
CH2

To USB/B Connector

C511
470P_0402_50V7K

1
C497

2008/11/24

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

BT & & Finger Print & eSATA & USB Conn

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
E

29

of

45

+3VALW

2 EC_SMB_CK1
4.7K_0402_5%
2 EC_SMB_DA1
4.7K_0402_5%
1 EC_I2C_INT2
10K_0402_5%
EC_RCIRRX

1
R254
+3VS

2 LID_SW #
100K_0402_5%

1
R188
1
R187
+3VS

2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%

[31,38]
[31,38]
[4,31]
[4,31]

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

[21] PM_SLP_S3#
[21] PM_SLP_S5#
[21]
EC_SMI#
[31]
LID_SW #
[26]
EC_PME#
[8] MCH_TSATN_EC#
[4] FAN_SPEED1
[29]
BT_ON#
[32]
ON/OFF
[36] PW R_SUSP_LED
[31,36] NUM_LED#

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

EC_CRY1
EC_CRY2

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

R189
10K_0402_5%
@

AVCC

DAC_BRIG
EN_DFAN1
IREF

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE
EC_I2C_INT2

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

3S/4S#
65W /90W #
SBPW R_EN
ID_JAL90_JAW 50#

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK
EC_SPICS#/FSEL#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RCIRRX
ON_0FF_TP SW #
FSTCHG
BATT_RED_LED#
CAPS_LED#
BATT_Yellow Green_LED#
PW R_LED
SYSON
VR_ON
ACIN

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

SPI Flash ROM

SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

3
1
1
C1599
4.7U_0805_10V4Z
2 KAL90_90+@

Vs
GND

OUT
GND

4
2

IR1 KAL90_90+@
TSOP36236TR_4P

RCIRRX

SA00001J580

[33]

PAD T24 @

ACOFF
[40]
ECAGND
2
1
C262 0.01U_0402_16V7K
BATT_OVP [40]
ADP_I
[40]

AD_BID0

3S/4S#

V18R

124

KB926QFD3_LQFP128_14X14

+3VALW

ID_JAL90_JAW 50#
2
R204
@
2
R203
@
100K_0402_5%

DAC_BRIG [17]
EN_DFAN1 [4]
IREF
[40]
CALIBRATE# [40]
EC_MUTE [34]
PVT
EC_I2C_INT2 [32]
PGD_IN
[43]
BT_LED# [31]
TP_CLK [31]
TP_DATA [31]

BT_LED#
TP_CLK
TP_DATA

EC_LID_OUT#
EC_ON

65W /90W #
2
R193

3S/4S# [40]
65W /90W # [40]
SBPW R_EN [35,41]

EC_PW ROK
BKOFF#
W L_OFF#
ON_0FF_TP LED#
BATTERY_LED#L 1

R205
0_0402_5%

ENBKL
EAPD
SUSP#
PBTN_OUT#
MC_RST#

+3VALW

2008/11/10

Issued Date

Rb

AD_BID0
R190

8.2K_0402_5%

C263
0.1U_0402_16V4Z

2
B

EC_CRY1

EC_CRY2

PVT
C283
27P_0402_50V8J

PM_SLP_S4# [21,32]
ENBKL
[10]
EAPD
[33]
EC_THERM# [21]
SUSP#
[28,32,35,41]
PBTN_OUT# [21]
MC_RST# [31]

PVT

C284
27P_0402_50V8J

X1
32.768KHZ_12.5P_MC-306

C289
4.7U_0805_10V4Z

C270
BATT_TEMP
2
C269
BATT_OVP
2
C303
ACIN
2

For KB926 D3 reversion

Deciphered Date

100P_0402_50V8J
1
100P_0402_50V8J
1
100P_0402_50V8J
1

Compal Electronics, Inc.

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

R191 @
100K_0402_5%

Ra
ON_0FF_TP SW # [31]
FSTCHG [40]
BATT_RED_LED# [36]
CAPS_LED# [36]
BATT_Yellow Green_LED# [36]
PW R_LED [36]
SYSON
[28,32,35,41]
VR_ON
[32,43]
ACIN
[21,35,36,37,40]

PVT

1
100K_0402_5%

Analog Board ID definition,

Please see page 3.

EC_SI_SPI_SO [31]
EC_SO_SPI_SI [31]
EC_SPICLK [31]
EC_SPICS#/FSEL# [31]

EC_RSMRST# [21]
EC_LID_OUT# [21]
EC_ON
[32]
EC_SW I# [21]
EC_PW ROK [21,32]
BKOFF# [17]
W L_OFF# [28]
ON_0FF_TP LED# [31]
2
BATTERY_LED# [31]

1
100K_0402_5%
1

+3VALW

Compal Secret Data

Security Classification

2
4.7K_0402_5%

PAD T11 @
PAD T16 @

20mil

L19
ECAGND 2
1
FBM-L11-160808-800LMT_0603

1
R184

BATT_TEMP [38]

EC_RCIRRX

D45 KAL90_90+@
CH751H-40PT_SOD323-2

C1598
1000P_0402_50V7K
2 KAL90_90+@

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

XCLK1
XCLK0

1/6 Change version to D3

BEEP#

SPI Device Interface

CIR

68
70
71
72

GND
GND
GND
GND
GND

122
123

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

GPIO

PVT
R485
100_0805_5%
KAL90_90+@

FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PW R_SUSP_LED
NUM_LED#

+3VALW

+3VALW

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW #
EC_GPIOB
EC_GPIOC
EC_PME#

BATT_TEMP
BATT_OVP

11
24
35
94
113

EC_GPIOB
2
4.7K_0402_5%
EC_GPIOC
2
4.7K_0402_5%

63
64
65
66
75
76

PS2 Interface

@ 1
R255
@ 1
R256

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

PWM Output

DA Output

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

PAD T25 @

1
R173
1
R172
2
R171

2 TP_CLK
4.7K_0402_5%
2 TP_DATA
4.7K_0402_5%

1
R186
1
R185
+3VALW

R224
47K_0402_5%

R223
47K_0402_5%

+5VS

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

INVT_PW M
BEEP#

+3VALW +3VALW

21
23
26
27

IN

E51RXD_P80CLK [28]
E51TXD_P80DATA [28]

OUT

C291
0.1U_0402_16V4Z

EC_SCI#

[21]
EC_SCI#
[21] PM_CLKRUN#

KSO[0..17] [31]

ACES_85205-0400
@

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

AD

Place on RAM door

E51RXD_P80CLK
E51TXD_P80DATA

NC

[8,19,26] PLT_RST#

1
47K_0402_5%
1

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

1
2
3
4

1
2
3
4

NC

2
R225

+3VALW

12
13
37
20
38

KSO[0..17]

JP19

[31]

[16] CLK_PCI_LPC

KSI[0..7]

@
2 R253
1
33_0402_5%

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

KSI[0..7]
0.1U_0402_16V4Z

AGND

C316 @
22P_0402_50V8J
2
1

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

69

[20] EC_GA20
[20] EC_KBRST#
[21]
SERIRQ
[20] LPC_FRAME#
[20]
LPC_AD3
[20]
LPC_AD2
[20]
LPC_AD1
[20]
LPC_AD0

LPC_FRAME#

67

9
22
33
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC

@ C304
10P_0402_50V8J
2
1

+3VALW

C260

U9

For EC Tools

C261
1000P_0402_50V7K

2
2
0.1U_0402_16V4Z

C305
1000P_0402_50V7K
1
1

2
2
0.1U_0402_16V4Z

EC_PME#
2
10K_0402_5%

1
R257

C290

C306

ECAGND

+3VALW

L20
1
2 +EC_VCCA
2 FBM-L11-160808-800LMT_0603

0.1U_0402_16V4Z
1
2

0.1U_0402_16V4Z
1 C278
1
C293

Title

EC ENE KB926/CIR
Size
B
Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
1

30

of

45

C302 1

2
0_0603_5%

2 0.1U_0402_16V4Z

U13 & U15 CO-LAY

+SPI_VCC

Reserved for BIOS simulator.Footprint SO8

U13

+3VALW

EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#

R284 1
R249 1

1
3
7
4

To TP/B Conn.

U15

CE#
WP#
HOLD#
VSS

VDD
SCK
SI
SO

8
6
5
2

EC_SPICLK_R

R285 1
R286 1
R248 1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#

EC_SPICLK [30]
EC_SO_SPI_SI [30]
EC_SI_SPI_SO [30]

1
3
7
4

MX25L8005M2C-15G_SOP8

CS#
WP#
HOLD#
GND

JP21

+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI
EC_SI_SPI_SO

8
6
5
2

VCC
SCLK
SI
SO

+5VS
[30]
[30]

@ MX25L512AMC-12G_SO8

ENE suggestion SPI Frequency over 66MHz

SST: 50MHz
MXIC: 70MHz
ST: 40MHz

C244
100P_0402_50V8J

+3VS

G1
G2

27
28

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

[30] ON_0FF_TP SW#

ACES_85201-26051
CONN@

SW2
KALG1@
SMT1-05-A_4P
1

ON_0FF_TP LED#

ON_0FF_TP LED#

KAL90_G0_90+@
SW3
SMT1-05-A_4P
LEFT_BTN# 3
1

(Hall Effect Switch)

PVT

KAL90_G0_90+@
SW4
SMT1-05-A_4P
RIGHT_BTN# 3
1

+3VALW

G1
G2

27
28

0.1U_0402_16V4Z

1
D9

2 LID_SW#
RB751V_SOD323

LID_SW#

JP26
C28

1
2
3
4
5
6
7
8
9
10
GND
GND

10P_0402_50V8J

C220 1

100P_0402_50V8J

KSO7

C214 1

100P_0402_50V8J

KSO12

C219 1

100P_0402_50V8J

KSO6

C213 1

100P_0402_50V8J

KSO5

C212 1

100P_0402_50V8J

KSO4

C211 1

100P_0402_50V8J

KSO3

C210 1

100P_0402_50V8J

KSI0

C225 1

100P_0402_50V8J

KSO11

C218 1

100P_0402_50V8J

KSO10

C217 1

100P_0402_50V8J

KSI1

C226 1

100P_0402_50V8J

KSI4

C229 1

100P_0402_50V8J

KSO2

C209 1

100P_0402_50V8J

KSI2

C227 1

100P_0402_50V8J
KSO1

C208 1

100P_0402_50V8J

KSO9

C216 1

100P_0402_50V8J

KSI3

C228 1

100P_0402_50V8J

KSO0

C207 1

100P_0402_50V8J

KSO8

C215 1

100P_0402_50V8J

KSI5

C230 1

100P_0402_50V8J

KSI6

C231 1

100P_0402_50V8J

KSI7

C232 1

100P_0402_50V8J

FOR EMI
KSI5

+3VS

KSO0
KSI1

WL_BTN#

KSI2

BT_BTN#

KSI3

EMAIL_BTN#

KSI4

IE_BTN#

KSI5

E-KEY_BTN#

KSI5

WL_BTN#

Volume Down

KSI6

BT_BTN#

Volume Up

To Media/B Conn.

PVT

R486
2

100P_0402_50V8J

MINI1_LED#

C195 1

BT_LED#

C194 1

100P_0402_50V8J

100P_0402_50V8J

R491
[30,38]

EC_SMB_DA1

KALH0@
1

[4,30] EC_SMB_DA2

0_0402_5%

KAL90_90+@ 0_0402_5%
1
2

R489
[30,38] EC_SMB_CK1
[32] EC_I2C_INT1
[30]

MC_RST#

KALH0@
1

[4,30] EC_SMB_CK2

1
2
3
4
5
6
7
8
9
10
11
12

KAL90

JP28

Program (KBLG0)
Battery (KALG0)

1
2
3
4
5
6
7
8
GND
GND

1
2
3
4
5
6
7
8
9
10

e-key/B

+5VS
+3VS

MINI1_LED#
KSI1
FB_KSI4
KSO0
KSI2
BT_LED#
FB_KSI3

KSO0
KSI5

JP25 CONN@
1
1
2
2
3
3
4
4
E&T_6905-E04N-00R

PVT

ACES_85201-1005N
CONN@

Back Up

0_0402_5%

KALH0

KAL90_90+@
R475 0_0402_5%
1
2 KSI4
FB_KSI4

+5VS
+3VS

MINI1_LED#
FB_KSI4
BT_LED#
FB_KSI3

KALH0@
R476 0_0402_5%
1
2

NUM_LED#

[30,36]

MEDIA_LED#

[36]

KAL90_90+@
R477 0_0402_5%
1
2 KSI3
FB_KSI3

MC_RST#

2
@ R492
0_0402_5%

MEDIA_CK
MEDIA_DA
MC_RST+#

R493 @
10K_0402_5%
1

C1600 @
0.1U_0402_16V4Z

1
2
3
4
5
6
7
8
9
10
GND
GND

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
GND
GND

1
2
3
4
5
6
7
8
9
10
11
12

KALG1
KSO4
KSO2
KSO3
KSI5
KSI6
BATTERY_LED#
BT_LED#
MINI1_LED#

KALH0@
R478 0_0402_5%
1
2

2008/11/10

+5VS

BATTERY_LED# [30]
BT_LED# [30]
MINI1_LED# [28]

ACES_85201-1005N
CONN@

ACES_85201-08051
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

JP29
PVT

JP22

KAL90_90+@ 0_0402_5%
1
2

+3VALW

[email protected]
GRATIS - FOR FREE

+5VS+3VSMCVCC

@
C193 1

CONN@
ACES_85201-08051

R488
R129
10K_0402_5%
1
2
@

KSO3

1
R479
1
R480

KSO13

KSO2

KSO4

2
KALH0@ 0_0603_5%
2
KAL90_90+@ 0_0603_5%

100P_0402_50V8J

[30]

R481
1

100P_0402_50V8J

SW6 KALH0@
SMT1-05-A_4P
1

FN/B
3

0_0603_5%
2

C224 1

100P_0402_50V8J

RIGHT_BTN# 3

R31
47K_0402_5%

C223 1

KSO17

100P_0402_50V8J

SW5 KALH0@
SMT1-05-A_4P
1

GND
KSO16
2

To BTN/B Conn.
C221 1

KALH0 TP SW
LEFT_BTN#

U2
A3212ELHLT-T_SOT23W-3

C222 1

[30]

M/B TP SW

OUTPUT

KSO14

D22
@
PSOT24C_SOT23

0.1U_0402_16V4Z
LED9
KALG1@

Lid Switch

ACES_85201-26051
CONN@

KSO15

TP_DATA
C192

HT-121UD_AMBER

C27

(Right)

R226
1.5K_0402_5%
KALG1@

5
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

TP_CLK

5
6

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

CONN@

5
6

(Left)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

ACES_85201-0605

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

ON_0FF_TP SW#

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

JP23

(Left)

PVT

R227
47K_0402_5%
KALG1@

VDD

KALH0
INT_KBD

JP30

C237
100P_0402_50V8J

8
7

[30]

PVT

INT_KBD

8
7

5
6

KSO[0..17]

+5VS

KSO[0..17]

6
5
4
3
2
1

+5VS

[30]
1

KSI[0..7]

KSI[0..7]

6
5
4
3
2
1

TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

TP_CLK
TP_DATA

[30] EC_SPICS#/FSEL#

5
6

1
R250

+3VALW

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

BIOS, I/O Port & K/B Connector

Size
C
Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet

31

of

45

2
@

10K_0603_5%
2
10K_0603_5%

+3VALW

2
R258
ON/OFFBTN#

[30]

51ON#

[37]

D1
1
@
C1
100P_0402_50V8J
EMI Reserve 2

1
RLZ20A_LL34
PVT

R506
KAL90_90+@
510K_0402_5%

MCVCC +3VS

R507
KAL90_90+@
10K_0402_5%
1

Power ON Circuit

PVT

R508
KALH0@
10K_0402_5%
D
Q44
KAL90_90+@
S 2N7002_SOT23

2
G

+3VALW

+3VALW

Q43
KAL90_90+@
S 2N7002_SOT23

2
G

[31] EC_I2C_INT1

+3VS

2N7002_SOT23
10K_0402_5%

MCVCC

PJSOT24C_3P_C/A_SOT-23

D29

R194

2
G
Q25

EC_ON

[30]

EC_ON

C317
1000P_0402_50V7K

1/8
D

51ON#

5
6

DAN202UT106_SC70-3

ON/OFF

51ON#

2
1

D27
ON/OFFBTN#

100K_0402_5%
SW1
SMT1-05-A_4P
3
1

D58 USE
PJSOT24C 3P C/A SOT-23
SCA00000E00
24V

Bottom Side

1
R335

Power Button

TOP Side
R114

C277
1U_0603_10V6K
@

14

SYS_PWROK

1
R202 @

2
0_0402_5%

EC_PWROK [21,30]

R509
D46 @
1SS355_SOD323-2
2

For South Bridge

1

1
+3VS

10K_0402_5%
@

EC_I2C_INT2 [30]

2
R510
0_0402_5%

+3VALW

+3VALW

CH751H-40PT_SOD323-2

+3VALW

P
1

U8B
SN74LVC14APWLE_TSSOP14

VR_ON

U8A
SN74LVC14APWLE_TSSOP14

[30,43]

D25 @

14

R201
@
180K_0402_5%

14

U8D
SN74LVC14APWLE_TSSOP14
O

VS_ON

HDA MDC Conn.

[41]

For +VCCP/+1.05VS

+3V

15mil

JMDC1
3

[20] HDA_SDOUT_MDC
[20] HDA_SYNC_MDC
[20] HDA_SDIN1
[20] HDA_RST_MDC#

2
R332

HDA_SDIN1_MDC
33_0402_5%

1
3
5
7
9
11

1
3
5
7
9
11

2
4
6
8
10
12

2
4
6
8
10
12

+MDC_VCC

1
R333

2
0_0402_5% @

+3V

1
R331

2
0_0402_5%

+1.5V

+3V

C369
1U_0603_10V4Z

HDA_BITCLK_MDC [20]
R334
0_0402_5%
2

ACES_88018-124N
CONN@

2
G
Q19
2N7002_SOT23

SUSP

C268
0.1U_0402_16V7K
3

[35,42]

SUSP

U8C
SN74LVC14APWLE_TSSOP14

P
5

[28,30,35,41] SUSP#

R222
10K_0402_1%
1
2

14

R192
@
10K_0402_1%

S4

DDR3

+3VALW

1
1

P
1

[41] 1.5VPGOOD

+3VALW

11

10

D24
1
2 CH751H-40PT_SOD323-2

@
R197 0_0402_5%

1
2
R196 0_0402_5%

[21,30] PM_SLP_S4#

2
G

Q18
2N7002W-T/R7_SOT323-3

For EMI

POWER OK

Time delay 1RC Time

DDR3_SM_PWROK [8]

For South Bridge

C276
2 0.1U_0603_25V7K

2
@
R19810K_0402_5%

2008/11/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

22P_0402_50V8J

1.5V
R181
10K_0402_5%

U8E
SN74LVC14APWLE_TSSOP14

[28,30,35,41] SYSON

R200
47K_0402_5%

14

R199 @
0_0402_5%
1
2

C370

+1.5V
2

+3VALW
0.1U_0402_16V4Z
2
C275

Power OK, Reset, MDC

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
E

32

of

45

+VDDA

J8

2
+5VAMP
R264
10K_0402_5%
2

+5VS

C296
1U_0402_6.3V6K
R263
10K_0402_5%

1U_0402_6.3V6K
1
2
R287
1.3K_0402_1%

Q26

2
B

SURR_L

MIC2_R

SURR_R

R298

20K_0402_1%
2
1

DMIC_DATA
DMIC_CLK

R504

1 @
2 0_0402_5%
1
2
R499 KAL90_G0_90+@ 0_0402_5%

Sense Pin

SPDIF

Impedance

SENSE A

HDA_GPIO0
HDA_GPIO3
SENSE_A

2
R300
0_0402_5%
DMIC_DATA 1
2
R497 KAL90_G0_90+@ 0_0402_5%
1
2
R498
KALH0@ 0_0402_5%
PVT
PVT

22
12

2
3
13
34
47

EAPD
1

SPDIF_R

HP_RIGHT

45

[20] HDA_SDOUT_AUDIO

HP_LEFT

46

10

[20] HDA_SYNC_AUDIO
PVT

39
41

SIDE_L

11

[20] HDA_RST_AUDIO#

[30]
[34]

1
C332

AMP_RIGHT

SIDE_R

48
4
7

CD_GND
BITCLK

3
4

PORT-A (PIN 39, 41)

20K

PORT-B (PIN 21, 22)

10K

PORT-C (PIN 23, 24)

5.1K

PORT-D (PIN 35, 36)

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-G (PIN 43, 44)

[email protected]
PORT-H (PIN 45, 46)
5.1K
GRATIS - FOR FREE
A

G1
G2
ACES_88266-02001
CONN@
2

AMP_RIGHT [34]
MIC2_VREFO

HP_LEFT [34]
HP_RIGHT [34]
PVT
PVT

DMIC_CLK_268

1
R483

DMIC_CLK
2
0_0402_5%

R495
2.2K_0402_5%
KALH0@

15mil

43

DMIC_CLK

44

1
R289

2 C321
22P_0402_50V8J

2
1
22_0402_5%

DMIC_DATA

For EMI

R496 @

0_0603_5%

HDA_BITCLK_AUDIO [20]

MIC1_L
MIC1_R
PCBEEP

SDATA_IN
PIN37_VREFO
LINE1_VREFO

RESET#

31
28

MIC1_VREFO_R

32

SPDIFO2
GPIO0/DMIC_CLK MIC2_VREFO
SENSE A
SENSE B
VREF
SPDIFI/EAPD
SPDIFO
GPIO1/DMIC_DATA
DVSS

JDREF
SENSE C
AVSS1
AVSS2

DGND

2
33_0402_5%

HDA_SDIN0 [20]

29

MIC1_VREFO_L
SDATA_OUT

1
R288

37

LINE2_VREFO
SYNC

HDA_SDIN0_AUDIO

10mil

Digital MIC

MIC1_VREFO_L
MIC1_VREFO_R
PVT

30

+3VS
PVT

MIC2_VREFO

40

33
26
42

DMIC_CLK
DMIC_DATA

L44
1

FBMA-11-100505-301T_2P
2 DMIC_CLK_R
DMIC_DATA_R

R19

1
2
3
4

0_0603_5%

2
D2

BOM Option
ALC268
ALC888S-VC

GND

2008/11/10

5
6

C17
220P_0402_50V8J
KAL90_G0_90+@

1
R315

2
0_0805_5%

1
R406

2
0_0805_5%

1
R444

2
0_0805_5%

1
R443

2
0_0805_5%

1
R426

2
0_0805_5%

GNDA

GND

GNDA

Compal Electronics, Inc.

2008/11/24

Deciphered Date

Title

HD Audio Codec ALC888S-VC

Document Number

Rev
0.1

KALG1

Date:

G1
G2

ACES_88266-04001
C16
CONN@
220P_0402_50V8J

2
0_0805_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

1
2
3
4

1
R314

Compal Secret Data

Security Classification
Issued Date

268@
888@

SM05T1G_SOT23-3
@

AGND

SVID=1025
SSID=0260
FOR KALG1 and KALG0.

SM010027780
JP13

10mil

CODEC_VREF

27

ALC888S-VC_LQFP48_7x7

1
2

AMP_LEFT [34]

Codec Signals

39.2K

1
2

10U_0805_10V4Z

SENSE B

JP24
DMIC_DATA_R
DMIC_CLK_R

10K_0402_1%
1
2

C327
MIC1_R

36

LINE1_R

LFE

UMA HDMI
C308

PVT
AMP_LEFT

LINE1_L

CENTER

35

24

CD_R

C320

0.1U_0402_16V4Z

23

CD_L

+1.5VS

MIC2_L

21

ANALOG MIC

L23
MBK1608121YZF_0603
1
2

+1.5VS_DVDD

R299

MIC1_C_L
2
4.7U_0603_6.3V6M
MIC1_C_R
2
4.7U_0603_6.3V6M
MONO_IN

C351

4.75V

4.7U_0805_10V4Z

+3VS

0.1U_0402_16V4Z

39.2K_0402_1%
2
1

[34] LINEIN_PLUG#
[34] MIC_PLUG#

MIC1_R

R313
[34] HP_PLUG#

[34]

G9191-475T1U_SOT23-5 1

16

19
MIC1_L

FRONT_R

20

MIC1_L

C350

PVT

FRONT_L

LINE2-R

18

[34]

SHDN

10U_0805_10V4Z

C344

LINE_R

LINE2-L

15

17

+VDDA

GND

C324

C346

MIC2_C_L
1
2
C1601 KALH0@ 4.7U_0603_6.3V6M
MIC2_C_R
1
2
C1602 KALH0@ 4.7U_0603_6.3V6M
LINE_L
LINE_C_L
1
2
KAL90_G0_90+@ C333
4.7U_0603_6.3V6M
LINE_R
LINE_C_R
1
2
KAL90_G0_90+@ C342
4.7U_0603_6.3V6M

R494 1K_0402_5%
1 INT_MIC_R
KALH0@

LINE_L

14

DVDD

U17

DVDD_IO

2
0.1U_0402_16V4Z

C319

C334
38

25

[34]

C323

0.1U_0402_16V4Z

40mil

0.1U_0402_16V4Z
1
1
C343

C345
10U_0805_10V4Z

[34]

BYP

(output = 300 mA)

40mil

0.1U_0402_16V4Z

+AVDD_HDA

L25 1
2
FBM-11-160808-700T_0603

DMIC_CLK_R 2

D28
CH751H-40PT_SOD323-2

R262
10K_0402_5%

+VDDA

C322

AVDD2

R260

560_0402_5%

AVDD1

U19

1U_0402_6.3V6K

C294
1

SB_SPKR

L24
MBK1608121YZF_0603
1
2

2SC2411K_SOT23
1

[21]

OUT

20mil

+3VS_DVDD

0.1U_0402_16V4Z
E

560_0402_5%

10U_0805_10V4Z

R305

1U_0402_6.3V6K

R261

1
1
L27 1
C352
C355
2
KC FBM-L11-201209-221LMAT_0805
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z

IN

0.01U_0402_16V7K

MONO_IN

20K_0402_1%

L26 1
2
KC FBM-L11-201209-221LMAT_0805

JUMP_43X39

HD Audio Codec

C318
1
2

C295
1

BEEP#

[30]

PVT

60mil

Tuesday, March 24, 2009

G

Sheet

33
H

of

45

+5VAMP

W=40mil
+3VS
1
1

2.2K_0402_5%

+5VAMP
HP_RIGHT

[33]

HP_LEFT

HP_RIGHT
1
C513
HP_LEFT
1
C489

27
1
R460 1

2 100K_0402_5% 24

R463 1

2 100K_0402_5% 21

HP_RIGHT_C 1
4.7U_0805_6.3V6K R459
HP_LEFT_C
1
4.7U_0805_6.3V6K R445

2
2

HP_RIGHT_R
39K_0402_5% HP_LEFT_R

28
2

VOL_AMP

23

2
39K_0402_5%

25
VDD

7
17

15

/AMP EN

LOUT+
LOUTHP_R
HP_L

INR_H
INL_H
SET

19
18

SPKR+
SPKR-

5
6

SPKL+
SPKL-

13
16

HPOUT_R
HPOUT_L

NC
NC

3
14

VSS

12

GND
PGND
PGND
CGND
GND

26
4
20
10
29

S/PDIF Out JACK

LINE Out/Headphone Out
1

1U_0402_6.3V4Z

ROUT+
ROUT-

9
11

2 EC_MUTE
G
Q37
2N7002_SOT23

1
S

C506

2
0.01U_0402_16V7K

CP+
CP-

22

BIAS

EC_MUTE [30]

APA2051QBI-TRG_TQFN28_4X4

C354
2.2U_0805_10V6K

C478
C498

1U_0402_6.3V4Z
1/9
R453
56.2_0603_1%
HPOUT_L 1
HPOUT_L_1 1
2
L37
HPOUT_R 1
HPOUT_R_1 1
2
L36
R442
56.2_0603_1%

D34
PJDLC05_SOT23-3
@

C488

330P_0402_50V7K 330P_0402_50V7K
1
1
HPOUT_L_2
2
FBM-11-160808-700T_0603
HPOUT_R_2
2
FBM-11-160808-700T_0603

JHP1
1
2
6
3

C477
VOL_AMP

INR_A
INL_A

HP_EN

R461
43K_0402_1%

R462
100K_0402_1%

[33]

U24

2.2K_0402_5%

HPF Fc = 154Hz

+5VAMP

PVDD
PVDD

AMP_RIGHT_C
1U_0402_6.3V4Z
AMP_LEFT_C
1U_0402_6.3V4Z

AMP_RIGHT_C-1
1
C505
AMP_LEFT_C-1
1
2
1
C503
C504
0.47U_0603_16V4Z
R458
R470

HVDD

AMP_LEFT

CVDD

[33]

C514
0.47U_0603_16V4Z
1
2

AMP_RIGHT

[33]

C492
C490
0.1U_0402_16V4Z
2
2
4.7U_0805_10V4Z

C491
0.1U_0402_16V4Z
2

SPDIF_PLUG#

Gain= 10dB

[33]

5
4
7
8
10

SPDIF

SPDIF
+5VSPDIF
C499
100P_0402_50V8J

9
2

SINGA_2SJ-E373-T01
CONN@

+5VAMP
+5VAMP

MIC1_VREFO_R
JMIC1

[33]

MIC1_L

MIC1_L_1

R455
75_0603_1%

4
MIC1_R_R

MIC1_L_R

1
C500

Int. Speaker Conn.

220P_0402_50V7K

3
6
2
1
SINGA_2SJ-E351-S01
CONN@

1
C512

(HDA Jack)

2 220P_0402_50V7K

MIC JACK
1

20mil

[33] MIC_PLUG#

1
2
L38
FBM-11-160808-700T_0603

For ESD Protect

3

8
7

MIC1_R

R468
2.2K_0402_5%

20mil

[33]

1
D37
PJDLC05_SOT23-3

+5VSPDIF

R454
2.2K_0402_5%
R456
L39
75_0603_1%
FBM-11-160808-700T_0603
1
2 MIC1_R_1 1
2

Q40A
2N7002DW-T/R7_SOT363-6

6 1

3
S

SPDIF_PLUG#

MIC1_VREFO_L

Q40B
2N7002DW-T/R7_SOT363-6

2
R467
100K_0402_5%

Q41
AO3413_SOT23-3

HP_PLUG# [33]

HP_PLUG#
R466
100K_0402_5%

D35 @
PJDLC05_SOT23-3

JP14

SPKL+
SPKLSPKR+
SPKR-

G1
G2

5
6

kAL90_G0_90+@

JLINE1

LINE_R

[33]

LINE_L

LINE_L_1 1

R457
75_0603_1%
KAL90_G0_90+@

2008/11/10

Issued Date

Deciphered Date

SINGA_2SJ-E351-S03
CONN@

(HDA Jack)

LINE-IN JACK
4

D36 @
PJDLC05_SOT23-3

Compal Electronics, Inc.

Compal Secret Data

Security Classification

3
6
2
1

LINE_L_R

2
L40
FBM-11-160808-700T_0603
KAL90_G0_90+@

[33]

LINEIN_PLUG# 5

PVT
[33] LINEIN_PLUG#
KAL90_G0_90+@
R469
L43
KAL90_G0_90+@
75_0603_1%
FBM-11-160808-700T_0603
LINE_R_1 1
LINE_R_R
1
2
2

KAL90_G0_90+@ C502
220P_0402_50V7K

@2

220P_0402_50V7K
KAL90_G0_90+@ C501

8
7

C41
220P_0402_50V8K

@2

C40
220P_0402_50V8K

C42
1

220P_0402_50V8K

C43
1

220P_0402_50V8K

1
2
3
4

ACES_88266-04001
CONN@

D7 @
SM05T1G_SOT23-3

For ESD

2
1

SM05T1G_SOT23-3

D8 @

1
2
3
4

2008/11/24

Title

Amplifier & Audio Jack

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
E

34

of

45

+3VALW

PVT
R266
100K_0402_5%
@
[32,42]

SUSP

SUSP

R251
100K_0402_5%
1

10U_0805_10V4Z
2
2
1U_0603_10V4Z

R163
470_0603_5%

RTCVREF +5VALW

SBPWR_EN#

S
5VS_GATE

[28,30,32,41] SUSP#

2N7002DW-T/R7_SOT363-6
1

SBPWR_EN#

0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6

C349

R296
10K_0402_5%
2

1 1

R267

Q24B

1
Q14A

470_0603_5%

3V_GATE

2
1
R164
200K_0402_5%

SI4800BDY-T1-E3_SO8

C329

+VSB
3
2
1
1 C330

1U_0603_10V4Z

C341

1
2

SI4800BDY-T1-E3_SO8

C353

+3VS

5
6
7
8

2 SUSP
G
Q27
2N7002_SOT23

+1.5V to +1.5VS

+VSB

2
0.1U_0603_25V7K

1
C390

2
0.1U_0603_25V7K
@

FOR

Q8B
2N7002DW-T/R7_SOT363-6

1.5VS_GATE

2
1
R121
510K_0402_5%

EMI

SUSP

C187

R183
100K_0402_5%

0.1U_0603_25V7K
2
Q8A
2N7002DW-T/R7_SOT363-6

2
G
Q17
S
2N7002_SOT23

[30,41] SBPWR_EN

SUSP

1
C421

2
0.1U_0603_25V7K
@

1
C388

SBPWR_EN#

[22] SBPWR_EN#

40mil width

2
0.1U_0603_25V7K

R182
100K_0402_5%
R119
470_0603_5%

+1.5VS

40mil width
1
C173

10U_0805_10V4Z
2
2
10U_0805_10V4Z

+1.05VS

C179

3
1
1
C186
2 C185
1
10U_0805_10V4Z
2
2
1U_0603_10V4Z
SI4800BDY-T1-E3_SO8

C180
2
0.1U_0603_25V7K

1
C383

5
6
7
8

2
0.1U_0603_25V7K

@
1
C459

2
0.1U_0603_25V7K

C89

1
C189

U6

40mil width

2
0.1U_0603_25V7K

+3VALW

40mil width

+5VALW

+1.5VS
4

+1.5V
+3VS

2N7002DW-T/R7_SOT363-6

R252
100K_0402_5%

3
2
1
1 C347

Q14B
2N7002DW-T/R7_SOT363-6

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

C340

C348

U16

0.1U_0603_25V7K

3 1

5
6
7
8

+3VALW TO +3VS

SYSON

[28,30,32,41] SYSON

+3V

2
10U_0805_10V4Z

Q24A
C356

SUSP

C238

+3VALW

2
2

Q15A
0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6

U18
SUSP

SYSON#
6

2
1

SBPWR_EN#2
1
R316
200K_0402_5%

1
[29,42] SYSON#

470_0603_5%

R162

Q15B
2N7002DW-T/R7_SOT363-6

5VS_GATE

2
1
R161
200K_0402_5%

+VSB

SI4800BDY-T1-E3_SO8

C375

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

C372

3
3
2
1
1 C373

R297
100K_0402_5%

5
6
7
8

+3V

C371
1

Q30
AO3413_SOT23-3

+3VALW

10U_0805_10V4Z

U20

Colay

+5VS

+3VALW TO +3V_SB(ICH8M AUX Power)

+5VALW TO +5VS
+5VALW

+5VALW

H7
H_4P2
@

[21,30,36,37,40]
H14
H_4P2

H8
H_4P2

2N7002_SOT23
Q11
@

2
G

ACIN

H6
H_3P7N
@

H19
H_3P2

R34 @
470_0603_5%

R165 @
470_0603_5%

R113 @
470_0603_5%

D
2 SUSP
G
Q22 @
2N7002_SOT23

1
1

1
1

D
2 SUSP
G
Q10 @
2N7002_SOT23

D
2 SUSP
G
Q4 @
2N7002_SOT23

D
2 SYSON#
G
Q16 @
2N7002_SOT23

1
D

M2.5X3

TOP SIDE

PVT

1
FIDUCIAL_C40M80

[email protected]
GRATIS - FOR FREE
A

+1.5V

2 SYSON#
G
Q9 @
2N7002_SOT23

2008/11/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/11/24

Deciphered Date

Title

DC Interface & Screw Hole

FD1

FD4

FD3

FIDUCIAL_C40M80

FD2

FIDUCIAL_C40M80

R233 @
470_0603_5%

+1.8V

H9
H17
H_10P0X6P0N H_5P5X4P3N
@
@

+0.75VS

MDC
PVT
H11
H24
H_4P7X3P7N H_5P1X4P1N
@
@

+1.05VS

R118 @
470_0603_5%

PVT

H22
H_3P2

H21
H_3P2

H_7P1 H16
H15
H_3P2 H_3P2 H_3P2
@
@
@
@

H23
H_3P2

H25
H_3P2

H18
H_3P2

+1.5VS
H20
H_3P2

H13
H_4P2

H4
H_3P2
@

H5
H_3P2
@

H10
H_3P2
@

H12
H_3P2
@

H1
H_3P2
@

H2
H_3P2
@

H3
H_3P2

R120
2.2M_0402_1%
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FIDUCIAL_C40M80

Date:

Document Number

Rev
0.1

KALG1
Tuesday, March 24, 2009

Sheet
E

35

of

45

Enlightener LED
+5VALW

+5VALW

(BLUE)

+5VALW

R318 330_0402_5%
1
2

+5VALW

R317 866_0402_1%
1
2

2
R1
499_0402_1%
D

R15
1.5K_0402_5%

PVT

KALG1@

KALG1@

PVT

KAL90_G0_90+@
LED10

(BLUE)

2
4

KALG1@
LED11

PW R_LED#
PW R_SUSP_LED#

+5VALW

R320 330_0402_5%
1
2

+5VALW

R319 866_0402_1%
1
2

2
4

Blue

BATT_RED_LED#

BATT_RED_LED# [30]

BATT_Yellow Green_LED#

BATT_Yellow Green_LED#

[30]

AMB
HT-297UD/CB _BLUE/AMB_0603

HT-297UD/CB _BLUE/AMB_0603

Change footprint:LED_HT-297DQ-GQ_4P
2

LED3 KAL90_G0_90+@
HT-191NBQA_BLUE_0603

ACIN#

Compal Footprint
PVT

LED2 KAL90_G0_90+@
HT-191NBQA_BLUE_0603

ACIN#
LED15

KALH0@
UD

LED16

R500 KALH0@
453_0402_1%
1
2 PW R_SUSP_LED#

R502 KALH0@
220_0402_5%
1
2

+5VALW

NB

(AMB)

UD

+5VALW
PW R_LED#

NB

(BLUE)

HT-210UD/NB_AMB/BLUE

KALH0@

R501 KALH0@
453_0402_1%
1
2

R503 KALH0@
220_0402_5%
1
2

PW R_SUSP_LED#

PVT

ON/OFF LED DOWN

(BLUE)

PW R_LED#

LED8 KALG1@
HT-191NBQA_BLUE_0603

HT-210UD/NB_AMB/BLUE

+5VALW

PW R_LED#

R16
KALG1@
392_0402_1%

MEDIA_LED

NUM_LED

+5VS

+5VS

(BLUE)

+5VS

(BLUE)

+5VALW
Q20A
2N7002DW -T/R7_SOT363-6

(BLUE)

R5 KAL90_90+@
453_0402_1%

R7 KALG1@
866_0402_1%

R259
R9 KALG1@
866_0402_1%

PVT

10K_0402_5%

LED5 KAL90_G0_90+@
HT-191NBQA_BLUE_0603

LED6 KAL90_G0_90+@
HT-191NBQA_BLUE_0603

LED7 KAL90_G0_90+@
HT-191NBQA_BLUE_0603

Q20B
2N7002DW -T/R7_SOT363-6
+5VALW

CAPS_LED#

NUM_LED# [30,31]

1
1

NUM_LED#

LED4 KALG1@
HT-191NBQA_BLUE_0603

(BLUE)

[30] PW R_SUSP_LED
MEDIA_LED#

ON/OFF LED RIGHT

PW R_SUSP_LED#

1
2

PVT

R6 KALG1@
866_0402_1%

2
R17
10K_0402_5%
@

PW R_SUSP_LED#

LED12
KAL90_90+@
HT-297UD/CB _BLUE/AMB_0603

PW R_LED

[30]

(AMB)

PW R_LED#

CAPS_LED

R234

CAPS_LED# [30]

PW R_LED#

R4 KALG1@
604_0402_1%

10K_0402_5%

(AMB)
+5VALW

PW R_LED#

MEDIA_LED#

D3

PW R_SUSP_LED#

LED13
KAL90_90+@
HT-297UD/CB _BLUE/AMB_0603

ACIN#

D5

R8 KAL90_90+@
453_0402_1%

CAPS_LED#

NUM_LED#

PW R_SUSP_LED#
D4

FOR EMI
1

ON/OFF LED LEFT

PJMBZ6V8_3P_C/A_SOT-23

PJMBZ6V8_3P_C/A_SOT-23
KAL90_G0_90+@

PJMBZ6V8_3P_C/A_SOT-23
KAL90_G0_90+@

PW R_SUSP_LED#
PW R_LED#

@
C307 1
@
C292 1

100P_0402_50V8J

100P_0402_50V8J

LED1 KALG1@
HT-191NBQA_BLUE_0603

(BLUE)
+5VALW

PW R_LED#

R3 KALG1@
392_0402_1%
NUM_LED#
CAPS_LED#

+3VS

SATA_LED#

MEDIA_LED#

MEDIA_LED# [31]

100P_0402_50V8J

100P_0402_50V8J

(AMB)
+5VALW

R2 KAL90_90+@
453_0402_1%

Q21
KAL90_G0_90+@
2N7002_SOT23 S

2
G

ACIN

PW R_SUSP_LED#

LED14
KAL90_90+@
HT-297UD/CB _BLUE/AMB_0603

PVT

SATA_LED# 4

ACIN#

100P_0402_50V8J

[21,30,35,37,40]

[20]

5IN1_LED#

[25]

Q35A
2N7002DW -T/R7_SOT363-6

MEDIA_LED#

@
C3
@
C4
@
C2

+3VS

Q35B
2N7002DW -T/R7_SOT363-6

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/11/10

Issued Date

Deciphered Date

2008/11/24

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PWR/B
Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

36

of

45

DC231000500
VIN

PR1
1M_0402_1%
1
2

2DC_IN_S2

VIN

VIN

@ PR2
10K_0402_5%

PVT

RTCVREF

Vin Dectector

Min.
H-->L 16.976V
L-->H 17.430V

PR122
@ 200K_0402_1%
2

PR102
200K_0402_1%

RTCVREF

2
G

PC5
1000P_0402_50V7K

PQ28
@ SI2301BDS-T1-E3_SOT23-3

+3VALWP

PR8
10K_0402_1%
1
2

2
0_0603_5%
@

MCVCC
PQ25
@ SI2301BDS-T1-E3_SOT23-3

PR6
20K_0402_1%

PR123
1

PR5
22K_0402_5%
1
2

PC6
0.1U_0603_25V7K
2
1

PU1A
LM358DT_SO8
PD3
GLZ4.3B_LL34-2

PR7
10K_0402_1%

2 1

P
1
1

[21,30,35,36,40] ACIN

PR4
0_0402_5%
1
2

PR3
84.5K_0402_1%
PR209
10K_0402_1%

PC1
1000P_0402_50V7K

VS

1
2

1
PC4
100P_0402_50V8J

PC2
100P_0402_50V8J

PC3
1000P_0402_50V7K

PJP3

G
G

PL1
SMB3025500YA_2P
1

DC_IN_S1

@
SINGA_2DC-G756I200

Typ
17.525V
17.901V

Max.
17.728V
18.384V

2
G
D

PQ45
@ 2N7002W -T/R7_SOT323-3
2
SPOK
G

PQ46
2N7002W -T/R7_SOT323-3

RTC Conn

[38,39]

+RTCBATT
+RTCBATT

@
PBJ1
1

ML1220T13RE

VIN
PJ2
PD4
LL4148_LL34-2

+3VALWP

2
@

BATT+

PR11
200_0603_5%
CHGRTCP 1
2

PR10
68_1206_5%

N1

+1.8VP

2
@

+5VALW

+0.75VSP

JUMP_43X118

PC8
0.1U_0603_25V7K

+VSBP

+0.75VS

+1.5VP

+VSB

+1.5V

@ JUMP_43X118

PJ17
1

+1.05VS

+1.5VP

+1.5V

@ JUMP_43X118

1
PR14
200_0603_5%

PU2
G920AT24U_SOT89-3
IN
GND

PC9
10U_0805_10V4Z

N2

+1.05VS

@ JUMP_43X118
4

OUT

PJ16

+1.05VSP

PC10
1U_0805_25V4Z

3.3V

PJ7
1

@ JUMP_43X39

Issued Date

[email protected]
GRATIS - FOR FREE

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PC7
0.22U_0603_25V7K

RTCVREF

+CHGRTC

@ JUMP_43X79

PJ8

+1.8V

PJ5
1

@ JUMP_43X118

PR16
560_0603_5%
1
2

VS

+1.05VSP

PR15
560_0603_5%
1
2

@ JUMP_43X79

PJ6

PR12
100K_0402_1%

[32] 51ON#

+3VALW

PJ4

+5VALWP

PR9
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3

PR13
22K_0402_1%
1
2

PD5
LL4148_LL34-2
2
1

PJ3
1

JUMP_43X118

2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DCIN & DETECTOR & RTC

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

D

Sheet

37

of

45

PH1 under CPU botten side :

CPU thermal protection at 96 degree C
Recovery at 60 degree C
VL
VL
VL
2

VMB
PR17
47K_0402_1%

TM_REF1

SUYIN_250133MR007G115ZL

+
-

LL4148_LL34-2
3

PU3A
LM393DG_SO8

VL

PR25
100K_0402_1%

PR26
1K_0402_1%

PR23
100K_0402_1%
2
1

1
2

PC15
1000P_0402_50V7K

+3VALW P

PR22
15.4K_0402_1%

PR24
6.49K_0402_1%
2
1

PR21
100_0402_1%
1

PR20
100_0402_1%

PC14
0.22U_0603_16V7K

PD6
1

O
4

PQ2
DTC115EUA_SC70-3

PR19
13.7K_0402_1%
1
2

PC13
0.01U_0402_25V7K

PC12
1000P_0402_50V7K

MAINPW ON [20,39]
1

PR18
47K_0402_1%
1
2

PC11
0.1U_0603_25V7K

PH1
100K_0603_1%_TH11-4H104FT
2

EC_SMCA
EC_SMDA

BATT+
1

BATT_S1

1
2
3
4
5
6
7

1
2
3
4
5
6
7

PL2
SMB3025500YA_2P
1
2

PJP2

BATT_TEMP [30]

PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
Recovery at 47 degree C

EC_SMB_CK1 [30]
EC_SMB_DA1 [30]

VL

@ PR27
47K_0402_1%

@ PR28
47K_0402_1%
1
2

PQ3
TP0610K-T1-E3_SOT23-3
@ PH2
100K_0603_1%_TH11-4H104FT

8
O
-

@ PR32
15.4K_0402_1%

PU3B
LM393DG_SO8

@ PC18
0.22U_0603_16V7K

@ PD7
LL4148_LL34-2
2
1

5
TM_REF1

1
2

@ PR30
13.7K_0402_1%
1
2

PC17
0.1U_0603_25V7K

PR31
22K_0402_1%
1
2

VL

VL

+VSBP

1
PR29
100K_0402_1%

PC16
0.22U_1206_25V7K

B+

VL

PQ4
2
G

PR34
0_0402_5%
2

[37,39] SPOK

PC19
0.1U_0402_16V7K

PR33
100K_0402_1%

2N7002W -T/R7_SOT323-3
<BOM Structure>

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

D

Sheet

38

of

46

ISL6237_B+

ISL6237_B+
@
PR35
0_0805_5%
1
2

PJ10

PC28
4.7U_0603_6.3V6M
2
1

PHASE1

16

LGATE1

18

DL5

LGATE2

23

VL

30

OUT2

32

REFIN2

PGND

22

OUT1

10

FB1

11

BYP

SKIP

29

2VREF_ISL6237
1
PC36

LDOREFIN

@ PR44
2

EN1

ILIM1

12

ILM1

27

EN2

ILIM2

31

ILIM2

SPOK

PU4
ISL6237IRZ-T_QFN32_5X5

PC25
2200P_0402_50V7K
2
1

[37,38]
B

PR49
330K_0402_1%

PR53
0_0402_5%

+5VALWP Ipeak=8.444A ; Imax=5.91A

Choke DCRmax=60m ohm, DCRtyp=54m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Iocp=Ilimit+Delta I/2
=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)

2VREF_ISL6237

PC143
1U_0603_10V6K
1
2

21

2
PR51
0_0402_5%
1
2
2

GND

14

PR48
330K_0402_1%
2
1

TON

13

1
1
2

POK1

@ PC39
0.047U_0402_16V7K

PQ35
TP0610K-T1-E3_SOT23-3

EN_LDO

2
1

@ PR55
47K_0402_5%
1
2

PC38
0.047U_0402_16V7-K

[20,38] MAINPWON

28

@ PR50
0_0402_5%

PR52
806K_0603_1%

VL

POK2

2VREF_ISL6237

2
1

PR47
200K_0402_5%
1
2

PC37
0.22U_0603_25V7K

0_0402_5%
1
0_0402_5%
2

NC

PR54
0_0402_5%
2

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

[email protected]
GRATIS - FOR FREE

Deciphered Date

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

REF

NC

20

PR46
100K_0402_1%
1
2

VL

+ PC35
220U_6.3V_M

FB5

PR45
1

PD12
1SS355_SOD323-2

0.22U_0603_10V7K

PD8
GLZ5.1B_LL34-2
1
2

3
2
1

PHASE2

LX5

PQ8
AO4712_SO8

DH5
PR40 2.2_0603_5%
BST5A 2
1

PR41
63.4K_0402_1%

17

PR43
10K_0402_1%
1
2

15

BOOT1

PR39
4.7_1206_5%
2
1

UGATE1

BOOT2

PC29
1U_0603_10V6K
1
2

19

PL4
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1

PC34
680P_0402_50V7K
2
1

UGATE2

24

25

DL3

FB3

3
2
1

26

PVCC

5
6
7
8

7
LDO

3
VCC

VIN

TP

PC27
1U_0603_10V6K
1
2

33

PC32
0.1U_0603_25V7K
LX3

@ PR42
10K_0402_1%

+3.3VALWP Ipeak=8.444A ; Imax=5.91A

Choke DCRmax=60m ohm, DCRtyp=54m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
VS
Iocp=Ilimit+Delta I/2
=10.134A ~ 11.967A
Delta I=1.934A (Freq=300KHz)

+5VALWP

PC31
0.1U_0603_25V7K

1
2
3

PC33
680P_0402_50V7K

DH3
PR37
2
1 BST3A
2.2_0603_5%

PQ6
AO4466_SO8
4

PR38
0_0402_5%

PC30
330U_6.3V_M

PQ7
AO4712_SO8

PR36
4.7_1206_5%

1
1

8
7
6
5

PL3
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

+3VALWP

PC26
0.1U_0603_25V7K

PC24
4.7U_1206_25V6K
2
1

5
6
7
8
8
7
6
5
PQ5
AO4466_SO8
4

VL

1
2
3

PC20
4.7U_1206_25V6K
2
1

PC41
2200P_0402_50V7K
2
1

PC23
4.7U_1206_25V6K
2
1

PC22
2200P_0402_50V7K
2
1

PC21
4.7U_1206_25V6K
2
1

JUMP_43X118
@ PC92
2200P_0402_50V7K
2
1

B+

Title

+5VALWP/+3VALWP
Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

39

of

46

ACSET

PR67
340K_0402_1%

ACOP

OVPSET

AGND

DL_CHG

LODRV

23

PGND

22

LEARN

21

CELLS

20

CELLS

1
2
1

PC55
P
C55
680P_0402_50V7K

PC57
0.1U_0402_16V7K
1
2
ACOFF

RTCVREF

11

SRP

19

SE_CHG+

SRN

18

SE_CHG-

BAT

17

TP

29

VADJ

ACGOOD

14

BATDRV

SRSET

IADAPT

16

SRSET

15

PR72
10_0603_5%
1
2

2
1
3

24751_VREF

PC144
1000P_0402_50V7K

PR81
100K_0402_1%

[30] FSTCHG

2N7002W -T/R7_SOT323-3
<BOM Structure>

PR86
49.9K_0402_1%
2

2N7002W -T/R7_SOT323-3
<BOM Structure>

PQ18
2
G

2
1

CHGEN#

@ PR177
4.3K_0402_5%

PQ19
2
G

2
G

PR82
100K_0402_1%

@ PQ16
2N7002W -T/R7_SOT323-3

VADJ

[21,30,35,36,37]

2N7002W -T/R7_SOT323-3

PR80
0_0402_5%
1

PQ17
SI2301BDS-T1-E3_SOT23-3
2N7002W -T/R7_SOT323-3
REGN

ACGOOD#
2

ACIN

1
PR78
887K_0402_1%

PR84
221K_0402_1%
2
1

PQ36
2
G

24751_VREF
2

PQ15_GATE

@ PR176
0_0402_5%
1

[30]

[30] CALIBRATE#
4

PQ20
2
G

2
1

PR180
200K_0402_1%
2
1
1

PQ37
2
G

PC163
0.1U_0402_16V7K
ACOFF 1
2

ADP_I

ACSET

PC66
0.01U_0402_25V7K

2
2
PR83
64.9K_0402_1%
24751_VREF 1
2

PR79
105K_0402_1%

24751_VREF

@ PR75
100K_0402_1%

24751_VREF

PR179
100K_0402_1%
2
1

PR76
499K_0402_1%

PR181
340K_0402_1%
2
1

@PC63
@PC63
0.01U_0402_25V7K

IREF=0.7748*Icharge

PR73
100K_0402_1%

[30] BATT_OVP

PU1B
LM358DT_SO8
7 0

PR77
10K_0402_1%
1
2

24751_VREF

Per cell=4.5V

IREF [30]

For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A

For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
Icharge=(Vsrset/Vdac)*(0.1/PR62)
IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge

2
2

BATT-OVP=0.1112*VMB

PC64
100P_0402_50V8J

LI-3S :13.5V----BATT-OVP=1.5012V

PC65
0.01U_0402_25V7K

BATT-OVP=0.1112*VMB

PR71
17.4K_0402_1%
2
1

BQ24751ARHDR_QFN28_5X5

PR74
340K_0402_1%

VS

Icharge Setting

ICHG setting

/BATDRV

13

VMB

LI-4S :18.0V----BATT-OVP=2.001V

PC61
0.1U_0603_25V7K

ACGOOD#

CP POINT=(1.434V/3.3V)*(0.1/0.015)=2.896A

12

VADJ

ACSET

Vacset=3.3*(49.9K/(49.9K+64.9K))=1.434V

VDAC

PR70
100K_0402_1%

PC62
0.1U_0603_25V7K

65W adapter

65W /90W #

@PC59
@PC59
0.1U_0603_25V7K

PC58
0.1U_0603_25V7K

VREF

PC60
1U_0603_10V6K

CP point=Iadapter*85%

@ PR85
100K_0402_1%

[30]
1

24751_VREF 10

PR69
100K_0402_1%
1
2PQ15_GATE
2

CP Point Setting

[30]

PQ13
AO4466_SO8

24751_VREF
PQ15
SI2301BDS-T1-E3_SOT23-3

Fsw : 300KHz

BATT+

3
<BOM Structure>

2
PC54
1U_0603_10V6K

PR68
54.9K_0402_1%

Input UVP : 17.26V

[30]

Cells selector

Input OVP : 22.3V

PR62 0.02_1206_1%
4

OVPSET

@ PQ14
2N7002W -T/R7_SOT323-3
2
3S/4S#
G

@ PR64
4.7_1206_5%

24
1

PC56
0.47U_0603_16V7K
1
2
7

PR66
0_0402_5%
1
2

1
1

REGN

CELLS

ACSET

PL5
10UH_PCMB104T-100MS_6A_20%
1
2

LL4148_LL34-2
PC51
0.1U_0603_25V7K

REGN

PR63
54.9K_0402_1%

4 Cell

3 Cell

VREF

LX_CHG
PD10
2

25

PC53
10U_1206_25V6M

PH

ACDRV
ACDET

4
5

ACDRV
ACDET

3
2
1

DH_CHG
5
6
7
8

26

PC52
10U_1206_25V6M

HIDRV

ACN
ACP

/BATDRV

PQ11
AO4466_SO8

PQ12
AO4407A_SO8

3
2
1

2
3

PR57
100K_0402_1%

ACN
ACP

PC40
0.01U_0402_25V7K

PR61
0_0603_5%
1
2

BTST

PC44
2200P_0402_25V7K

27

BTST

@PC49
@PC49
0.1U_0603_25V7K

PC43
4.7U_1206_25V6K

PC48
0.1U_0603_25V7K
1
2

PVCC

5
6
7
8

28

2
@ PR65
47K_0402_1%

GND

CHG_B+

CHGEN

1
PC47
0.1U_0603_25V7K

2
2
1
2

CELLS

PVCC

PU5
1

1
2

PC46
0.1U_0402_16V7K
1
2

Place close to back to back MOS

24751_VREF

JUMP_43X118

PR60
340K_0402_1%
PC50
2.2U_0805_25V6K

PJ11
2
CHGEN#

PR59
100K_0402_1%

PC45
0.01U_0402_25V7K

PR174
3.3_1210_5%

PR56
1
0.015_1206_1%

PC42
4.7U_1206_25V6K

8
7
6
5

2
1

1
2
3

5
6
7
8

1
2
3

8
7
6
5

PR58
3.3_1210_5%

B+

PQ10
AO4407A_SO8

VIN

3
2
1

PQ9
AO4407A_SO8

2N7002W -T/R7_SOT323-3
@

CP setting

Charger ADJ

PR78

PR84

4.0V

Calibrate#
L

4.1V

887K

221K

4.2V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

KALG1

Date:

CHARGER

Tuesday, March 24, 2009

D

Sheet

40

of

46

Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+2.28/2= 11.04A

PJ9
1.05V_IN

PR526
0_0402_5%
1
2

1.05V_EN
1

PU503
TPS51117RGYR_QFN14_3.5x3.5

PC541
4.7U_0805_10V6K

PR531
13.7K_0402_1%
1
2

PR112
0_0402_5%
1
2

[32] VS_ON

PC538
10U_0805_6.3V6M

LG_1.05V

DRVL

PGND
8

GND
7

PC540
@ 47P_0402_50V8J
1
2

TP

VBST

10

PQ508
+5VS

+1.05VSP

PC537
330U_D2E_2.5VM

PGOOD

V5DRV

1.05V_TRIP
1
2
PR530
5.9K_0402_1%

PR528
4.7_1206_5%

SW _1.05V

1.05V_SNB2

VFB

12
11

LL
TRIP

1.05V_FB

UG_1.05V

PC542
680P_0603_50V7K

V5FILT

13

5
6
7
8

VOUT

DRVH

3
2
1

3
1.05V_V5FILT

14

15

1
TON

EN_PSV

AO4456_SO8

PL502
1UH_PCMC063T-1R0MN_11A_20%
1
2

1
PC539
1U_0603_10V6K

1.05V_EN

@ PR178
0_0402_5%
1
2

[30,35] SBPWR_EN

PC536
0.1U_0402_16V7K
@

PR529
422_0603_1%
1
2

+5VS

PQ507
AO4466_SO8

0.1U_0603_25V7K

PR910
30K_0402_5%

[30,32,35] SUSP#

PR527
PC535
0_0603_5%
BST_1.05V 1
2BST_1.05V-1
1
2

B+

3
2
1

2
1
PC534
10U_1206_25V6M

1.05V_TON

12/25

@ JUMP_43X118

5
6
7
8
PR525
300K_0402_5%
1
2

VFB=0.75V

PR532
33.2K_0402_1%

12/25

PJ12
1.5V_IN
2
1
PC501
10U_1206_25V6M

PQ501
AO4466_SO8

PR523
22.1K_0402_1%
1
2

PU501
TPS51117RGYR_QFN14_3.5x3.5

PC531
4.7U_0805_10V6K
PQ506

AO4456_SO8

1.5VPGOOD [32]

1
2

LG_1.5V

+
2

PC528
10U_0805_6.3V6M

DRVL

PGND
8

PGOOD

PR909
100K_0402_1%
1
2
+1.5VP

GND

PC530
@ 47P_0402_50V8J
1
2

PC527
330U_D2E_2.5VM

10

+5VALW

1.5V_SNB 2

V5DRV

1.5V_TRIP
1
2
PR522
5.9K_0402_1%

PR520
4.7_1206_5%

14

15

VBST

SW _1.5V

VFB

12
11

LL
TRIP

+1.5VP

PC532
680P_0603_50V7K

1.5V_FB

UG_1.5V
5
6
7
8

V5FILT

13

3
2
1

VOUT

DRVH

3
1.5V_V5FILT

6
2

PC529
1U_0603_10V6K

B+

PL501
1UH_PCMC063T-1R0MN_11A_20%
1
2

TON

TP

PR521
422_0603_1%
1
2

EN_PSV

PC526
@0.1U_0402_16V7K

2
+5VALW

0.1U_0603_25V7K

PR911
30K_0402_5%

3
2
1

1.5V_EN

12/25

PR519
PC525
0_0603_5%
BST_1.5V 1
2BST_1.5V-1
1
2

[30,32,35] SYSON

PR518
0_0402_5%
1
2

@ JUMP_43X118

5
6
7
8
PR501
300K_0402_5%
1
2

1.5V_TON

12/25
PR524
22.1K_0402_1%

VFB=0.75V
Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+2.28/2= 11.04A

12/25
4

Issued Date

[email protected]
GRATIS - FOR FREE
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.8VP / 1.05VSP
Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

D

Sheet

41

of

46

PJ609
@ JUMP_43X79

+3VALW

VIN

GND

NC

VREF

NC

VOUT

NC

TP

2
2
LDO_1.8V_REF

PR628
1.24K_0402_1%

PC627
0.1U_0402_16V7K

+1.8VP

PC631
@ 0.1U_0402_16V7K

APL5331KAC-TRL_SO8

1
1

PR626
0_0402_5%
2LDO_1.8V_EN
2
G

PC624
1U_0603_6.3V6M

SYSON#

[29,35]

+5VALW

VCNTL

PR623
1K_0402_1%

PC623
4.7U_0805_6.3V6K

<BOM Structure>
6

PU604
LDO_1.8V_IN

PC629
10U_0805_6.3V6M

PQ609
2N7002W -T/R7_SOT323-3

PJ14
JUMP_43X79

+1.5V

NC

REFEN

NC

VOUT

NC

GND

+3VALW
1

VCNTL

GND

PR118
1K_0402_1%

PC99
4.7U_0603_6.3V6M

VIN

2
1

PU8
1

PC100
1U_0402_6.3V6K

RT9173DPSP_SO8

+0.75VSP
2

PR120
2N7002W -T/R7_SOT323-3
<BOM Structure>
1K_0402_1%

PC101
0.1U_0402_16V7K
2
1

PC103
0.1U_0402_16V7K

[32,35] SUSP

PQ27
2
G

PR119
0_0402_5%
1
2

PC104
10U_0805_6.3V6M

12/25

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.8VP/+0.75VSP
Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

42

of

46

+5VS

UGATE2

UGATE_CPU2-1

BOOT2

26

NC

25

BOOT_CPU2
1
2
1
2
PR152
2.2_0603_5%
PC127
0.22U_0603_10V7K

3
2
1

PC116
1000P_0603_50V7K
2
1

PC114
2200P_0402_50V7K
2
1

PC113
10U_1206_25V6M
2
1

PR144
10K_0402_1%
2
1

PC120
680P_0402_50V7K

PR142
6.8_1206_5%
1 2
1

3
2
1

24

PR156
1_0402_5%
@ PR159
0_0603_5%
1
2

VSUM
1

PC132
0.22U_0603_10V7K
VCC_PRM
ISEN2
B

1
PR168
2.61K_0402_1%

PR173 3.83K +-1% 0402

2
PH3
10KB_0603_5%_ERTJ1VR103J
1

PC139 180P_0402_50V8J
1
2

PR172 1K_0402_1%

PR170
20_0402_5%

CPU_B+

VSUM
PC138
0.01U_0603_50V7K

PR171
11K_0402_1%
2
1

PR169
0_0402_5%
1
2

VSSSENSE

+5VS

LGATE_CPU2

820P_0402_50V7K
2

@PC137
@PC137
0.022U_0603_50V7K

[5]

PC136
1

ISEN1
ISEN2
2
1_0603_5%

PC135
0.1U_0603_25V7K

+CPU_CORE

PR167
20_0402_5%
1
2

PQ34
AO4456_SO8

VCC_PRM
CPU_B+

PL11
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

SI7686DP-T1-E3_SO8

PC131
1U_0402_6.3V6K

VCCSENSE

[5]

1
2
PR165
1K_0402_1%
PR166
0_0402_5%
1
2

PQ32

PQ33
AO4456_SO8
4

PC121
0.22U_0603_10V7K
ISEN1

PHASE_CPU2

PR145
1_0402_5%

28
27

PR121
0_0603_5%
1 U_CPU2-1

+CPU_CORE

PC117
1000P_0603_50V7K
2
1

PHASE2

PR164
10_0603_5%
1
2

PC134 1000P_0402_50V7K
1
2

3
2
1

2
2

PC115
220U_25V_M
2

@ PR146
0_0603_5%
1
2

PR155
10K_0402_1%
2
1

29

PC122
10U_1206_25V6M
2
1

PGND2

VSUM

PR157
3.65K_0805_1%
2
1

LGATE2

LGATE_CPU2

PC129
PR154
680P_0402_50V7K
6.8_1206_5%
2
1 2
1

31
30

3
2
1

PVCC

LGATE_CPU1

LGATE_CPU1

32

5
6
7
8

LGATE1

PHASE_CPU1

LGATE_CPU2

PR163
255_0402_1%
1
2

5
6
7
8
PGND1

33

UGATE_CPU1
3
2
1

34

PQ31
AO4456_SO8

5
6
7
8

35

PHASE1

LGATE_CPU1

38

37
UGATE1

1
+

PL10
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

PHASE_CPU1

PQ30
AO4456_SO8

1
PR158

220P_0402_50V7K
1
2

PQ29
SI7686DP-T1-E3_SO8

3
2
1

PR138
PC119
2.2_0603_5%
0.22U_0603_10V7K
BOOT_CPU1 1
2 1
2

36

ISEN2
23

GND

VDD
22

21

FB2

VIN

12

20

FB
VSUM

COMP

1
2
@ PR161
0_0402_5%
PR162
1K_0402_1%
2
1

PC133

PR107
0_0603_5%
1 U_CPU1

5
6
7
8

UGATE_CPU1 2

VID0

40

41

42

39

VID1

VID2

VID3

VID4

VID5

44

43

46

45
DPRSLPVR

47
CLK_EN#

VW

11

PC112
10U_1206_25V6M
2
1

1
[5]

PC128 1000P_0402_50V7K
PR160 97.6K_0402_1% PC130 470P_0402_50V7K
1
2
2
1

1
PC109
0.022U_0402_16V7K

PC110
2.2U_0603_6.3V6K

PC124
2200P_0402_50V7K
2
1

[5]

PL9
FBMA-L18-453215-900LMA90T_1812
2
1

PR143
3.65K_0805_1%
2
1

CPU_VID1

PR125
1_0603_5%

PC123
10U_1206_25V6M
2
1

[5]

B+

CPU_B+

[5]

CPU_VID2

BOOT1

ISEN1

OCSET

49
SOFT

10

6.81K_0402_1%
2

PU10
ISL6266AHRZ-T_QFN48_7X7

8
9

13K_0402_1%
1
2

1
1000P_0402_50V7K
PR153
1

NTC

19

PC126

13

PR151

VR_TT#

VO

PC125
0.022U_0603_25V7K
1
2

RBIAS

DFB

18

VR_TT#

PMON

17

PR149
147K_0402_1%
2

PSI#

DROOP

0_0402_5%

DPRSTP#

20_0402_5%

16

1@ PR148

PGOOD

RTN

PR147
1

PSI#

VSEN

[5]

[5]

CPU_VID3

2
1
PR129 0_0402_5%
2
1
PR135 0_0402_5%
2
1
PR136 0_0402_5%
2
1
PR137 0_0402_5%
2
1
PR130 0_0402_5%
2
1
PR131 0_0402_5%
2
1
PR132 0_0402_5%
2
1
PR133 0_0402_5%

PC118
1U_0402_6.3V6K
2
1

PR140
1.91K_0402_1%
2
1

2
1
[8,16,21] VGATE

GND

+3VS
+3VS

0_0402_5%
2

15

PR134
1

14

[16] CLK_ENABLE#

PGD_IN

CPU_VID4

CPU_VID0

0_0402_5%
2

VID6

PR128
1

0_0402_5%
2

48

[5,8,20] H_DPRSTP#

[30]

[5]

PR127
1

VR_ON

[8,21] PM_DPRSLPVR

PR139
499_0402_1%

CPU_VID5

PR126
499_0402_1%
1
2

3V3

[5]

VR_ON

VDIFF

[30,32]

CPU_VID6

VCC_PRM
PC140
0.1U_0402_16V7K
1
2

PC141

1
0.22U_0402_6.3V6K
A

2
PC142
0.22U_0603_10V7K

2007/09/20

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+CPU_CORE
Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

43

of

46

Version change list (P.I.R. List)

Item
1
2

Reason for change

Rev.

Date

Modify 1.5V and 1.05V choke to cyntec for eff.

PL501 & PL502

Change PR525 & PR501 from 240K to 300K

Change PR138 and PR158 to 2.2 OHM

Change PR530 & PR522 to 5.9K

Modify 1.5V & 1.05V OCP to 14A

Modify 3V & 5V choke to 4.7UH for eff.

Change PL3 & PL4 from 8.2UH to 4.7UH

Modify 5V output cap to OS-CON for costdown

Change PC35

Modify 3V output cap to OS-CON for costdown

Change PC30

Modify dischager mos to

Change PQ12

Phase

Change PQ506 & PQ508 from FDS6670 to A04456

Add CPU_core boost resister for EMI request

Modify List
Change PR37 and PR40 to 2.2 OHM

Modify 1.5V and 1.05V low side mos for eff.

PG#

Add 3/5V boost resister for EMI request

Modify 1.5V and 1.05V frequnce from 336K to 264K for eff.

Page 1 of 2
for PWR

Fixed Issue

AO4407A for rating risk

Add 30K OHM to TPS51117 EN pin , Disable SMPS mode

10

ADD PR910 & PR911

11
12
13
14
B

15

16
17
18
19
20
21
22
A

23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR)
Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

44

of

46

2008/03/28

Issued Date

[email protected]
GRATIS - FOR FREE
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

HW PIR
Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

45

of

45

PCB
ZZZ

LA-5271P MB Rev0: DA60000C500

D

PCB 08Y LA-5271P REV0 M/B

North Bridge
U21
PVT

GL40

GL40: SA00002Q8N0

S IC AC82GL40 SLGGM A1 FCBGA1329 GL ABO

GL40@

2
R7
150_0402_1%
KAL90_90+@

R6
453_0402_1%
KAL90_90+@

MEDIA_LED NUM_LED CAPS_LED

R9
150_0402_1%
KAL90_90+@

RIGHT
R4
220_0402_5%
KAL90_90+@

R3
220_0402_5%
KAL90_90+@

DOWN
R16
220_0402_5%
KAL90_90+@

LEFT

ON/OFF LED Risiter

Enlightener LED

R15
300_0402_5%
KAL90_90+@
Page 36

R1
300_0402_5%
KAL90_90+@

LED11
KAL90_90+@

LED11
KALH0@

YG

YG

HT-297DQ-GQ_AMB-YG

HT-297DQ-GQ_AMB-YG

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/08/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Option Component
Size
Document Number
Custom

Rev
0.1

KALG1

Date:

Tuesday, March 24, 2009

Sheet
1

46

of

46