UNIVERSIDAD NACIONAL MAYOR DE SAN MARCOS

FACULTAD DE INGENIERA ELECTRONICA Y

ELECTRICA

DISEO DIGITAL

ING. Alfredo Granados Ly

Informe 4: Estilo Estructural

Quispe Orosco, Emerson Kleem 10190027











UNIVERSIDAD NACIONAL MAYOR DE SAN MARCOS
(Universidad del Per, DECANA DE AMERICA)
FACULTAD DE INGENIERIA ELECTRONICA Y ELECTRICA

LABORATORIO DE DISEO DIGITAL
ING. ALFREDO GRANADOS LY

1. Escribir el cdigo de los siguientes circuitos

1-a
library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ckto1 is
port(gn,rclk,srclrn,srclk,ser: in std_logic;
q: out std_logic_vector(8 downto 1);
qhn:out std_logic);
end ckto1;

architecture solucion of ckto1 is
signal y:std_logic_vector(8 downto 1);
signal x:std_logic_vector(8 downto 1);
signal w:std_logic;
begin
U0:
process(srclrn,srclk,ser)
begin
if srclrn='0' then
x(1)<='0';
elsif srclk='1' and srclk'event then
x(1)<=ser;
end if;
end process;

U1: for j in 2 to 8 generate
process(srclrn,srclk,ser)
begin
if srclrn='0' then
x(j)<=x(j-1);
elsif srclk='1' and srclk'event then
x(j)<=x(j-1);
end if;
end process;
end generate;

U2:
process(rclk,x(1),y(1))
begin
if rclk='1' and rclk'event then
y(1)<=x(1);
end if;
end process;

U3: for i in 2 to 8 generate
process(rclk,x(i),y(i))
begin
if rclk='1' and rclk'event then
y(i)<=x(i);
end if;
end process;
end generate;

q<=y when w='1' else "ZZZZZZZZ";

w<=not gn;

qhn<=x(8);

end solucion;
















2-a



library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ckt2 is
port(oen,ld,ser,clrn,clk: in std_logic;
d: in std_logic_vector(4 downto 1);
q: out std_logic_vector(4 downto 1);
q4b:out std_logic);
end ckt2;

architecture solucion of ckt2 is
signal w,t:std_logic;
signal x:std_logic_vector(4 downto 1);
signal y:std_logic_vector(4 downto 1);
begin

U0: for j in 1 to 4 generate

process (clrn,x(j),clk)
begin
if clrn='0' then
y(j)<='0';
elsif clk='0' and clk'event then
y(j)<=x(j);
end if;

end process;

end generate;


U1: for i in 2 to 4 generate

x(i)<=(ld and d(i)) or (y(i-1) and (not ld));

end generate;

x(1)<=(ld and d(1)) or (ser and (not ld));

q<=y when w='1' else "ZZZZ";

w<=not oen;

q4b<=y(4);

end solucion;



3-a




library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ckt3 is
port(A1: in std_logic_vector(4 downto 1);
A2: in std_logic_vector(4 downto 1);
g1,g2: in std_logic;
Y1,Y2:out std_logic_vector(4 downto 1));
end ckt3;

architecture solucion of ckt3 is
signal w1,w2:std_logic;
signal x1,x2:std_logic_vector(4 downto 1);
begin

U0: for i in 1 to 4 generate

x1(i)<=not A1(i);
x2(i)<=not A2(i);

end generate;

Y1<=x1 when w1='1' else "ZZZZ";

Y2<=x2 when w2='1' else "ZZZZ";

w1<=not g1;
w2<=not g2;

end solucion;























4-a




library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ckt4 is
port(oen:in std_logic_vector(3 downto 1);
d:in std_logic_vector(8 downto 1);
clrn,pren,ena: in std_logic;
q: out std_logic_vector(8 downto 1));
end ckt4;

architecture solucion of ckt4 is
signal x,w:std_logic;
signal y:std_logic_vector(8 downto 1);
signal z:std_logic_vector(8 downto 1);

begin

U0: for i in 1 to 8 generate

y(i)<=(not pren) or (d(i) nor (not clrn));

process(x,y(i))
begin

if x='1' then
z(i)<=y(i);
end if;
end process;
end generate;

q<=z when w='1' else "ZZZZZZZZ";

w<=(not oen(1)) and (not oen(2)) and (not oen(3));

x<= ena or (not clrn) or (not pren);

end solucion;


2. Utilizando la biblioteca :lpm_component disee un circuito que permita escribir un dato en
una memoria

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library lpm;
use lpm.lpm_components.all;

Entity memoria is

PORT( RESET: in std_logic;
clockLW: in std_logic;
LWenable: in std_logic;
FULL: out std_logic;
entrada: in std_logic_vector(7 downto 0);
salida: out std_logic_vector(7 downto 0) );

end memoria;

architecture solucion of memoria is

component LPM_RAM_DP
generic (LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : string := UNUSED;
LPM_TYPE : string := L_RAM_DP;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string;
LPM_HINT : string := UNUSED);
port ( DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDCLOCK : in std_logic := '0';
WRCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
WRCLKEN : in std_logic := '1';
RDEN : in std_logic;
WREN : in std_logic;
Q : out std_logic_vector(LPM_WIDTHAD-1 downto 0));
end component;

signal direccion: std_logic_vector(7 downto 0);
signal leer,escribir: std_logic;
signal clockenable: std_logic;

begin
U0: LPM_RAM_DP generic map( LPM_WIDTH=>8,
LPM_WIDTHAD=>8,
LPM_FILE=>"UNREGISTERED")
port map( DATA=>entrada,
RDADDRESS=>direccion,
WRADDRESS=>direccion,
RDCLOCK=>clockLW,
WRCLOCK=>clockLW,
RDCLKEN=>clockenable,
WRCLKEN=>clockenable,
RDEN=>leer,
WREN=>escribir,
Q=>salida );

clockenable<='1';

PROCESS(RESET,clockLW,entrada,LWenable)

begin

if RESET='1' then direccion<="00000000";

elsif clockLW='1' and clockLW'event then

if LWenable='1' then escribir<='1';
leer<='0';
direccion<=direccion+1;
FULL<='0';
if direccion="11111111" then direccion<="00000000";
FULL<='1';
end if;

elsif LWenable='0' then escribir<='0';
leer<='1';
direccion<=direccion+1;
FULL<='0';
if direccion="11111111" then direccion<="00000000";
FULL<='1';
end if;
end if;
end if;

end PROCESS ;

end solucion;




3. Disee un multiplicador de 8 bibs

library ieee;
use ieee.std_logic_1164.all;

library lpm;
use lpm.lpm_components.all;

entity multip is
port( dataa : in std_logic_vector (7 downto 0);
datab : in std_logic_vector (7 downto 0);
result : out std_logic_vector (15 downto 0));
end multip;

architecture solucion of multip is

signal sub_wire0 : std_logic_vector (15 downto 0);

component lpm_mult

generic (lpm_widtha : positive;
lpm_widthb : positive;
lpm_widthp : positive;
lpm_widths : positive;
input_b_is_constant : string;
lpm_representation : string;
use_eab : string);

port (dataa : in std_logic_vector (7 downto 0);
datab : in std_logic_vector (7 downto 0);
result : out std_logic_vector (15 downto 0));

end component;

begin
result <= sub_wire0(15 downto 0);

lpm_mult_component : lpm_mult
generic map (lpm_widtha => 8,
lpm_widthb => 8,
lpm_widthp => 16,
lpm_widths => 16,
input_b_is_constant => "no",
lpm_representation => "unsigned",
use_eab => "off")

port map (dataa => dataa,
datab => datab,
result => sub_wire0);

end solucion;






4. Ejercicio utilizando el multip

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity MAC is
port(data_out: buffer std_logic_vector(15 downto 0);
clk: in std_logic;
dato: in std_logic_vector(7 downto 0));
end MAC;

architecture solucion of MAC is

component multip

port(dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
end component;

signal flag: std_logic;
signal salmult1: std_logic_vector(15 downto 0);
signal salsum: std_logic_vector(16 downto 0);

begin

U0: multip port map (data_out(7 downto 0),dato,salmult1);
salsum <= data_out+salmult1;

process(clk)
begin
if clk='1' and clk'event then
if flag='0' then
data_out <= "0000000000000101";
flag <= '1';
elsif flag='1' then
flag <= '1';
data_out <= salsum(15 downto 0);
end if;
end if;
end process;
end solucion;