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Question Paper Code:: Elective

This document appears to be an exam question paper for a Masters level course in VLSI Design, focusing on low power VLSI design. It contains 15 questions split into two parts - Part A contains 10 short answer questions worth 2 marks each, and Part B contains 5 long answer questions worth 16 marks each. The questions cover various topics related to low power VLSI design including subthreshold swing, transistor reordering, SRAM cells, row decoders, reconfigurable computing, signal activity, short circuit power, drain induced barrier lowering, low power design principles, power consumption sources, technology mapping, circuit level power reduction techniques, finite state machine power reduction through state assignment, write driver and sense amplifier power reduction, MTCMOS vs D

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Shanmugapriya Anandan

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0% found this document useful (0 votes)

95 views2 pages

Question Paper Code:: Elective

Uploaded by

Shanmugapriya Anandan

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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51

Reg. No. :

Question Paper Code : 98081

M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010

Elective
VLSI Design

VL 9252 LOW POWER VLSI DESIGN

(Common to M.E. Applied Electronics)
(Regulation 2009)
Time : Three hours

Maximum : 100 Marks

Answer ALL questions

PART A (10 2 = 20 Marks)
Define subthreshold swing.

What is body effect?

What is meant by transistor reordering?

Define intrinsic delay.

Draw a 6 transistor SRAM cell.

Compare NOR type row decoder and NAND type row decoder in memories.

What is reconfigurable computing?

Implement function AX 2 + BX + C using two multipliers and two adders.

Define signal activity.

10.

Write down an algorithm to compute signal probabilities.

PART B (5 16 = 80 Marks)
(a)

(i)

Derive an expression for short circuit power dissipation of a CMOS

inverter.
(10)

(ii)

Write a short note on drain induced barrier lowering.

(b)

12.

(a)

Explain basic principles of low power design.

(ii)

Discuss the various sources of power consumption in CMOS

devices.
(8)

(i)

Discuss the various features of technology mapping.

(ii)

Explain the circuit level techniques for minimization of power

dissipation.
(8)

(a)

(8)

(i)

Explain the concept of state assignment for finite state machine to

reduce power dissipation with example.
(10)

(ii)

Factoring out a common sub-expression can achieve power saving.

Justify.
(6)

(i)

How can power be reduced in write driver circuits and sense

amplifier circuits? Explain.
(10)

(ii)

Differentiate MTCMOS from DTCMOS.

13.

(6)

(i)

Or
(b)

51
6

11.

(6)

14.

(a)

(i)

Explain the working of DCVS voltage level converter.

(ii)

Design a full adder using Adiabatic logic.

(i)

How do you compute signal probability using binary decision

diagrams? Discuss.
(8)

(ii)

Discuss methods of estimating average power in combinational

circuits.
(8)

(b)

(10)
(6)

Explain in detail about Monte Carlo method for estimating glitch power.

(a)

(i)

Elaborate on the use of pipelining and parallelism for low power. (8)

(ii)

Discuss the principle of pre-computation logic for reducing power

with a suitable example.
(8)

15.

(b)

Explain the various methods to minimize power based on software power

optimization.

(b)

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Question Paper Code:: Elective

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Question Paper Code:: Elective

Uploaded by

51

Question Paper Code : 98081

M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010

VL 9252 LOW POWER VLSI DESIGN

Maximum : 100 Marks

Answer ALL questions

What is body effect?

What is meant by transistor reordering?

Define intrinsic delay.

Draw a 6 transistor SRAM cell.

What is reconfigurable computing?

Define signal activity.

Write down an algorithm to compute signal probabilities.

Derive an expression for short circuit power dissipation of a CMOS

Write a short note on drain induced barrier lowering.

Explain basic principles of low power design.

Discuss the various sources of power consumption in CMOS

Discuss the various features of technology mapping.

Explain the circuit level techniques for minimization of power

Explain the concept of state assignment for finite state machine to

Factoring out a common sub-expression can achieve power saving.

How can power be reduced in write driver circuits and sense

Differentiate MTCMOS from DTCMOS.

Explain the working of DCVS voltage level converter.

Design a full adder using Adiabatic logic.

How do you compute signal probability using binary decision

Discuss methods of estimating average power in combinational

Discuss the principle of pre-computation logic for reducing power

Explain the various methods to minimize power based on software power

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