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Digital Design M. Morris Mano
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[email protected]
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www.uqucs.com
Binary Systems ............................................. ....... ... .............. .
-
Introduction .................................................................... . ....... ... ...... .....
- Digital Systems ........................................ . ......... . ......... .. ... ..........
- The Conversion Between Numbering Systems ..... .. . ... . . ...
- Binary To Decimal From ..................................... . .. .......
.................................................. .. ..... .
Octet To Decimal -
......................... .. .. ...... . .. .
Hexadecimal To Decimal -
................. . ........................ ........... . .... Decimal To Binary -
........... .................................. ... ............ Decimal To Octet -
....................... .. .... .........
Decimal To Hexadecimal -
.......................... . ................. ....... .. ........... Binary To Octet -
...................... ............................. . ...... . . ... Octet To Binary -
............................... .. . . . .. ....
Binary To Hexadecimal -
............................... . ... .....
Hexadecimal To Binary -
.......... . ............ . ....... Operations on Binary Numbers -
................ . ............................................ .. .......... . ........... One's Complement -
................................................................ ........ .. .. .......... Two's Complement -
. ....... ......................................................... ... . ...... .... Adding & Subtraction -
................................ .. .... Boolean Algebra And Logic Gates
-
Introduction ...................................................................... ................. ..
........................................................... .................. Binary Logic -
..... .................... .................................... ...... ........... ........ .... Grammars -
................................................................... ...... .................. ....... Logic Gates -
.................................... ..... ....................... Complement of a Function -
........................ ............... ...... . .................... Canonical and Standard Forms -
..................... .............................................................. Digital Logic Gates -
...................................................Gate Level Minimization
-
Introduction .......................................................................... . .............
.................................................................... .. ... .. Map Method -
.................................................. .... .. Three Variable Map -
........................ ............. .................... Four Variable Map -
..................... ............................................................ Don't Care Conditions -
Combinational Logic ......................... ............................... ....
-
Introduction ........................................................................... ........... .
............................................................. ...... Analysis Procedure -
............................ . . ...................................... Design Procedure -
.................................................................. .............................. .. Half Adder -
... ............................................................................................... . Full Adder -
...................................................................... ............................... .. Decoder -
.. . ....................... .................................................................... ................ .. Decoder 2 * 4 -
.......................................................................................... .................... .. Decoder 3 * 8 -
.................... ..................................................................... .......... ......... .. Decoder 4 * 16 -
.. . ....................................... ............................... ........ . Decoder With Enabel -
...................................... ................ ............................... . ...... ...... Multiplexer -
........................................ .............. ..................................... .......... ......... Multiplexer 2*1-
................................................ .................................. ............. .............. . Multiplexer 4*1-
............................................................................... ........... .................... Multiplexer 8*1-
..................................... ..... Synchronous Sequential Logic
-
Introduction .......... . .......................... .............................. .. ........ . .........
........ . ................................................................ .. . ... ......... Types of Flip Flop -
.................. . ................................................................................... . .. ....... .... D Flip Flop -
........... ............ ........................................................................... . .............. J K Flip Flop -
... ............ ...................................................................................... . .............. T Flip Flop -
.. .. ........ ... Analysis of clocked sequential circuits -
.. . . ........................................................................ .............. ......... State Table -
........................ .. ...... ........................................ ............... ....... State Diagram -
. .. .............................................................. State Reduction and Assignment -
........ .. ............................................... ... .......... Design Procedure -
.......................................................Registers and Counters
-
Introduction ...................................................................... .............. ....
. . ............................................................................. .............. Register -
............................... ................................................................... .............. Shift Register -
............................................................................................ . .. .............. Rotate Register -
..... . ................... ........................................................... ........... Counter -
.................................... ................................................ ................
-
Introduction :
(Digital systems) :
(Decimal system) (Binary system) (Octet system)
(Hexadecimal system) .
(Operations on binary numbers) :
(One's complement) ) two's complement (
. (Adding & Subtraction)
- Digital Systems :
Base Digits System
10 0,1,2,3,4,5,6,7,8,9 Decimal System
2 0,1 Binary System
8 0,1,2,3,4,5,6,7 Octet System
16 0,1,2,3,4,5,6,7,8,9,
A,B,C,D,E,F
Hexadecimal System
-
The Conversion Between Numbering Systems :
- Binary To Decimal
From :
: Example
:
(1011)2
: Selution
(1011)2 = 1*2 + 1*2 + 0*2 + 1*2
= 1 + 2 + 0 + 8
= (11)10
: explain
1
(1011)2
2
1
2 0
2
1 2
.
11=
: Example
:
(110.1)2
: Selution
(110.1)2 = 0*2 + 1*2 + 1*2 + 1*2
= 0 + 2 + 4 + 0.5
= (6.5)10
: explain
.
.
. 2
. 1
0,1,2,3,..
2
. -1,-2,-3
: Example
:
(1100.101)2
: Selution
= 0*2 + 0*2 + 1*2 + 1*2 + 1*2 + 0*2 +1*2
= 0 + 0 + 4 + 8 + 0.5 + 0 + 0.125
= (12.625) 10
: Octet To Decimal -
2
8
: Example
:
(752)8
: Selution
(752)8 = 7*8 + 5*8 + 2*8
= 7 + 40 + 448
= (490) 10
: Example
:
(35.6)8
: Selution
(35.6)8 = 5*8 + 3*8 + 6*8
= 5 + 24 + 0.75
= (29.75)10
: Hexadecimal To Decimal -
16
: Example
:
(ABC)16
: Selution
(ABC)16 = 12*16 + 11*16 + 10*16
= 12 + 176 + 2560
= (2748)10
: Example
:
(2F.8)16
: Selution
(2F.8)16 = 15*16 + 2*16 + 8*16
= 15 + 32 + 0.5
= (47.5) 10
:
) ( ) (
.
: Decimal To Binary -
: Example
:
(59)10
: Selution
2
59
29 1
14 1
7 0
3 1
1 1
0 1
(59)10 = (111011)2
: explain
59
.
29.5 =
2
59
1 2 0.5
2
29
1 = 0 =
. 59 (111011)
:
-
0 = 14 / 2 = 7
- .
: Example
:
(0.78125)10
: Selution
0.78125 * 2 = 1.5625
1
0.5625 * 2 = 1.125
1
0.125 * 2 = 0.25
0
0.25 * 2 = 0.5
0
0.5 * 2 = 1
1
(0.78125)10 = (0.11001)2
: explain
: (0.78125)
2
1 (1.5625)
2
(0.78125)
(0.5625)
.
:
-
.
-
.
: Example
:
(35.375)10
:
.
2
35 0.375 * 2 = 0.75
0
17 1 0.75 * 2 = 1.5
1
8 1
0.5 * 2 =
1
1
4 0 (0.011)
2 0
1 0
0 1
(100011)
(35.375)10 = (100011.011)2
: Decimal To Octet -
: Example
:
(153.6875)10
: Selution
8
153 0.6875 * 8 = 5.5
5
19 1 0.5 * 8 = 4
4
2 3
(0.54)
0 2
(231)
(153.6875)10 = (231.54)8
: explain
8
:
(0.125)
(19.125) 8
(153)
1
8
(19)
= . 0 =
.
:Decimal To Hexadecimal -
16
. (D) 13 = 125
: Example
:
(125.34375)10
: Selution
16
125 0.34375 * 16 = 5.5
5
7 13 0.5 * 16 = 8
8
0 7
(0.58)
(7D)
(125.34375)10 = (7D.58)16
:
) ( :
.
.
: Binary To Octet -
:
: Example
:
(10011101110)2
: Selution
010 011 101 110
2 3 5 6
(10011101110)2 = (2356)8
: explain
.
.
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
: Example
:
(.0101111)2
: Selution
010 111 100
2 3 4
(.0101111)2 = (.234)
: explain
.
) (
.
: Example
:
(11001.01)2
: Selution
011 001 .010
3 1 2
(11001.01)2 = (31.2)8
: explain
.
: Octet To Binary -
.
: Example
:
(62.7)8
: Selution
(62.7)8 = (110 010 . 111)2
: Example
:
(35.41)8
: Selution
(35.41)8 = (011 101 . 100 001)
: Binary To Hexadecimal -
:
:
Example
:
(0010 1110. 1010)2
: Selution
(0010 1110.1010)2 = (2E.A)16
: Example
:
(1111 1100. 0101 1011)2
: Selution
(1111 1100. 0101 1011)2 = (FC.5B)16
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
A 1010
B 1011
C 1100
D 1101
E 1110
F 1111
: Hexadecimal To Binary -
: Example
:
(AB.6D)16
: Selution
(AB.6D)16 = (1010 1011.0110 1101)2
: Example
:
(9C.8F3)16
: Selution
(9C.8F3)16 = (1001 1100.1000 1111 0011)2
: Operations on Binary Numbers -
: One's Complement -
. 1
0
: Example
:
(1100101001)2
: Selution
0011010110 =
:Example
:
(10000000000)2
: Selution
01111111111 =
: Two's Complement -
.
.
:
:
1
: Example
:
(1100101001)2
: Selution
0011010110 =
:
1 :
0011010111 =
: Example
:
(1111000000)2
: Selution
0000111111 =
:
:
1
0
1 1 0
.
: Example
:
(1100101001)2
: Selution
0011010111 =
: explain
1
0
1 1 0
: Example
:
(1111000000)2
: Selution
0001000000 =
: explain
1
.
: Adding & Subtraction -
.
.
: Example
:
1101 - 0100
: Selution
1101 - 1100 = +1001
: explain
.
0100 1101
. 1100 =
4 (Overflow) 11001 =
4 5 4
+ .
:Example
:
0110 - 1100
: Selution
0110 - 1100 = -0110
: explain
4 (Overflow)
- 0110 = 1010
:
( + Overflow)
(Overflow)
-
Introduction :
(Functions)
(Boolean algebra)
. (karnaugh map)
.
(AND , OR , NOT..)
. (Maxterms) (Minterms)
: Binary Logic -
AND OR NOT
X Y
X .Y
X + Y X Y
0 0 0 0 1 1
0 1 0 1 1 0
1 0 0 1 0 1
1 1 1 1 0 0
(Truth table)
(Functions)
: Grammars -
(Boolean Algebra) (Functions)
( . De Morgan)
9
OR
1
x+1 = 1
2
x+x' = 1
3
x+x = x
4
x+0 = x
5
(x')' = x
6
x+y = y+x
7
x+(y+z) = (x+y)+z
8
x.(y+z) = x.y+x.z
9
(x+y)' = x'.y'
10
x+(x.y) = x
AND
1
x.1 = x
2
x.x' = 0
3
x.x = x
4
x.0 = 0
5
(x')' = x
6
x.y = y.x
7
x.(y.z) = (x.y).z
8
x+y.z = (x+y).(x+z)
9
(x.y)' = x'+y'
10
x.(x+y) = x
: Logic Gates -
Name Graphic Symbol Algebraic
Function
AND
F = xy
OR
F = x+y
Inverter
F = x'
.
: Example
:
F1 = x + y'z
: Selution
: Example
:
F1 = xy' + x'z
: Selution
: Example
: Simplify the following Boolean functions
x(x' + y) -
x + x'y -
(x + y).(x + y') -
xy + x'z + yz -
: Selution
(Boolean Algebra)
. (OR) (AND)
1- x(x' + y) = xx' + xy
= 0 + xy
= xy
2- x + x'y = (x+x').(x+y)
= 1 .(x+y)
= x + y
3- (x+y) (x+y') = x(x+y') + y(x+y')
= xx + xy' + xy + yy'
= x+xy' +xy +0
= x(1+y'+y)
= x1
= x
4- xy + x'z + yz = xy + x'z + yz.(x+x')
= xy + x'z + xyz + x'yy
= xy(1+z) + x'z(1+y)
=xy +x'z
: Complement of a Function -
(A + B + C + D )' = A'B'C'D'
(ABCD)' = A' + B' +C' + D'
( . De Morgan)
:
. (OR) (AND) -
- .
: Example
: find the complement of the following functions
F1 = x'yz' + x'y'z
: Selution
F1 = (x'yz' + x'y'z)'
= (x'yz')' . (x'y'z)'
= (x+y'+z) . (x+y+z')
: explain
.
:
. (AND) (OR) -
- .
. (OR)
(AND) -
- .
: Example
: find the complement of the following functions
F1 = (x+y'+z').(x'+y+z).(x'+y'+z')
: Selution
F1 = ((x+y'+z').(x'+y+z).(x'+y'+z'))'
=(x+y'+z')' + (x'+y+z)' + (x'+y'+z')'
= (x'yz) + (xy'z') + (xyz)
Canonical and Standard Forms -
Minterms Maxterms
X Y Z Term deaignation
Term deaignation
0 0 0 x'y'z' m0 x+y+z M0
0 0 1 x'y'z m1 x+y+z' M1
0 1 0 x'yz' m2 x+y'+z M2
0 1 1 x'yz m3 x+y+'z' M3
1 0 0 xy'z' m4 x'+y+z M4
1 0 1 xy'z m5 x'+y+z' M5
1 1 0 xyz' m6 x'+y'+z M6
1 1 1 xyz m7 x+'y'+z' M7
: explain
(Maxterms) (Minterms) (X,Y,Z) (Truth table)
. (Maxterms) (Minterms)
Maxterms Minterms
(OR)
(AND)
(x+y'+z) (010)
1 0
(x'yz') (010)
0 =
1 =
(Maxterms) (Minterms) :
(Minterms) (De Morgan)
: Example
:
Products of Sum
Sum of Products
: Selution
Sum of Products Minterms
Products of Sum Maxterms
:Sum of Products( )
F1 = x'y'z + xy'z' + xyz = m1 + m4 + m7
( 1,4,7)
F2 = x'yz + xy'z + xyz' + xyz = m3 + m5 + m6 + m7
( 3,5,6,7)
: Products of Sum ) (
F1 = (x+y+z)(x+y'+z)(x+y'+z')(x'+y+z')(x'+y+'z) = M0.M2.M3.M4 (0,2,3,5,6)
F2 = (x+y+z)(x+y+z')(x+y'+z)(x'+y+z) = M0.M1.M2.M4 (0,1,2,4)
X Y Z F1 F2
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
: Example
: Express the Boolean function F = A + B'C in a sum of minterms
: Selution
.
:
F = A + B'C
= A(B+B') + B'C
= AB +AB' + B'C
= AB(C+C') + AB'(C+C') +B'C(A+A')
= ABC + ABC' + AB'C + AB'C' + AB'C + A'B'C
= ABC + ABC' + AB'C + AB'C' + A'B'C
: explain
F = A + B'C (sum of minterms)
A,B,C :
(B'C) (A)
. (sum of minterms)
(B) (C) (A)
1
(B+B') A 1=
(C+C')
(AB')
(AB)
.
(A) (B'C)
.
:
F = A + B'C
= [ ABC + ABC' + AB'C + AB'C' ] + [ AB'C + A'B'C ]
= ABC + ABC' + AB'C + AB'C' + A'B'C
: explain
.
(B) (C ( ) A)
. (A)
(B'C)
.
: Example
: Express the Boolean function F = xy + x'z in a product of maxterms from
: Selution
:
F = xy + x'z
= (x+x'z)(y+x'z)
= (x+x')(x+z)(y+x')(y+z)
= 1(x+z)(y+x')(y+z)
= (x+z)(y+x')(y+z)
= (x+y+z)(x+y'+z)(x'+y+z)(x'+y+z')(x+y+z)(x'+y+z)
= (x+y+z)(x+y'+z)(x'+y+z)(x'+y+z')
= M0 . M2 . M3 . M4 = (0,2,4,5) = (1,3,6,7)
: explain
F = xy + x'z (product of maxterms)
(OR) (AND)
. (OR) (AND)
(x'z) (xy)
. (x+x'z)(y+x'z)
.
.
:
F = xy + x'z
= xyz + xyz' + x'yz + x'y'z
= m7 + m6 + m3 + m1 = (1,3,6,7) = (0,2,4,5)
: explain
1 =
(Minterms)
0 = (Maxterms)
(product of maxterms) (sum of minterms)
(sum of minterms) (product of maxterms)
1= (sum of minterms)
(1,3,6,7)
(product of maxterms) (0,2,4,5)
. (Maxterms)
: Digital Logic Gates -
Name Graphic Symbol Algebraic
Function
Truth Table
AND
F = xy
X
Y
F
0 0 0
0 1 0
1 0 0
1 1 1
OR
F = x+y
X
Y
F
0 0 0
0 1 1
1 0 1
1 1 1
Inverter
F = x'
X
F
0 1
1 0
Buffer
F = x
X
F
0 0
1 1
NAND
F = (xy)'
X Y F
0 0 0
0 1 1
1 0 1
1 1 1
NOR
F = (x+y)'
X Y F
0 0 0
0 1 0
1 0 0
1 1 1
XOR
F = xy' + x'y
= x
y
X
Y
F
0 0 0
0 1 0
1 0 0
1 1 1
XNOR
F = xy' + x'y
= x
y
X
Y
F
0 0 0
0 1 0
1 0 0
1 1 1
-
Introduction :
.(karnaugh map) (Functions)
. (karnaugh map)
: Map Method -
. (karnaugh map)
. (Y) 0,1
(X)
. (Y)
(X)
. (Y)
(X)
X Y
Minterms
0 0 x'y'
m0
0 1 x'y m1
1 0 xy' m2
1 1 xy m3
: Example
: Simplify the following Boolean function
F(x,y) = x'y + x'y'
: Selution
F(x,y) = x'
: explain
. x'y + x'y'
1
(Y) 0 (X) (x'y)
1
1
(Y) (X)
1
0
0 (Y) 0
(X)
(x'y')
.
:
1
4
8 16
.
(X)
(X) X 1 X' 0 (X)
(X)
1 0 (X)
.(Y)
(Y)
(X) 1 X' =
. (Y) (Y) 0
: Example
: Simplify the following Boolean function
F(x,y) = xy + x'y
: Selution
F(x,y) = y
: explain
(X)
1 0 (X)
. (Y)
1
(Y)
: Example
: Simplify the following Boolean function
F(x,y) = x'y' + xy' + xy
: Selution
F(x,y) = x + y'
: explain
1
. 1
1
1
0
1
2
1
1 1
3
3 0
1
1s
1s
1 1
1
.
: Example
: Simplify the following Boolean function
F(x,y) = xy + x'y + xy' + x'y'
: Selution
F(x,y) = 1
: explain
4
.
1=
:Three Variables Map -
. (karnaugh map)
( . YZ)
(X)
:
2
3 1 -
. 6 7
5
2 0 (karnaugh map) -
2
0 1s 6 4
. 6 4
: Example
: Simplify the following Boolean function
F(x,y,z) = (3,4,6,7)
: Selution
F(x,y,z) = xz' + yz
: explain
1s
.
1
( . Z)
(X) 4,6
. (X) 1 = (X)
(Z ,Y)
(Y)
(Y)
1
0
(Y)
(Z)
(Z)
(Z')
0 =
. 3,7
+
xz' + yz =
+ .
: Example
: Simplify the following Boolean function
F(x,y,z) = (0,1,2,4.5,6)
: Selution
F(x,y,z) = y' + z'
: Example
: Given the Boolean function
F(x,y,z) = A'C + A'B + AB'C + BC
Express it in sum of minterms -
Find the minimal sum of products expression -
: Selution
F(x,y,z) = (1,2,3,5,7) -
F(x,y,z) = C + A'B -
: explain
(sum of products)
1s
.
Four Variables Map -
. (karnaugh map)
. (X)
(W)
(karnaugh map)
.
(karnaugh map)
.
. (karnaugh map)
(karnaugh map)
: Example
: Simplify the following Boolean function
F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14)
: Selution
F(w,x,y,z) = y' + w'z' + xz'
: explain
.
(karnaugh map)
.
: Example
: Simplify the following Boolean function
F(w,x,y,z) = (0,2,3,5,7,8,9,10,11,13,15)
: Selution
F(w,x,y,z) = wx' + yz + xz + x'z'
: Don't Care Conditions -
: Example
: Simplify the following Boolean function
F(w,x,y,z) = (0,3,7,11,15)
Which has the don't care conditions
d(w,x,y,z) = (0,2,5,8)
: Selution
F(w,x,y,z) = w'x' + yz
: explain
. (x) (Don't care)
(Don't care)
(Don't care)
. 1s
(Don't care) 1s (karnaugh map)
.
3,7,15,11
.
0,1,3,2,
1,3
(Don't care)
(Don't care)
.
.
(Don't care)
. 5,8
(Don't care)
.
-
Introduction :
(Analysis) .
(Design) .(Design)
:
Half Adder) ( Full Adder) ( (Decoder) (Multiplexer)
.
: Analysis Procedure -
T1 = A + B + C
T2 = ABC
F2 = AB + AC + BC
T3 = T1F'
= (A+B+C)(AB+AC+AB)'
= (A+B+C)(A'+B')(A'+C')(B'+C')
F1 = T2 + T3
= (ABC) + (A'+B')(A'+C')(B'+C')
: explain
. F1,F2
.
.
: Design Procedure -
: (Design)
- .
. (Truth table) -
- .
- .
: Example
Design a combinational circuit that converts the binary coded decimal (BCD)
the excess-3 code for the decimal digit
: Selution
. 3 (BCD)
A,B,C,D 4 (Truth table)
W,X,Y,Z
3 ) (
:
0 0 1 1(3) 3 0 0 0 0 (0) -
0 1 1 1 (7) 3 0 1 0 0 (4) -
:
(Truth table)
9 (BCD)
9
: 6
(Don't care) 9
InPuts OutPuts
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
:
.
W X
W = A + BD + BC
X = BC'D' + B'D + B'C
Y Z
Y = C'D' + CD Z = D'
:
.
.
W X
Y Z
: Half Adder -
:
Truth
Table
(Sum)
(S)
X+Y
0 1 (Carry) (Carry)
(C)
1 X+Y (Carry)
InPuts OutPuts
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Algebraic
Function
S = xy' + x'y
C = xy
(A)
S = x
y
C = xy
(B)
Graphic
Symbol
(A)
(B)
(Half adder)
: Full Adder -
: (Half adder)
Truth
Table
(Carry out) (Co) (Carry in)
(Ci)
InPuts OutPuts
X Y Ci Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Algebraic
Function
S = x'y'z + x'yz' + xy'z' + xyz
= x y
z
C = xy + xz + yz
Graphic
Symbol
: Example
: Design a 4 - bit full adder
: explain
(Ci) = 0
(full adder) 4
:
: Example
: Design a 4 - bit full subtractor using full adder and additional gates
: Selution
: explain
(Ci) = 1
(full adder) 4
. (Two's Complement)
: (Two's Complement)
= A + (B' + 1)
= A + (2's Comp of B)
= A - B
: Example
: Design a 2 - bit binary multiplier
: Selution
. (multiplier)
(A B)
(B1 B0) (A1 A0)
: A*B
0 = B = 1 0 (2)
A = 0 0 (0) -
0
3 = B = 1 1 (3) A = 0 1 (1) -
. 3
.
InPuts OutPuts
A1 A0 B1 B0 C3
C2
C1
C0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1
C0 C1
C2 C3
C0 C1
C2 C3
: Example
: Design a 2 - bit magnitude comparator
: Selution
.
(magnitude comparator)
InPuts OutPuts
A1 A0 B1 B0
X
(A>B)
Y
(A<B)
Z
(A=B)
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1
X Y
X = A1B'1 + A1A0B'0 + A0B'1B0
Y = A'1B1 + A'0B1B0 + A'1A'0B0
Z
Z = A'1A'0B'1B'0 + A'1A0B'1B0 + A1A0B1B0 + A1A'0B1B'0
X Y
Z
: Decoder -
A decoder has n inputs and
outputs
) ( 2
= n =
4 = = 2 =
8 = = 3 =
. (Decoder)
: Decoder 2 * 4 ( Has 2 inputs and 4 outputs ) -
( : Decoder)
Truth Table
A,B
0 1 D0
0 =
1 D1
1 =
. 0
InPuts
OutPuts
A
B
D3
D2
D1
D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Graphic
Symbol
(Decoder)
: Decoder 3 * 8 -
: Decoder 4 * 16 -
: Decoder With Enabel -
: (Enabel)
. (Decoder) (Enabel) = 0
. (Decoder) (Enabel) = 1
. (Enabel)
(Enabel)
(Enabel) = 0
0 = (Decoder)
(Enabel) = 1
. (Decoder)
.
.
.
(Don't care)
(X)
(A) (B) = X
(Don't care)
(A) (B) (Don't care)
1 =
0 = (X)
( . A) (B)
InPuts OutPuts
E A B
D3
D2
D1
D0
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
InPuts OutPuts
E A B
D3
D2
D1
D0
0 X X
0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
: Example
: Desing a Decoder 3*8 using a Decoder 2*4 with Enable and additional gate
: Selution
(Enable) (Decoder 2*4) (Decoder 3*8)
: explain
(Enabel) (A)
.
InPuts OutPuts
A
B C
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
: Example
: Desing a Decoder 4*16 using a Decoder 3*8 with Enable and additional gate
: Selution
(Enable) (Decoder 3*8) (Decoder 4*16)
.
: Multiplexer -
A Multiplexer has
inputs , 1outputs and n selections
n = (Selections) 1 = =
2 = 1 = 4 =
=
3 =
1 = 8 = =
: Multiplexer 2*1 -
A Multiplexer has 2 inputs , 1 outputs and 1 selections
( : Multiplexer)
Truth Table
:
Q = Y , Y S = 0
Q = X , X S = 1
Selection
InPuts OutPuts
S X Y Q
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Algebraic
Function
Q = sy + sx
Graphic
Symbol
(Multiplexer)
: Multiplexer 4*1 -
: Multiplexer 8*1 -
: Example
: Construct an Multiplexer 8*1 with two Multiplexer 4*1 and additional gate
: Selution
( . Multiplexer 4*1) 2 (Multiplexer 8*1 ) )(
: Example
: Construrt an Multiplexer 8*1 with two Multiplexer 4*1 and one Multiplexer 2*1
: Selution
(Multiplexer 4*1) 1 (Multiplexer 4*1) 2 (Multiplexer 8*1 ) )(
: Example
: Implement the following Boolean function F(x,y,z) = (2,5,6) using an 8*1 Multiplexer
: Selution
(8*1 Multiplexer)
: Example
: Implement the following Boolean function F(A,B,C) = (2,3,5,6) using an 4*1 Multiplexer
: Selution
(4*1 Multiplexer)
: explain
(8*1 Multiplexer)
(4*1 Multiplexer)
A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
-
Introduction :
. (Flip Flop)
.
(Analysis of clocked sequential circuits)
(State table) (State diagram) ) circuits ( .
: Types of (Flip Flop) -
: D Flip Flop -
( : Flip Flop)
. (D Flip flop)
Characteristic
Table
Q(t+1)
Q(t+1)
.(D)
D Q(t+1)
0 0
1 1
Truth Table
Presnt State
Next State
D Q(t) Q(t+1)
0 0 0
0 1 0
1 0 1
1 1 1
Characteristic
Equation
Q(t+1) = D
Excitation
Table
Q(t+1),Q(t) (D)
. (Truth Table)
Q(t)
Q(t+1)
D
0 0 0
0 1 0
1 0 1
1 1 1
: J K Flip Flop -
( : Flip Flop)
Characteristic
Table
J K
Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q'(t)
Truth Table
Presnt State Next State
J K Q(t)
Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Characteristic
Equation
Q(t+1) = JQ'(t) + K'Q(t)
Excitation
Table
Q(t)
Q(t+1)
J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 1
: T Flip Flop -
( : Flip Flop)
Characteristic
Table
T Q(t+1)
0 Q(t)
1 Q'(t)
Truth Table
Presnt State
Next State
T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
Characteristic
Equation
Q(t+1) = T'Q(t) + tq'(t) => T Q(t)
Excitation
Table
Q(t)
Q(t+1)
T
0 0 0
0 1 1
1 0 1
1 1 0
: Example
: Desing a J K Flip Flop using D Flip Flop
Selution :
(J K Flip Flop) (D Flip Flop)
Truth table) (
Truth table) ( :
- (Presnt state)
(Flip Flop) (Flip Flop)
(J K)
Q(t)
- (Next state)
(Flip Flop) (D)
Q(t+1)
Q(t+1) (Characteristic table) (J K Flip Flop)
) D ( ) (Excitation table (D Flip Flop)
(Flip Flop)
Q(t+1) (D Flip Flop)
D = JQ'(t) + K'Q(t)
J K Q(t)
Q(t+1)
D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
.
.
: Example
: Desing a T Flip flop using J K Flip flop
: Selution
(T Flip Flop) (J K Flip Flop)
.
T Q(t)
Q(t+1) J K
0 0 0 0 X
0 1 1 X 0
1 0 1 1 X
1 1 0 X 1
J K
K = T
J = T
: Analysis of clocked sequential circuits -
: Example
: Analysis of clocked sequential circuits
: Selution
.
(A Flip Flop) (Flip Flop) 1
A(t+1) (N.S)
(Flip Flop)
A(t+1) = D
A(t+1) = XA'(t)
: Example
: Analysis of clocked sequential circuits
: Selution
(O/P)
(N.S)
(Flip Flop) 2
A(t+1) (N.S) (A Flip Flop)
B(t+1) (N.S) (A Flip Flop)
(O/P) Y
:
A(t+1) = DA XA + XB
B(t+1) = DB XA'
Y = (A+B)X' X'A + X'B
: State Table -
( . State table)
P.S I/P N.S O/P
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
: explain
(O/P), (N.S)
(State table)
(State table) Y , B(t+1) , A(t+1)
.
:
( . I/P)
(P.S)
(O/P) (N.S)
(A) A(t+1)
(B) B(t+1)
(Y) Y
(X = 1) (B = 1) (A = 0) ( : O/P) (N.S)
(A) A(t+1) = XA + XB
A = XA + XB
=1*0 + 1*1
= 0 + 1
= 1
(B) B(t+1) = XA'
B = XA'
= 1*1
= 1
(Y) Y = X'A + X'B
Y = X'A + X'B
= 0*1 + 0*1
= 0 + 0
.
: State Diagram -
(State diagram)
: explain
( . State table) (State diagram)
.
:
[(P.S),(N.S)] (A B)
[(I/P),(O/P)] (X Y)
(O/P) Y (I/P) X
(State diagram) (State table)
(O/P) = 0 (I/P) = 0 (N.S) = 00 (P.S) = 00 :
: (State table)
00 = (N.S)
00 = (P.S)
(I/P) (00) (00) (N.S) (P.S)
(O/P) = 0 (I/P) = 0 (O/P)
(O/P) = 0 (I/P) = 1 (N.S) = 11 (P.S) = 10
. (1/0) (11) (10)
: Example
: Analysis with J K Flip flop
: Selution
.
JA = B KA = X'B
JB = X' KB = A'X + X'A => X A
A(t+1) = JA*A' + K'A*A
= BA' + (X'B)'A
= A'B + (X+B')A
= A'B + XA + AB'
B(t+1) = JB*B' + K'B*B
= X'B' + (XA' + X'A)'B
= X'B' + X'A'B + XAB
: State Table
P.S I/P N.S
A B X A B
0 0 0 0 1
0 0 1 0 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 0
1 1 1 1 1
: State Diagram
: explain
. (Y)
(X)
: Example
: Analysis with T Flip flop
: Selution
.
TA = XB
TB= X
A(t+1) = TA
A' B(t+1) = TB
B Y =AB
= XB A = X
B
: State Table
P.S I/P N.S O/P
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 1
: State Diagram
: explain
(Y) (State diagram)
(X)
(N.S) (Y) (A,B) (N.S)
(X)
(Y) (Y) (X)
. (X)
(Y)
. (Y)
: State Reduction and Assignment -
(State table)
(State diagram) (State table)
. (State table)
: Example
: Selution
(State table) (State diagram) (State table)
.
:
. P.S)
. (X)
. (N.S) (X)
. (O/P) (X)
(State diagram) (State table)
.
: State Table
: explain
. (State diagram) (State table)
:
. (P.S)
. (N.S)
(X = 0) 0 = (X)
(X = 0) (N.S)
(X) (O/P)
(X = 1) 1 = (X)
(X = 1) (N.S)
(X)
(O/P)
:
(State diagram) (P.S = a)
(a)
(0/0) (a)
(a) (N.S) (X = 0)
(O/P) (X = 0)
(0) (X)
.
(b)
.
.
.
.
N.S O/P P.S
X = 0
X = 1
X = 0
X = 1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
.
(g) (g) (e)
(e) (g)
( . e) (f) (g)
(f ( ) d) (e) (g) (g)
. (d) (f ) (f)
(State table) (d)
(f)
(f)
.
N.S O/P P.S
X = 0
X = 1
X = 0
X = 1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
N.S O/P P.S
X = 0
X = 1
X = 0
X = 1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
: Design Procedure -
(Analysis of clocked sequential circuits)
(Analysis of clocked sequential circuits)
(State table) (O/P) (N.S)
. (State diagram)
(State diagram) (Design Procedure)
(N.S)
(State table)
. (O/P)
: Example
: Design circuit thet delects three or more consecutive 1'S in a string of bits
: Selution
: D Flip flop
P.S I/P N.S O/P
A B X A B Y DA
DB
0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1
0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0
1 0 1 1 0 0 1 1
1 1 0 0 1 1 0 0
1 1 1 1 1 1 1 1
DA DB
DA = AX + BX
DB = AX + B'X
Y
Y= AB
: J K Flip flop
P.S I/P N.S O/P
A B X A B Y JA
KB
JA KB
0 0 0 0 0 0 0 X 0 X
0 0 1 0 0 0 0 X 1 X
0 1 0 0 0 0 0 X X 1
0 1 1 1 0 0 1 X X 1
1 0 0 0 0 0 X 1 0 X
1 0 1 1 0 0 X 0 1 X
1 1 0 0 1 1 X 1 X 1
1 1 1 1 1 1 X 0 X 0
JA KA
JA = BX
KA = X'
JB KB
JB = X
KB = A'+X'
Y
Y= AB
: T Flip flop
P.S I/P N.S O/P
A B X A B Y TA TB
0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1
0 1 0 0 0 0 0 1
0 1 1 1 0 0 1 1
1 0 0 0 0 0 1 0
1 0 1 1 0 0 0 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 0 0
TA TB
TA = A'BX + AX'
TA = B'X + A'X + Bx'
Y
Y= AB
-
Introduction :
: (Register)
(Rotate) (Shift)
. (Counter)
: Register -
A7
A6
A5
A4
A3
A2
A1
A0
(Register)
: Shift Register -
(Register) (Shift) (Register)
(Register) (Register)
(0) (Register)
: Example
: Shift left R
R
1 1 0 1
: Selution
(R Register) (Shift)
(Shift) (Register)
(0)
:
:
R
1 0 1 0
: Example
: Shift Right R
R
0 1 0 1
: Selution
(R Register) (Shift)
R
0 0 1 0
: Rotate Register -
(Shift) (Register)
(Register) (Shift)
: Example
: Rotate left R
R
1 0 0 1
: Selution
(R Register) (Rotate)
:
:
R
0 0 1 1
: Example
: Rotate Right R
R
0 1 0 1
: Selution
(R Register) (Rotate)
R
1 0 1 0
: Example
: Rotate Right R 3 himes
R
1 1 0 0 0 1 0 1
: Selution
(R Register) 3
(Rotate)
R
1 1 1 1 0 0 0 1 0
2 0 1 1 1 0 0 0 1
3 1 0 1 1 1 0 0 0
: Example
: Content of Register A(11010100) shift Register a 4 times or the left with serial input
101100
A
1 1 0 1 0 1 0 0
: Selution
. (A Register) 4 (Shift)
(Serial)
.
(Serial) 4 (Shift)
. (Serial)
(Register) 1 (Serial)
.
0 (Serial)
. 4 (Shift)
1 1 0 1 0 1 0 0 1
2 0 1 0 1 0 0 1 0
3 1 0 1 0 0 1 0 1
4 1 1 0 0 1 0 1 1
: Counter -
: Example
: Design a 3-bit Counter using T Flip flop
: Selution
. (T Flip flop) (3-bit)
P.S N.S
A2 A1 A0 A2 A1 A0
TA2
TA1
TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
: explain
(State diagram) (State table)
. 8 3
:
: 2 = 8
. (3-bit)
3
. 8
(4-bit)
:
= 16
16 = 4
(Counter)
. (Design Procedure)
:
(Counter) (State diagram)
: (State table)
. (P.S)
. (N.S)
(Excitation table) (T Flip Flop)
(T Flip Flop)
. (State table) (T Flip Flop)
Excitation Table
(N.S) Q(t+1) (N.S) Q(t)
: (TA2)
(P.S) (A2) (TA2)
(N.S) (A2)
.
(Excitation table)
. (State diagram) (State table)
Q(t)
Q(t+1)
T
0 0 0
0 1 1
1 0 1
1 1 0
. (State table) (T Flip Flop)
(Counter)
.
TA2 TA1
TA2 = A1A0
TA1 = A0
TA0
TA0 = 1
: Example
: Design a Counter that goce through the following binary repeated sequence : 0,1,2,4,5,6
using T Flip flop
: Selution
(T Flip flop)
:
0
1
2
4
5
6
0
6
:
0 1 2 4 5 6 0
3
7 (N.S) (P.S)
(Don't care) (N.S) (P.S)
.
P.S N.S
A2 A1 A0 A2 A1 A0
TA2
TA1
TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 1 0 0 1 0 0
0 1 1 X X X X X X
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0
1 1 1 X X X X X X
TA2 TA1
TA0 = 1
TA1 = A0
TA0
TA2 = A1A0
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