Phase Locked Loop (PLL)
Vineet Sahula
[email protected]
Phase Locked Loop System
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 2
Phase Detector
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 3
PLL
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 4
PLL- Linear Analysis
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 5
I Order without Filter
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 6
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 7
I Order Filter Characteristics
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 8
I Order Filter- Analysis
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 9
Filter with Pole only
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 10
Filter with a zero added
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 11
Filter Circuit
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 12
Freq. Response
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 13
PLL Lock range
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 14
Lock Range
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 15
Integrated Circuit PLL
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 16
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 17
VCOEmitter Coupled Multi-vibrator
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 18
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 19
Multivibrator VCO
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 20
Analog Multiplier
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 21
Analog Multiplier
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 22
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 23
Gilbert Cell
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 24
Gilbert Cell analysis
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 25
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 26
Inverse Hyperbolic Tangent (predistortion)
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 27
tanh-1 circuit- Analysis
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 28
4-Quadrant Multiplier
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 29
Gilbert Multiplier as Balanced Modulator
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 30
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 31
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 32
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 33
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL 34
Type I PLL
H(s) open
out
(s) open
in
1
K PD
s
1
LPF
IIT Mandi, Even Semester (Analog CMOS & beyond)
KVCO
PLL # 35
Type I PLL
KPD KVCO
out
(s) 2
s
in
s K PD KVCO
LPF
out
n2
(s) 2
(second order system)
2
in
s 2 n s n
n LPF KPD KVCO (natural frequency)
1
2
LPF
K PD KVCO
(damping ratio)
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 36
Type I PLL
1
n LPF
2
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 37
Type I PLL
Transient response as a function of
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 38
Type I PLL Bode Plot
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 39
Acquistion Range
Acquistion range is LPF
Improved Acquistion Range System
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 40
Phase-Frequency Detector
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 41
Phase-Frequency Detector
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 42
PFD with LPF
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 43
PFD with Charge Pump
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 44
Basic Charge-Pump PLL
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 45
Charge-Pump PLL Dynamics
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 46
Charge-Pump Transfer Function
Vout (t)
h(t)
Ip
2 C p
Ip
2C p
t 0 u(t)
u(t)
Ip 1
Vout
(s)
2 C p s
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 47
I p KVCO
out
(s) open
2
in
2Cp s
I p KVCO
I p KVCO
2 Cp
H(s)
, s j
I
K
2
p VCO
2 Cp
s
2 Cp
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 48
CPPLL Compensation
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 49
CPPLL with Zero Added
I p K VCO
(RP CP s 1)
2 Cp
H(s)
I p KVCO
I p KVCO
2
s
RP s
2
2 Cp
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 50
CPPLL with Zero Added
I p K VCO
(RP CP s 1)
2 Cp
H(s)
I p KVCO
I p KVCO
2
RP s
s
2
2 Cp
sz 1/(RP CP )
wn
I p K VCO
RP
,
2 Cp
2
I p Cp KVCO
2
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 51
CPPLL Stability Issues
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 52
CPPLL Control Ripple
0.1CP C2 0.2CP
IIT Mandi, Even Semester (Analog CMOS & beyond)
PLL # 53