Synchronous Positive edge T Flip-Flop with Reset and Clock enable
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF_VHDL is
port( T: in
std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end T_FF_VHDL;
architecture Behavioral of T_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if Clock'event and Clock='1' then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if T='0' then
temp <= temp;
elsif T='1' then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
Decoder VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
port
(
Sel : in std_logic_vector(2 downto 0);
y : out std_logic_vector(7 downto 0)
);
end entity Decoder;
architecture Behavioral of Decoder is
begin
y <= "00000001" when Sel="000" else
"00000010" when Sel="001" else
"00000100" when Sel="010" else
"00001000" when Sel="011" else
"00010000" when Sel="100" else
"00100000" when Sel="101" else
"01000000" when Sel="110" else
"10000000";
end architecture Behavioral;
Multiplexer VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer_VHDL is
port
(
a, b, c, d, e, f, g, h : in std_logic;
Sel : in std_logic_vector(2 downto 0);
Output : out std_logic
);
end entity Multiplexer_VHDL;
architecture Behavioral of Multiplexer_VHDL is
begin
process (a, b, c, d, e, f, g, h, Sel) is
begin
case Sel is
when "000"
=> Output <= a;
when "001"
=> Output <= b;
when "010"
=> Output <= c;
when "011"
=> Output <= d;
when "100"
=> Output <= e;
when "101"
=> Output <= f;
when "110"
=> Output <= g;
when others => Output <= h;
end case;
end process;
end architecture Behavioral;
Priority Encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Priority_Encoder_VHDL is
port ( Sel : in std_logic_vector(3 downto 0);
encoded_data : out std_logic_vector(1 downto 0);
D : out std_logic);
end entity Priority_Encoder_VHDL;
architecture Behavioral of Priority_Encoder_VHDL is
begin
encoded_data <= "11" when Sel(3)='1' else
"10" when Sel(2)='1' else
"01" when Sel(1)='1' else
"00";
D <= '0' when Sel="0000" else '1';
end architecture Behavioral;
4-Bit Adder with Carry Out VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Adder is
port
(
nibble1, nibble2 : in unsigned(3 downto 0);
sum
: out unsigned(3 downto 0);
carry_out : out std_logic
);
end entity Adder;
architecture Behavioral of Adder is
signal temp : unsigned(4 downto 0);
begin
temp <= ("0" & nibble1) + nibble2;
-- OR use the following syntax:
-- temp <= ('0' & nibble1) + ('0' & nibble2);
sum
<= temp(3 downto 0);
carry_out <= temp(4);
end architecture Behavioral;
4x4-Bit Multiplier VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Multiplier_VHDL is
port
(
Nibble1, Nibble2: in std_logic_vector(3 downto 0);
Result: out std_logic_vector(7 downto 0)
);
end entity Multiplier_VHDL;
architecture Behavioral of Multiplier_VHDL is
begin
Result <= std_logic_vector(unsigned(Nibbl1) * unsigned(Nibble2));
end architecture Behavioral;
Synchronous Positive Edge Triggered D Flip-Flop with Active-High
Reset, Preset, and Clock Enable
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_FF_VHDL is
port
(
clk : in std_logic;
rst : in std_logic;
pre : in std_logic;
ce
: in std_logic;
d : in std_logic;
q : out std_logic
);
end entity D_FF_VHDL;
architecture Behavioral of D_FF_VHDL is
begin
process (clk) is
begin
if rising_edge(clk) then
if (rst='1') then
q <= '0';
elsif (pre='1') then
q <= '1';
elsif (ce='1') then
q <= d;
end if;
end if;
end process;
end architecture Behavioral;
Synchronous Positive edge T Flip-Flop with Reset and Clock enable
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF_VHDL is
port( T: in
std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end T_FF_VHDL;
architecture Behavioral of T_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if Clock'event and Clock='1' then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if T='0' then
temp <= temp;
elsif T='1' then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
Synchronous Positive edge JK Flip-Flop with Reset and Clock enable
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JK_FF_VHDL is
port( J,K: in
std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end JK_FF_VHDL;
architecture Behavioral of JK_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
4-Bit Binary Up/Down Counter with Parallel Load
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_VHDL is
port( Number: in std_logic_vector(0 to 3);
Clock: in std_logic;
Load: in std_logic;
Reset: in std_logic;
Direction: in std_logic;
Output: out std_logic_vector(0 to 3) );
end Counter_VHDL;
architecture Behavioral of Counter_VHDL is
signal temp: std_logic_vector(0 to 3);
begin
process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif ( Clock'event and Clock='1') then
if Load='1' then
temp <= Number;
elsif (Load='0' and Direction='0') then
temp <= temp + 1;
elsif (Load='0' and Direction='1') then
temp <= temp - 1;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
4-Bit BCD Up Counter with Clock Enable
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter2_VHDL is
port( Clock_enable: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
Output: out std_logic_vector(0 to 3));
end Counter2_VHDL;
architecture Behavioral of Counter2_VHDL is
signal temp: std_logic_vector(0 to 3);
begin
process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif(Clock'event and Clock='1') then
if Clock_enable='0' then
if temp="1001" then
temp<="0000";
else
temp <= temp + 1;
end if;
else
temp <= temp;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
4-Bit Shift Register
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Shift_register_VHDL is
port( Clock: in std_logic;
L,w: in std_logic;
Output: out std_logic_vector(3 downto 0);
Input: in std_logic_vector( 3 downto 0));
end Shift_register_VHDL;
architecture Behavioral of Shift_register_VHDL is
signal temp: std_logic_vector(3 downto 0);
begin
process
begin
wait until Clock'event and Clock='1';
if L='1' then
temp <= Input;
else
for i in 0 to 2 loop
temp(i) <= temp(i+1);
end loop;
temp(3) <= w;
end if;
end process;
Output <= temp;
end Behavioral;
