Laboratory Manual

PART I

VLSI Technology and Design

B. E. SEMESTER: VI

Electronics & Communication Engineering

GOVERNMENT ENGINEERING COLLEGE, DAHOD
(GUJARAT TECHNOLOGICAL UNIVERSITY)
Term Date: 21-1-2013 to 18-5-2013

Prepared by: Prof. S. B. Prajapati

Lab-Manual (VLSI Technology and Design)

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Page 1

INDEX
Sr.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Title of the experiment

Date

Sign

Marks

Implementation of Basic Digital Gates

using VHDL
Implementation of Boolean Logic
functions using VHDL
Implementation of 1-bit Half-Adder
and Full-Adder using VHDL
Implementation of 4-bit Full-Adder in
VHDL using different methodology
Use of PROCESS statementImplementation of Basic Digital Gates
Implementation of 4-bit Comparator
in VHDL
Implementation of BCD Generator &
BCD-to-7-Segment Decoder
Implementation of Multiplexers using
VHDL
Implementation of Decoders using
VHDL
Implementation of a Priority Encoder
using VHDL
Implementation of various Flip-Flops
using VHDL
Implementation of 4-Bit Shift Register
using VHDL
Implementation of 4-bit Binary UpCounter
Finite State Machine (FSM) based
Design

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Page 2

Practical 1
Implementation of Basic Digital Gates using VHDL

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Page 3

TO IMPLEMENT THE AND GATE USING VHDL

VHDL PROGRAM:
LIBRARY IEEE;
ENTITY AND2 IS
PORT ( A,B : IN
BIT;
Y : OUT BIT);
END AND2;
ARCHITECTURE ANDGATE OF AND2 IS
BEGIN
Y <= A AND B;
END ANDGATE;

SYMBOL:

RTL VIEWER:

DELAY MATRIX:

Y~0
A
B

OUTPUT WAVEFORM:

FLOOR PLAN EDITOR:

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Page 4

TO IMPLEMENT THE OR GATE USING VHDL

VHDL PROGRAM:
LIBRARY IEEE;
ENTITY OR2 IS
PORT (A,B : IN
BIT;
Y : OUT BIT );
END OR2;
ARCHITECTURE ORGATE OF OR2 IS
BEGIN
Y <= A OR B;
END ORGATE;

SYMBOL:

RTL VIEWER:

DELAY MATRIX:

Y~0
A
B

OUTPUT WAVEFORM:

FLOOR PLAN EDITOR:

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Page 5

TO IMPLEMENT THE NAND GATE USING VHDL

VHDL PROGRAM:
LIBRARY IEEE;
ENTITY NAND2 IS
PORT (A,B : IN
BIT;
Y : OUT BIT);
END NAND2;
ARCHITECTURE NANDGATE OF NAND2 IS
BEGIN
Y <= A NAND B;
END NANDGATE;

OUTPUT WAVEFORM:

*****************************************************
TO IMPLEMENT THE NOR GATE USING VHDL
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY NOR2 IS
PORT (A,B : IN
BIT;
Y : OUT BIT);
END NOR2;
ARCHITECTURE NORGATE OF NOR2 IS
BEGIN
Y <= A NOR B;
END NORGATE;

OUTPUT WAVEFORM:

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Page 6

TO IMPLEMENT THE XOR GATE USING VHDL

VHDL PROGRAM:
LIBRARY IEEE;
ENTITY XOR2 IS
PORT (A,B : IN
BIT;
Y : OUT BIT);
END XOR2;
ARCHITECTURE XORGATE OF XOR2 IS
BEGIN
Y <= A XOR B;
END XORGATE;

OUTPUT WAVEFORM:

*******************************************************
TO IMPLEMENT THE XNOR GATE USING VHDL
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY XNOR2 IS
PORT (A,B : IN BIT;
Y : OUT BIT);
END XNOR2;
ARCHITECTURE XNORGATE OF XNOR2 IS
BEGIN
Y <= A XNOR B;
END XNORGATE;

OUTPUT WAVEFORM:

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Page 7

Practical 2
Implementation of Boolean Logic functions using
VHDL

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Page 8

Function-1
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY example1 IS
PORT (x1, x2, x3 : IN BIT ;
f : OUT BIT) ;
END example1;
ARCHITECTURE LogicFunc OF example1 IS
BEGIN
f <= (x1 AND x2) OR (NOT x2 AND x3);
END LogicFunc;

OUTPUT WAVFORM:

FLOORPLAN EDITOR:

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Page 9

Function-2
VHDL PROGRAM:
LIBRARY IEEE;
ENTITY example2 IS
PORT ( x1, x2, x3, x4 : IN
BIT ;
f, g
: OUT BIT ) ;
END example2;
ARCHITECTURE LogicFunc OF example2 IS
BEGIN
f <= (x1 AND x3) OR (NOT x3 AND x2);
g <= (NOT x3 OR x1) AND (NOT x3 OR x4);
END LogicFunc;

OUTPUT WAVEFORM:

DELAY MATRIX:

FLOORPLAN EDITOR:

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Page 10

Lab-Manual (VLSI Technology and Design)

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Page 11

Practical 3
Implementation of 1-bit Half-Adder and Full-Adder
using VHDL

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Page 12

TO IMPLEMENT THE HALF ADDER USING VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Halfadd IS
PORT ( a, b : IN STD_LOGIC;
sum, cout : OUT
STD_LOGIC ) ;
END Halfadd;
ARCHITECTURE LogicFunc OF Halfadd IS
BEGIN
sum <= a XOR b;
cout <= a AND b;
END LogicFunc;

OUTPUT WAVEFORM:

TO IMPLEMENT THE FULL ADDER USING VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladd IS
PORT ( Cin, a, b : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC);
END fulladd;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
sum <= a XOR b XOR Cin;
cout <= (a AND b) OR (b AND Cin) OR (a AND Cin);
END LogicFunc;

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OUTPUT WAVEFORM:

DELAY MATRIX:

FLOORPLAN EDITOR:

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Page 14

Practical 4
Implementation of 4-bit Full-Adder in VHDL
using different methodology

TO IMPLEMENT THE FULL ADDER USING PACKAGE

TO IMPLEMENT THE FULL ADDER USING GENERATE STATEMENT

TO IMPLEMENT THE FULL ADDER USING LPM

TO IMPLEMENT THE ADDER LPM USING GENERIC

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Page 15

 TO IMPLEMENT THE FULL ADDER USING PACKAGE IN VHDL

PACKAGE DEFINITION
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE fulladd_package IS
COMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC;
s, Cout : OUT STD_LOGIC );
END COMPONENT;
END fulladd_package;

X(0)

X(1)

X(2)

X(3)

S(1)

S(2)

S(3)

S(0)

1 BIT
FULL
ADDER

Cin

Y(0)

1 BIT
FULL
ADDER

C0

Y(1)

1 BIT
FULL
ADDER

C1

Y(2)

1 BIT
FULL
ADDER

C2

Y(3)

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.fulladd_package.all;
ENTITY adder IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout : OUT STD_LOGIC);
END adder;
ARCHITECTURE Structure OF adder IS
SIGNAL C : STD_LOGIC_VECTOR(1 TO 3);
BEGIN
stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) );
stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) );
stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) );
stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout );
END Structure;

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Page 16

Cout

SYMBOL:

OUTPUT WAVEFORM:

DELAY MATRIX:

FLOORPLAN EDITOR:

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Page 18

TO IMPLEMENT THE FULL ADDER USING GENERATE STATEMENT

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.fulladd_package.all;
ENTITY adder_g IS
PORT ( Cin : IN STD_LOGIC;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout : OUT STD_LOGIC ) ;
END adder_g;
ARCHITECTURE Structure OF adder_g IS
SIGNAL C : STD_LOGIC_VECTOR(0 TO 4);
BEGIN
C(0) <= Cin;
Generate_label:
FOR i IN 0 TO 3 GENERATE
bit: fulladd PORT MAP ( C(i), X(i), Y(i), S(i), C(i+1) );
END GENERATE;
Cout <= C(4);
END Structure;

OUTPUT WAVEFORM:

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Page 19

TO IMPLEMENT THE FULL ADDER USING LPM

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY adderLPM IS
PORT ( Cin : IN STD_LOGIC;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout : OUT STD_LOGIC );
END adderLPM;
ARCHITECTURE Structure OF adderLPM IS
BEGIN
instance: lpm_add_sub
GENERIC MAP (LPM_WIDTH => 4)
PORT MAP (dataa => X, datab => Y, Cin => Cin, result => S, Cout => Cout );
END Structure;

OUTPUT WAVEFORM:

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Page 20

TO IMPLEMENT THE ADDER LPM USING GENERIC IN VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.fulladd_package.all;
ENTITY addern IS
GENERIC ( n : INTEGER := 4 );
PORT ( Cin : IN STD_LOGIC;
X, Y : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);
Cout : OUT STD_LOGIC);
END addern;
ARCHITECTURE Structure OF addern IS
SIGNAL C : STD_LOGIC_VECTOR(0 TO n);
BEGIN
C(0) <= Cin;
Generate_label:
FOR i IN 0 TO n-1 GENERATE
stage: fulladd PORT MAP ( C(i), X(i), Y(i), S(i), C(i+1) );
END GENERATE;
Cout <= C(4);
END Structure;

OUTPUT WAVEFORM:

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Page 21

Practical 5
USE OF PROCESS STATEMENT
Implementation of Basic Digital Gates

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Page 22

TO IMPLEMENT THE DIFFERENT GATES USING PROCESS

VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GATES IS
PORT( A,B,CLK : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0 );
Y : OUT STD_LOGIC);
END GATES;
ARCHITECTURE ALLGATES OF GATES IS
BEGIN
PROCESS (CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
CASE SEL IS
WHEN "000" =>
Y <= A AND B;
WHEN "001" =>
Y <= A OR B;
WHEN "010" =>
Y <= A NAND B;
WHEN "011" =>
Y <= A NOR B;
WHEN "100" =>
Y <= A XOR B;
WHEN "101" =>
Y <= NOT (A XOR B);
WHEN "110" =>
Y <= (NOT A) AND B;
WHEN "111" =>
Y <= (NOT A) AND (NOT B);
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS;
END ALLGATES;

OUTPUT WAVEFORM:

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FLOORPLAN EDITOR:

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Practical 6
Implementation of 4-bit Comparator in VHDL

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Page 25

TO IMPLEMENT THE COMPARATOR USING VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY compare IS
PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
AeqB, AgtB, AltB : OUT STD_LOGIC );
END compare;
ARCHITECTURE Behavior OF compare IS
BEGIN
AeqB <='1' WHEN A = B ELSE '0' ;
AgtB <= '1' WHEN A > B ELSE '0';
AltB <= '1' WHEN A < B ELSE '0';
END Behavior;

OUTPUT WAVEFORM:

DELAY MATRIX

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Page 26

FLOORPLAN EDITOR:

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Page 27

Practical 7
A. Implementation of BCD Generator using VHDL
B. Implementation of BCD-to-7-Segment Decoder

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Page 28

TO IMPLEMENT THE BCD GENERATOR USING VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY BCD IS
PORT ( X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) );
END BCD;
ARCHITECTURE Behavior OF BCD IS
SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL Adjust : STD_LOGIC;
BEGIN
Z <= ('0' & X) + Y;
Adjust <= '1' WHEN Z > 9 ELSE '0';
S <= Z WHEN (Adjust = '0') ELSE Z + 6;
END Behavior;

TO IMPLEMENT THE SEVEN SEGMENT DISPLAY USING VHDL

a
b
c
d
e
f
g

w0
w1
w2
w3

d
(b) 7-segment display

w3 w2 w1 w0
0
0
0
0
1
1
1
1
0
0

(a) Code

0
0
0
0
0
0
0
0
1
1

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1
0
1
1
0
1
1
1
1
1

1
1
1
1
1
0
0
1
1
1

1
1
0
1
1
1
1
1
1
1

1
0
1
1
0
1
1
0
1
1

1
0
1
0
0
0
1
0
1
0

1
0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
1
1

(c) Truth table

A BCD-to-7-segment display code converter

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Page 29

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY seg7 IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
leds : OUT STD_LOGIC_VECTOR(1 TO 7) );
END seg7;
ARCHITECTURE Behavior OF seg7 IS
BEGIN
PROCESS ( bcd )
BEGIN
CASE bcd IS
---- abcdefg
WHEN "0000" => leds <= "1111110";
WHEN "0001" => leds <= "0110000";
WHEN "0010" => leds <= "1101101";
WHEN "0011" => leds <= "1111001";
WHEN "0100" => leds <= "0110011";
WHEN "0101" => leds <= "1011011";
WHEN "0110" => leds <= "1011111";
WHEN "0111" => leds <= "1110000";
WHEN "1000" => leds <= "1111111";
WHEN "1001" => leds <= "1110011";
WHEN OTHERS => leds <= "-------";
END CASE;
END PROCESS;
END Behavior;

OUTPUT WAVEFORM:

DELAY MATRIX:

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Page 30

Practical 8
Implementation of Multiplexers using VHDL
2 to 1 MUX (Behavioral Level)
4 to 1 MUX (Behavioral Level)
16 to 1 MUX using Package (Structural Level)

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Page 31

TO IMPLEMENT 2 TO 1 MUX USING VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC;
f : OUT STD_LOGIC );
END mux2to1;
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN '0',
w1 WHEN OTHERS;
END Behavior;

SYMBOL:

OUTPUT WAVEFORM:

DELAY MATRIX:

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Page 32

TO IMPLEMENT 4 TO 1 MUX USING VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f : OUT STD_LOGIC );
END mux4to1;
ARCHITECTURE Behavior OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS;
END Behavior;

SYMBOL:

OUTPUT WAVEFORM:

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Page 33

TO IMPLEMENT 16 TO 1 MUX USING PACKAGE IN VHDL

PACKAGE DEFINITION
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mux4to1_package IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f : OUT STD_LOGIC );
END COMPONENT;
END mux4to1_package;

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VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
USE work.mux4to1_package.all;
ENTITY mux16to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15);
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
f : OUT STD_LOGIC );
END mux16to1;
ARCHITECTURE Structure OF mux16to1 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3);
BEGIN
Mux1: mux4to1 PORT MAP
( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) );
Mux2: mux4to1 PORT MAP
( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) );
Mux3: mux4to1 PORT MAP
( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) );
Mux4: mux4to1 PORT MAP
( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) );
Mux5: mux4to1 PORT MAP
( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f );
END Structure;

OUTPUT WAVEFORM:

DELAY MATRIX:

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Page 35

Practical 9
Implementation of Decoders using VHDL

2 to 4 Decoder (Behavioral Level)

3 to 8 Decoder (Behavioral Level)

4 to 16 Decoder using Component (Structural Level)

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Page 36

TO IMPLEMENT 2 TO 4 DECODER USING VHDL

VHDL PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity DECODER2T04 is
Port(W0,W1,E : in
STD_LOGIC;
S : out STD_LOGIC_VECTOR(3 DOWNTO 0));
End DECODER2T04;
Architecture DECODERLOGIC of DECODER2T04 is
Signal ENW : STD_LOGIC_VECTOR(2 DOWNTO 0);
Begin
ENW <=E & W1 & W0;
PROCESS (ENW)
Begin
CASE ENW is
when "100"
=>
S
when "101"
=>
S
when "110"
=>
S
when "111"
=>
S
when OTHERS
=>
S
End CASE;
End PROCESS;
End DECODERLOGIC;

<=
<=
<=
<=
<=

"0001";
"0010";
"0100";
"1000";
"0000";

OUTPUT WAVEFORM:

DELAY MATRIX:

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TO IMPLEMENT 3 TO 8 DECODER USING VHDL

VHDL PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Entity DECODER3T08 is
Port (W : in STD_LOGIC_VECTOR(2 DOWNTO 0);
E : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 DOWNTO 0));
End DECODER3T08;
Architecture DECODERLOGIC of DECODER3T08 is
Signal ENW : STD_LOGIC_VECTOR (3 DOWNTO 0);
Begin
ENW <= E & W;
PROCESS (ENW)
Begin
CASE ENW is
when "1000" => S <= "00000001";
when "1001" => S <= "00000010";
when "1010" => S <= "00000100";
when "1011" => S <= "00001000";
when "1100" => S <= "00010000";
when "1101" => S <= "00100000";
when "1110" => S <= "01000000";
when "1111" => S <= "10000000";
when OTHERS => S <= "00000000" ;
End CASE;
End PROCESS;
End DECODERLOGIC;

OUTPUT WAVEFORM:

DELAY MATRIX:

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TO IMPLEMENT 4 TO 16 DECODER USING COMPONENT

VHDL PROGRAM:
library IEEE;
use IEEE.STD LOGIC 1164.all;
Entity DECODER4T016 is
Port ( W : in STD_LOGIC_VECTOR(3 DOWNTO 0);
E : in STD LOGIC;
S : out STD_LOGIC_VECTOR(15 DOWNTO-0));
End DECODER4T016;
Architecture DECODERLOGIC of DECODER4T016 is
Signal EN : STD_LOGIC_VECTOR(l DOWNTO 0);
Component DECODER3T08
Port( W : in STD_LOGIC_VECTOR(2 DOWNTO 0) ;
E : in STD LOGIC'
S : out STD_LOGIC_VECTOR(7 DOWNTO 0));
End Component;
Begin
EN(0) <= E and (not W(3));
EN (1) <= E and W(3)
D1 : DECODER3T08 PORT MAP ( W(2 DOWNTO 0), EN(0), S(7 DOWNTO 0)) ;
D2 : DECODER3T08 PORT MAP ( W(2 DOWNTO 0), EN(1), S(15 DOWNTO 8)) ;
End DECODERLOGIC;

OUTPUT WAVEFORM:

DELAY MATRIX:

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Page 39

Practical 10
Implementation of a Priority Encoder using VHDL

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Page 40

TO IMPLEMENT A PRIORITY ENCODER USING VHDL

VHDL PROGRAM:
LIBRARY ieee;
USE ieee. std_logic_1164. all;
ENTITY priority_encoder IS
PORT ( X: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
f : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );
END priority_encoder;
ARCHITECTURE Behavior OF priority_encoder IS
BEGIN
f <= "000" WHEN X(0) = '1' ELSE
"001" WHEN X(1) = '1' ELSE
"010" WHEN X(2) = '1' ELSE
"011" WHEN X(3) = '1' ELSE
"100" WHEN X(4) = '1' ELSE
"101" WHEN X(5) = '1' ELSE
"110" WHEN X(6) = '1' ELSE
"111" WHEN X(7) = '1' ELSE
"000";
END Behavior;

OUTPUT WAVEFORM:

DELAY MATRIX:

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Practical 11
Implementation of various Flip-Flops using VHDL

D-type LATCH

D Flip-Flop

D Flip-Flop with Asynchronous Reset

SR Flip-Flop with Asynchronous Reset

JK Flip-Flop

T Flip-Flop

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IMPLEMENTATION OF D-LATCH
VHDL PROGRAM:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY D_latch IS
PORT ( D, clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END D_latch ;
ARCHITECTURE Behavior OF D_latch IS
BEGIN
PROCESS ( D, clk )
BEGIN
IF clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;

IMPLEMENTATION OF D-FLIP FLOP

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC);
END flipflop;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D;
END IF;
END PROCESS;
END Behavior;

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IMPLEMENTATION OF D-FLIP FLOP USING WAIT-UNTIL STATEMENT

VHDL PROGRAM:
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END flipflop;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock = '1';
Q <= D;
END PROCESS;
END Behavior;

IMPLEMENTATION OF D-FLIP FLOP WITH ASYNCHRONOUS RESET

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC );
END flipflop;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0';
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D;
END IF;
END PROCESS;
END Behavior;

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IMPLEMENTATION OF JK-FLIP FLOP

VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JKFFLOP IS
PORT ( J,K : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC );
END JKFFLOP;
ARCHITECTURE JKFFLOP_BEHV OF JKFFLOP IS
SIGNAL STATE : STD_LOGIC;
SIGNAL INPUT : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
INPUT<= J & K;
PROCESS (CLK, RESET)
BEGIN
IF (RESET='1') THEN
STATE <='0';
ELSIF (RISING_EDGE (CLK)) THEN
CASE (INPUT) IS
WHEN "11" => STATE<= NOT STATE;
WHEN "10" => STATE<= '1';
WHEN "01" => STATE<= '0';
WHEN "00" => STATE<= STATE;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
Q <= STATE;
Qn <= NOT STATE;
END JKFFLOP_BEHV;

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IMPLEMENTATION OF SR-FLIP FLOP

VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SRFFLOP IS
PORT ( S,R
CLK
RESET
Q, Qn
END SRFFLOP;

: IN STD_LOGIC;
: IN STD_LOGIC;
: IN STD_LOGIC;
: OUT STD_LOGIC);

ARCHITECTURE SRFFLOP_BEHV OF SRFFLOP IS

SIGNAL STATE : STD_LOGIC;
SIGNAL INPUT : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
INPUT<= S & R;
PROCESS (CLK, RESET)
BEGIN
IF (RESET='1') THEN
STATE <='0';
ELSIF (RISING_EDGE(CLK)) THEN
CASE (INPUT) IS
WHEN "00" => STATE <= STATE;
WHEN "01" => STATE <= '0';
WHEN "10" => STATE <= '1';
WHEN "11" => STATE <= 'Z';
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
Q <= STATE;
Qn <= NOT STATE;
END SRFFLOP_BEHV;

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IMPLEMENTATION OF T-FLIP FLOP

VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TFFLOP IS
PORT( Tin
CLK,RESET
Q,Qn
END TFFLOP;

: IN STD_LOGIC ;
: IN STD_LOGIC ;
: BUFFER STD_LOGIC);

ARCHITECTURE TFFLOP_ARCHI OF TFFLOP IS

SIGNAL STATE : STD_LOGIC;
BEGIN
PROCESS(CLK,RESET)
BEGIN
IF RESET ='1' THEN
STATE<='0';
ELSIF (RISING_EDGE(CLK)) THEN
IF Q='0' THEN
STATE<= Tin;
ELSIF Q='1'THEN
STATE<= NOT Tin;
END IF;
END IF;
END PROCESS;
Q<= STATE ;
Qn<= NOT STATE ;
END TFFLOP_ARCHI;

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Practical 12
Implementation of 4-Bit Shift Register using VHDL

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IMPLEMENTATION OF 4-BIT SHIFT REGISTER

VHDL PROGRAM:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shift4 IS
PORT ( w, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(1 TO 4) );
END shift4;
ARCHITECTURE Behavior OF shift4 IS
SIGNAL Sreg : STD_LOGIC_VECTOR(1 TO 4) ;
BEGIN
PROCESS (Clock)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Sreg(4) <= w ;
Sreg(3) <= Sreg(4);
Sreg(2) <= Sreg(3);
Sreg(1) <= Sreg(2);
END IF;
END PROCESS;
Q <= Sreg;
END Behavior;

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Practical 13
Implementation of 4-bit Binary Up-Counter

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IMPLEMENTATION OF 4-BIT BINARY UP-COUNTER

VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT4 IS
PORT ( RESETN
E, CLOCK
Q
END COUNT4;

: IN
STD_LOGIC;
: IN
STD_LOGIC;
: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

ARCHITECTURE BEHAVIOR OF COUNT4 IS

SIGNAL COUNT : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS (CLOCK, RESETN)
BEGIN
IF RESETN = '0' THEN
COUNT <= "0000";
ELSIF (CLOCK'EVENT AND CLOCK = '1') THEN
IF E = '1' THEN
COUNT <= COUNT + 1;
END IF;
END IF;
END PROCESS;
Q <= COUNT;
END BEHAVIOR;

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Practical 14
FINITE STATE MACHINE (FSM) DESIGN

MOORE FSM

MEALY FSM

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DESIGN STATEMENT:
1. The circuit has one input, w and one output z
2. All changes in the circuit occur on the positive edge of a clock signal
3. The output z equal to 1 if during two immediately preceding clock cycles the input
w was equal to 1. Otherwise the value of z equal to 0.
Sequences of input and output signals

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0

MOORE FSM METHOD

W

Combinational
circuit

Flip-flops

Combinational
circuit

Clock

STATE DIAGRAM
Reset
w = 1
w = 0

A z = 0

B z = 0
w = 0
w = 1

w = 0

C z = 1

w = 1

STATE TABLE

Present State
A
B
C

Next State
w=0
A
A
A

Lab-Manual (VLSI Technology and Design)

w =1
B
C
C

Out Put
z
0
0
1

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VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE IS
PORT ( CLOCK : IN STD_LOGIC ;
W : IN STD_LOGIC ;
RESETN : IN STD_LOGIC ;
Z : OUT STD_LOGIC );
END MOORE;
ARCHITECTURE BEHAVIOR OF MOORE IS
TYPE STATE_TYPE IS (A, B, C);
SIGNAL Y : STATE_TYPE;
BEGIN
PROCESS (RESETN, CLOCK)
BEGIN
IF RESETN = '0' THEN
Y <= A;
ELSIF (CLOCK'EVENT AND CLOCK = '1') THEN
CASE Y IS
WHEN A => IF W = '0' THEN
Y <= A;
ELSE
Y <= B;
END IF ;
WHEN B => IF W = '0' THEN
Y <= A;
ELSE
Y <= C;
END IF ;
WHEN C => IF W = '0' THEN
Y <= A;
ELSE
Y <= C;
END IF;
END CASE;
END IF;
END PROCESS;
Z <= '1' WHEN Y = C ELSE '0';
END BEHAVIOR;

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MEALY FSM METHOD

Combinational
circui

Flip-flops

Combinational
circuit

Clock

STATE DIAGRAM

Reset
w = 1z = 0
w = 0z = 0

w = 1 z = 1

w = 0z = 0

STATE TABLE

Present State

A
B

Next State
w=0
A
A

Lab-Manual (VLSI Technology and Design)

w =1
B
B

Out Put
z
w=0
w =1
0
1
0
1

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VHDL PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MEALY IS
PORT ( CLOCK, RESETN : IN STD_LOGIC;
W : IN STD_LOGIC;
Z : OUT STD_LOGIC);
END MEALY;
ARCHITECTURE BEHAVIOR OF MEALY IS
TYPE STATE_TYPE IS (A, B);
SIGNAL Y : STATE_TYPE;
BEGIN
PROCESS ( RESETN, CLOCK )
BEGIN
IF RESETN = '0' THEN
Y <= A;
ELSIF (CLOCK'EVENT AND CLOCK = '1') THEN
CASE Y IS
WHEN A =>
IF W = '0' THEN Y <= A;
ELSE Y <= B;
END IF ;
WHEN B =>
IF W = '0' THEN Y <= A;
ELSE Y <= B;
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS (Y, W)
BEGIN
CASE Y IS
WHEN A =>
Z <= '0';
WHEN B =>
Z <= W;
END CASE;
END PROCESS;
END BEHAVIOR;

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