Systems Architecture, Programming and Design Second EditionTata McGraw-Hill Published hy the Tata MeGraw-Hill Publishing Company Limited "7 West Patel Nagas, New Delhi 110 008. Copyright © 2008 by Tata McGraw-Hill Publishing Company Limited NNo part of this publication may be reproduced or dsuibuted in any form or by any means, electron, mechanical, ‘hotocopying, recording, or otherwise or stored ina database or retrieval system without the prior writen permission of the publishers. The program listing (i any) may be entered, stored and executed in a computer system, but they may not be reproduced for publication. “This edition ean be exported from India only by the publishers, Tata MoGraw-Thil Publishing Company Limite. ISBN 13: 978-0-07-066764-8 ISBN 10: 0-07-066764-0 Managing Ditector: Ajay Shukla General Manager: Publishing—SEM & Tech Ed Vibha Mahajan Sponsoring Editor: Shalini Jha Jk. Sponsoring Eaitor: Nianjan Chakravarty Executive—Ealtorial Services: Sohini Mukherjee Production Executive: Suneeta S Bohra Goneral Manager: Marketing —Higher Education & School: Michael J Cruz Product Manager: SEM & Tech Ed: Biju Ganesan CConiroller—Prextuction: Rajender P Ghansela ‘Asst. General Manager—Production: tL Dogra Information contained inthis work has been obtained by Tata MeGraw- Hil, rom sourees believed to be reliale However, neither Tata McGraw-Hill nor its authors guarantee the accuracy or completeness of any information published herein, and nether Tata McGraw-Hill nor its authors shall be responsible for any errors, omissions, or ‘damages using Ou of use ofthis information, This work i published with the understanding that Tara MeGrass-TlL and its authors are supplying information but are not attempting to render engineering or other professional services. such services are required, the asistanee of an appropriate professional should be sought Published by the Tata McGraw-Hill Publishing Company Limited, 7 West Patel Nagar, New Dethi 110 008, sypeset at ‘Bukprint Indi, B-180A, Guru Nanak Pura, Laxmi Nagar-110 092 and printed at SDR Printers, A-28, West Jyoti Naga, Loni Road, Shabdara, Delhi 10-094 Cover: SDR Printers DDXLCRAXRYARDContents Proface tothe Second Editon Preface tothe First Eation 1, Introduction to Embedded Systems 1.1 Embedded Systems. 3 1.2 Processor Embedded into a System 5 1.3 Embedded Hardware Units and Deviees ina System 10 4 Embedded Software ina System 19 1-5 Examples of Embedded Systems 27 1.6 Embedded System-on-chip (Soc) and Use of VLSI Cireuit Design Technology 29 1.7 Complex Systems Design and Processors 32 LR Design Process in Embedded System 37 1.9 Formalization of Sysiem Design 42 1.10 Design Process and Design Examples 43 LLL Classification of Embedded Systems 52 1.12. Skills Required for an Embedded System Designer 53 2 $0SI and Advanced Processor Architectures, Memory Organization and Real-world Interfacing 2.1 S051 Architecture 62 Real World Inerfcing 72 Introduction to Advanced Architectures 84 24 Processor and Memory Organization 96 25 Instruction-Level Parallelism 104 26 Performance Metties 106 2.7 Memory-Types. Memory-Maps and Addresses 106 28 Processor Sclection 1/3 29 Memory Selection 18 3. Devices and Communication Buses. for Devices Network 3.1 10 Types and Examples 130 32 Serial Communication Devices 134 33 Parallel Device Ports 143 3.4. Sophisticated Imerfucing Features in Device Ports 150 35 Wireless Devices /57 346 Timer and Counting Devices 152 37 Watchdog Timer 157 38 Real Time Clock [58 39. Networked Embedded Systems 159 3.10 Serial Bus Communication Protocols 160 3.11, Parallel Bus Device Protocols—Parallel Communication Network Using ISA. PCI, PCL-X and Advanced Buses 166 {12 Internet Enabled Systems—Network Protocols 170 3.13 Wireless and Mobile System Protocols 175 4. Device Drivers and Interrupts Service Mechanism 4.1 Programmed-V/O Busy-wait Approach without Interupt Service Mechanism 189Contents 42 ISR Concept 192 43 Interrupt Sources 200 44 Inverrpt Servicing (Handling) Mechanism 203 45 Multiple Interupts 209 46 Context and the Periods for Context Switching, Interrupt Latency and Deadline 217 4.7 Clasifcation of Processors Interupt Service Mechanism from Context Saving Angle 217 48 Direct Memory Access 218 49 Device Driver Programming 220 5. Programming Concepts and Embedded Programming in C, C++ and Java 2M 5.1, Software Programming in Assembly Language (ALP) and in High-Level Language “C235 52. C Program Elements: Header and Source Files and Preprocessor Directives 237 53. Program Elements: Macros and Functions 239 $544 Program Elements: Data Types, Data Structures, Modifies, Statements, Loops and Pointers 247 55 Object Oriented Programming 262 5.6 Embedded Programming inC++ 263 5.7 Embedded Programming in Java 26 6. Program Modeling Concepts 273 6.1 Program Models_274 62. DFG Models 277 63 State Machine Programming Models for Event-controlied Program Flow | 282 64 Modeling of Multiprocessor Systems 288 65 UML Modelling 295 7. Interprocess Communication and Synchronization of Processes, Threads and Tasks 303 7.1. Multiple Processes in an Application 305 712 Multiple Threads in an Application | 306 73 Tasks 308 TA Task States 308 75 Tusk and Data 310 716 Cleat-cut Distnetion between Functions, ISRS and Tasks by their Characteristics 317 7.7 Concept of Semaphores 314 78 Shared Data 326 79 Interprocess Communication 330 7.10 Signal Function 332 TAL Semaphore Functions 334 7.12 Message Quoue Functions 335 7.13. Mailbox Funetions 337 7.14. Pipe Functions 339 71S Socket Functions 34 7.16 RPC Functions 345 8. Real-Time Operating Systems 350 BIOS Services 351 82 Process Management 355 83 Timer Funetions 356 84 Event Functions 358 85 Memory Management 35910. 2 13. MW 86 Device, Fle and 10 Subsystems Mansgement | 361 8.7 Interrupt Routines in RTOS Environment and Handling of Inerrupt Source Calls 366 88 Realtime Operating Systems 370 89 Basic Design Using an RTOS 372 8.10 Rios Task Scheduling Models, Interupt Lateney and Response ofthe Tasks as Performance Metrics 385 8.11 OS Security Issues 401 Real-time Operating System Programming-T: MicrocOS-11 and VxWorks 19.1, Basie Funetions and Types of RTOSES. 408 9.2 RTOS mCOS 410 93 RTOS VxWorks 453 Real-time Operating System Programming-it: Windows CE, OSEK and Real Linux Functions 10.1 Windows CE 478 102 OSEK 494 10.3 Linux 2.6. and RTLinox 496 Design Examples and Case Studies of Program Modeling and Programming with RTOS-1 1.1 Case Study of Embedded System Design and Coding for an Automatic 512 ‘Chocolate Vending Machine (ACVM) Using Mucos RTOS 11.2. Caso Study of Digital Camera Hardware and Sofware Architecture $37 11.3 Case Study of Coding for Sending Application Layer Byte Streams on a ‘TCPAP Network Using RTOS Vaworks 537 Design Examples and Case Studies of Program Modeling and Programming with RTOS2 12.1 Case Study of Communication Between Orchestra Robots 567, 12.2 imbedded Systems in Automobile 574 123 Case Study of an Embedded System for an Adaptive Cruise Contwol (ACC) System in a Car $77, 124 Case Study of an Embedded System fora Smart Card $92 125 Case Study of a Mobile Phone Software for Key Inputs 604 Embedded Software Development Process and Tools 13.1 Introduction to Embedded Software Development Process and Tools 620 13.2 Host and Target Machines 62. 133 Linking and Locating Software 626 134 Getting Embedded Softwae into the Target System 630) 133 sues in Hardware-Sortware Design and Co-design 636 ‘Testing, Simulation and Debugging Techniques and Tools 14.1 Testing on Host Machine 619 142 Simulators 650 143 Laboratory Tools 653 Appendix 1: Roadmap for Various Course Stulies Append 2: Select Bibliography Indes a7 su ois S88Walkthrough Simple approach with interesting ‘examples and figures ‘Simple approach with figures to ‘explain complex topic of system. ‘on chip for a mobile phoneWalkthrough ‘Summary, keywords and their definitions, review questio + and practice exercises in ‘chapterti @ eT a Simple way of point-wise presentation of the details by Using lists and tables(=) Waktough eat aan “a ORT TT TTRS weer aneees Explains modeling of programs and software angineating practices for system dasign by ‘case studies of sysiems for automatic chocolate vending machine, digital camera, TCP/ IP stack creation, robot orchestra, automatic cruise control, smart card and mobile phoneta =) 8 — Comprehensive explanation with coding examples for learning the widely used RTOSes- mCOS-II, VxWorks, Windows CE, OSEK and Real Time LinuxAppendix 2: Select Bibliography Walkthrough stalled selected bibliography of books, journal references and important web links at end of the book to facilitate building a startup library for references and further studies in Embedded Systems - :Introduction to Embedded Systems eS +2eaaRs GRR AOMS BO Section 1.1 Definitions of system and embedded system Section 1.2 The processing unit of an embedded system consists of 1. A processor 2. Commonty used microprocessors 3. Application-specific instruction set processors (ASIPs), ‘microcontrollers, DSPs and others 4. Single purpose processors Section 1 The hardware unit of an embedded system consists of I. An embedded system power source with controlled powers dissipation 2. Aclock oscillator circuit and clocking unit that lets a processor execute instructions 3. Timers and a real time clock (RTC) for various timing needs of the system Reset circuit and watchdog timer System and external memories System inpur owsput (10) ports, serial, parallel and wireless ‘communication, serial Universal Asynchronous Receiver and Transmitter (UART) and other port protocols and buses 7. Devices such as Digital to Analog Converter (DAC) using Pulse Width Modulation (PWM), Analog to Digital Converter (ADC), Light Emitting Diode (LED) and Liquid Crystal Display (LCD) units, keypad and keyboard, touch screen, pulse dialer, modem and transceiver 8. Mutiplexers, demubiplexers, decoder for interfacing of the devices and busesa £ A ERS N 1 N G Bo Smee HORS 9 Interrupt controller (handler) Section 1.4 1. Languages that are used 10 develop embedded software jor a system 2. Program models 3. Multitasking using an operating system (OS), system device drivers, device ‘management and real time operating system (RTOS) 4. Software tools for system design Section 1.5 Examples of applications of embedded systems Section 1.6 Designing an embedded system on a VLSI chip 1. Embedded SoC (System on Chip) and examples of its applications 2. Uses of Application Specific Instruction Set Processor (ASIP) and Intellectual Property (IP) core 3. Field Programmable Gate Array (FPGA) core with single or multiple processor units on an ASIC chip Section 1.7, The complex system consists of 1, Embedded microprocessors or GPPs in complex systems 2. Embedding ASIPs, microconurollers, DSPs, media and network processors 3. Embedding application-specific system processors (ASSP3) 4. Embedding multiple processors in systems Section 1.8 The design process has 1. Challenges in embedded system design 2. Design metrics optimization 4. Cordesign of hardware and software components Section The system design formalism is defined Section 1.10 The design of embedded hardware and software in an automatic chocolate vending ‘machine, smart card, digital-camera, mobile phone, mobite computer and robot are aiven as examples Section Classification of embedded systems into three types Section 1.12 Skills needed to design an embedded systempe & “1.1 “EMBEDDED SYSTEMS 1.1.1 System Assystem is a way of working, organizing or doing one or many tasks according t a fixed plan, program, or set of rules, A system is also an arrangement in which all its units assemble and work together according to the plan or program. Consider a watch, It is a time-display system. Its parts are its hardware, needles and battery with the ‘beautiful dial, chassis and strap. These parts organize to show the real time every second and continuously "update the time every second. The system-program updates the display using three needles after each second. Ir follows. set of rales. Some of these rules are as follows: () All needles move only clockwise. (ji) A thin and Tong needle rotates every second such that it retums to same position after a minute. (ii) A long needle rotates every minute such that it returns to same position after an hour. (iv) A short needle rotates every hour such that it returns to same position after twelve hours. (¥) All three needles return to the Same inclination after twelve hours each day. Consider a washing machine. It is an automatic clothes-washing system. The important hardware parts include its status display panel, the switches and dials for user-defined programming, a motor to rotate or spin, its power supply and control unit, an inner water-level sensor, a solenoid valve for letting water in and another valve for letting water drain out. These parts organize to wash clothes automatically according to a program preset by a user. The system-program is activated to wash the dirty clothes placed in a tank, which rotates or spins in preprogrammed steps and stages. It follows a set of rules. Some of these rules are as follows: () Follow the steps strictly in the following sequence. Step T: Wash by spinning the motor according to a programmed period. Step II: Rinse in fresh water after draining out the dirty water, and rinse a second ‘ime ifthe system is not programmed in water-saving mode, Step III: After draining out the water completely, spin the motor fast For a programmed period for drying by centrifuging out water from the clothes, Step IV: Show the wash-over status by a blinking display. Sound the alarm for a minute to signal that the wash cycle is ‘complete. (i) At each step, display the process stage of the system. (ii) In ease of an interruption, execute ‘only the remaining part of the program, starting from the position when the process was interrupted. There ‘ean be no repetition from Step Tunless the user resets the system by inserting anothe the program, 1.1.2 Embedded System Definition One of the definitions of embedded system is as follows: “An embedded system is a system that has embedded software and computer-hartware, which makes it 4a system dedicated for an applications) or specific part of an application or product or a part ofa larger sysiem” Embedded systoms have heen defined in books published recently in Several ways. Given helow isa series ‘of definitions from others in the field Wayne Wolf author of Computers as Components ~ Principles of Embedded Computing System Design: “What is an embedded computing system? Loosely defined, itis any device that includes a programmable ‘computer but isnot itself intended to bea general-purpose computer” and “a fax machine ora clock built from ‘a microprocessor is an embedded computing system”.(4) Embed Sytem ‘Todd D. Morton author of Embedded Microconirollers: “Embedded Systems are electronic systems that ‘contain a microprocessor or microcontroller, but we do not think of them as computers—the computer is hidden or embedded in the system.’ David E. Simon author of An Embedded Software Primer: “People use the ‘any computer system hidden in any of these products.” ‘Tim Wilmshurst author of An Introduction to the Design of Small Scale Embedded Systems with examples from PIC, 80C51 and 68HCOS/08 microcontrollers: (1) “An embedded system is a system whose principal function is not computational, but which is controlled by a computer embedded within it, The computer is likely to be a microprocessor or microcontroller. The word embedded implies that it lies inside the overall system, hidden from view, forming an integral part of [the] greater whole”, (2) “An embedded system is a ‘microconiroller-based, software-driven, reliable realtime control system, autonomous, or human- oF network- interactive, operating on diverse physical variables and in diverse environments, and sold into a competitive and cost-conscious market”. sm embedded system to mean ‘A computer is a system that has the Following or more components, 1. A microprocessor 2. A large memory of the following two kinds: (a) Primary memory (semiconductor memories: Random Access Memory (RAM), Read Only Memory (ROM) and fast accessible caches) (b) Secondary memory [(magnetic memory located in hard disks, diskettes and cartridge tapes, optical memory in CD-ROMSs or memory sticks (in mobile computers)] using which different user programs can be loaded into the primary memory and run VO units such as touch sereen, modem, fax eum modem, et. Input units such as keyboard, mice, digitizer, scanner, ee Output units such as an LCD screen, video monitor, printer, ete. [Networking units such as an Ethernet cand, front-end processor-hased server, bus drivers, ete ‘An operating system (OS) that has general purpose user and application software in the secondary ‘memory ‘An embedded system is a system that has three main components embedded into it: 1, Itembeds hardware similar to « computer. Figure 1.1 shows the units in the hardware of an embedded system. Asits sofware usually embeds in the ROM or flash memory, it usually do not need a secondary hard disk and CD memory as in a computer embeds main application software. The application software may concurrently perform a series of tasks of processes or threads 3. Itembeds a real-time operating system (RTOS) that supervises the application software running on hardware and organizes access 0 a resource according to the priorities of tasks in the system. It provides a mechanism to let the processor run a process as scheduled and context-switch between the various processes. (The concept of process, thread and task explained later in Sections 7.1 to 7.3.) It sets the rules during the execution of the application software, (A small-scale embedded system may not embed the RTOS.) Characteristics An embedded system is characterized by the following: (1) Real-time and muhirate «operations define the way’ in which the system works, reacts to events, interrupts and schedules the system's funetioning in realtime. It does so by following a plan to control latencies and to meet deadlines, (Latency refers tothe waiting period between running the eodes ofa task or interrupt servige routine and the instance {a which the need for the task or interrupt fom an event arses). The different operations may take place atpe & Input Devices Interfacing! Driver Ccuits Momory Processor ‘Menars Memory ‘Serial Communi- caton Pons Timers Iotorupt Parale! Conttoter Ports Power Supply, Reset and Osollator Crete ‘System Application Specie Circuits (Outputs interfacing! Driver Circus Fig. 1.1 The components of embedded system hardware distinct rates. For example, audio, video, data, network stream and events have different rates and time constraints. (2) Complex algorithms. (3) Complex graphic user interfaces (GUIs) and other user interfaces. (4) Dedicated functions. Constraints An embedded system is designed keeping in view three consrants: (1) avaiable system memory, (2) available processor speed, (3) the need to limit power dissipation when running the system continuously in cycles of ‘wait for events’, ‘run’, ‘stop’, ‘wake-up’ and ‘sleep’, ‘The system design or an embedded system has constraints with regard to performance, power, size and design and manfaetaring costs. ™ 1.2 “PROCESSOR EMBEDDED INTO A SYSTEM ‘A processor is an important unit in the embedded system hardware, It is the heart of the embedded system, Knowledge of basic concept of microprocessors and microcontrollers is must for an embedded system designer. ‘A reader may refer to a standard text or the texts listed in the “References” at the end of this book for an in= depth understanding of mieroprocessors, microcontrollers and DSPs that are incorporated in embedded system design. Chapter 2 will explain 8051 and a few processors. 1.2.1 Embedded Processors in a System A processor has two essential units: Program Flow Control Unit (CU) and Execution Unit (EU). The CU includes a fetch unit for fetching instructions from the memory, The EU has circuits that implement the instructions pertaining to data transfer operations and data conversion from one form to another. The EU ineludes the Arithmetic and Logical Unit (ALU) and also the circuits that execute instructions for a program(6) Embed Sytem control task, say, halt, interrupt, or jump to another set of instructions. It can also execute instructions fora call or branch to another program and for a eal to a function. A processor runs the cycles of fetch-and-execute. The instructions, defined in the processor instruction set, are executed in the sequence that they are fetched from the memory. A processor is in the form of an IC chip: alternatively, it could be in core form in an Application Specific Integrated Circuit (ASIC) or ‘System on Chip (SoC). Core means a part of the functional circuit on the Very Large Seale Integrated (VLST) chip. ‘An embedded system processor chip or core can be one of the following 1. General Purpose Processor (GPP): A GPP is a general-purpose processor with instruction set designed not specific to the applications (a) Microprocessor. Section 1.2.2) (b) Embedded Processor [Section 1.7.7] Application Specific Instruction-Set Processor (ASIP). An ASIP is a processor with an instruction set designed for specific applications on a VLSI chip. {a) Microcontroller [Seetion 1.2.3] (b) Embedded microcontroller [Section 1.7.7] (c) Digital Signal Processor (DSP) and media processor [Section 1.7.3] (d)_ Network processor, IO processor or domain-specific programmable processor 3. Single Purpose Processors as additional processors: Single purpose processor examples are as follows: (1) Coprocessor (e.g. used for graphic processing, floating point processing, encrypting, deciphering, diserete cosine transformation and inverse transformation or TCP/P protocol stacking and network ‘connecting functions), (2) Accelerator (cg, Java codes accelerator) (3) Controllers (c.g. for peripherals, direct memory accesses and buses). [Section 1.7.7] GPP or ASIP cores integrated into either an ASIC ora VLSI circuit or a Field Programmable Gate Array (FPGA) core integrated with processor units in a VLST (ASIC) chip. [Sections 1.6 and 1.7] Application Specific System Processor (ASSP). [Section 1.7.9] Multicore processors or multiprocessor [Section 1.7] or a system designer, the following are important considerations when selecting a processor: Instruction set Maximum bits in an operand (8 or 16 or 32) in a single arithmetic or logical operation ‘Clock frequency in MHz and processing speed in Million Instruetions Per Second (MIPS) or in an alternate mettie Dirystone for measuring processing performance (Section 2.6] 4. Processor ability to solve complex algorithms while meeting deadlines for their processing A microprocessor or GPP is used because: (3) processing based on the instructions available in a predefined general purpose instruction set results in quick system development. (ii) Once the board and 1 interfaces are designed for a GPP, these ean be used for a new system by just changing the embedded software in the ROM. (iii) Ready availability of a compiler facilitates embedded software development in high-level languages. (iv) Ready availability of well-tested and debugged processor-specific APIs (Application Program Interfaces) and codes previously designed for other applications results in new systems developed quickly. Fi 1.2.2 Microprocessor The CPU is unit that centrally fetches and processes a set of general-purpose instructions. The CPU instruction set includes instructions for data transfer operations, ALU operations, stack operations, 10 operations andIntroduction to Embedded Systems. program control, sequencing and supervising operations. The general-purpose instruction set is always specific to a specific CPU. Any CPU must possess the following basic functional units 1. A control unit that fetches and controls the sequential processing of a given command or instruction and communicates with the rest of the system, 2. An ALU that undertakes arithmetic and logical operations on bytes or words. It may be capable of processing 8, 16, 32 or 64-bit words at an instant A mieroprocessor is a single VLSI chip that has CPU and may also have some other units (e.g., caches, floating point processing arithmetic unit, pipelining and superscaling units) that are additionally present and ‘that result in faster processing of instructions, ‘The earlier generation microprocessor’s fetch-and-execute cycle was guided by a clock frequency of the order of ~4 MHz. Processors now operate at a clock frequency of 4 GHz and even have multiple cores. In early 2002, it became possible to design Gbps (Giga bit per second) transceiver and encryption engines in a ‘ew highly sophisticated embedded systems using processors that operate on GHz frequencies. A 1 isa wansmitting cum receiving circuit that has appropriate processing and controls units, for example, for controlling bus-collisions. An enetyption engine is a system that encrypts the data to be transmitted on the network Intel 80x86 (also referred as x86) processors are the 32-bit successors of 8086. (The x here refers to an {8086 extended for 32 bits] Examples of 32-bit processors in 80x86 series are Intel $0386, $0486 and Pentiums (a new generation of 32- and 64-bit microprocessors is the classic Pentiuin series). IBM PCs use 80x86 series and the embedded systems incorporated inside the PC for specific tasks (like graphic accelerator, disk controllers, network interface card) use these microprocessors. High performance processors have pipeline and superscalar architecture, fast ALUs and Floating Point Processing Units (FLPUS). [A pipeline architecture means thatthe instructions have between 3 and 9 stages. Different instructions are at different stages of the pipeline at any given instance. A superscalar architecture refers to wo oF more sets oF instructions executing in parallel pipelines.) ‘The imporant microprocessors used in the embedded systems are ARM, 68HCxxx, 80x86 and SPARC family of microprocessors Section 1.7 will describe the embedding of a microprocessor GPP in complex systems, A microprocessor is used as general-purpose processor when large embedded software has to be located in the external memory chips. 1.2.3 Microcontroller ‘A microcontroller is an integrated chip that has processor, memory and several other hardware units in it these form the microcomputer part of the embedded system. Figure 1.2 shows the functional circuits present {in slid boundary boxes) ina microcontroller, Italso shows the application-specific units (in dashed boundary boxes) ina specific version of a given microcontoler family Just as a microprocessor isthe most essential part of a computing systom, a microcontroller isthe most essential component ofa contol or communication circuit. A microcontroller isa single-chip VLSI unit (also called “microcompater", which, though having limited computational capabilities, possesses enhanced input~ output capabilities and & number of on-chip functional units. [Refer to Section 1.3 for various functional hardware units.) Microcontrollers are particularly suited for use in embedded systems for wal-time contol applications with on-chip program memory and devices.Embed Sytem Functional Circuits in 8 Chip or Core of Microcontroller (Microcomputer) T Internal Hes ae FastvROM roeeea ane — Eapatvenat on rote Sev ART Sen a Tiras and con na Saar — a et oe Cemmaneston ‘Application Specific Circuits in Specific Versions 1 | Panter! 1 Ccontraler | Controller | ; t ig 1 1.2. Various functional circuits (solid boundary boxes) in a microcontroller chip or core in an embedded system. Also shown are the application-specific units (dashed boundary boxes) in a specific version of a microcontroller A few of the latest microcontrollers also have dual core and high computational and superscalar processing, capabilities, Important microcontroller chips for embedded systems ane 8051, 8051MX, 68HCIIxx, HC12xx, HCI6xx, PIC 16F84 or 16C76, 16F876 and PICI8, microcontroller enhancements of ARM9/ARM7 from ARM, Intel, Philips, Samsung and ST microelectronics. Figure 1.3 shows commonly used microcontrollers in small-, medium- and large-scale embedded systems. Choosing a microcontroller as a processing unit depends upon the application-specific features in A microcontroller is used when a small or part of the embedded software has to be located in the internal ‘memory and when on-chip functional units such as the interruptchandler, port, timer, ADC, PWM and CAN controller are required. 1.2.4 Single Purpose Processors Single purpose processors used in embedded systems inelude: 1. Coprocessor (For example, for floating point processing).pe & ‘Small Scale Embedded System B16 bit Microcentoler — [05 any cverex [racine] [ane -Mecium Seale Embedded System 16 bi Mierocontoler SSS ES aos x | | PIC 16F876, PicTe Hitachi D64F2623FA 6BHC12ex, BHC TE Large Seale Embedded System 32-b8 Microcontroller SSS a ‘ARM family Cortex-M3, Atmel ATO1 series, itachi SH7O45 C16x/ST1O series, Philips LPC 2000 series, ‘Texas Instrument, TI TMS470R181M, SamsungS3C44B0X 1.3 Commonly used microcontrollers in small-, medium- and large-scale embedded systems Graphics processor: An image consists of a number of pixels. For example, Quarter common intermediate Format—Quarter-CIF images have 144 x 176 (horizontal x-axis x vertical y-axis) pixels. Video frames. have 525 x 625 pixels. The video graphic adapter (VGA) format of e-mailing and web pages has {640 x 480 = 307,200 pixels. A separate graphics processor is required for functions such as, for example, ‘gaming, display from graphics memory buffers and to move translate on sereen) and rotate an image orits segments 3. Pixel coprocessor: High-resolution pictures have formats: 2592 x 1944 pixels = 5,038,848 pixels; 2502 x 1728 = 3,2 M; 2048 x 1536 = 3 M and 1280 x 960 = 1 M. A pixel coprocessor is required in digital cameras for displaying images directly or after operations such as rotate right, roate-Ieft,rotate- up, rotate-down, shift 19 next, shift to previous. 4. Eneryption engine: A suitable algorithm runs in this processor to encrypt data for secure transmission. ‘5. Dectyption engine: A suitable algorithm runs inthis processor to decrypt the encrypted data at receiver's end, 6. A discrete cosine transformation (DCT) and inverse transformation (DCIT) processor is required in speech and video processing. 7._ Protocol stack processor: A protocol stack, which has a number of header words, is prepared before an application data issent 10 anetwork, At the receiver's end, the protocol sack is received and application data is accepted accordingly. A TCP/IP protocol stack processor processes TCP/IP network data. 8 Network processor: A network processor's functions are to establish a connection, finish, send and receive acknowledgements, send and receive retransmission requests and check and correct received data frame errors. The network processor's functions include all protocol stack-processing functions. 9. Accelerator (for example, Java codes accelerator). The accelerator is a coprocessor that accelerates, ‘computations by taking advance actions that are just-in-time compilations of the next object in Java programs. 10. CODEC (Coder and Decoder): A CODEC is a processor circuit that encodes input and decodes the «encoded information or bits or signals into a complete set of bits or original signal. Voice, speech,Enbected Syste image, video signals and bits are encoded for storing or transmission and decoded from the stored or received bits or signal for display or playing. The CODEC functions as a compression and decompression unit for voice, speech, image or video signals, LL. JPEG CODEC: This is a processor for jpg compression and decompression. The Joint Photographic Experts Group (JPEG) is an International Telecommunieation Union for Telecom (ITU-T) and International Standards Organisation (ISO) committee 12. MPEG CODEC: The Motion Pictures Experts Group (MPEG) recommends CODEC standards for video. MPEG3 CODEC is a processor for mp3 compression and decompression, MPEG 2 or 3 or 4 compression of audio/video data streams is done before storing or transmitting, and decompression is done before retrioving or playing files. For MPEG compression and decompression algorithms, if GPP-embedded software is run, then separate DSPs are required to achieve real-time processing. 13. Controller (eg. For peripheral, direct memory access or bus). Single purpose processors are used for specific applications or computations ors controllers for peripherals, direet memory accesses and buses, 3 EMBEDDED HARDWARE UNITS AND DEVICES IN A SYSTEM. 1.3.1 Power Source Most systems have a power supply of their own, The Network Interface Card (NIC) and Graphie Aceelerator are examples of embedded systems that do not have their own power supply and connect to PC power- supply lines. The supply has a specific operation range or a range of voltages, Various units in an embedded system operate in one of te following four power ranges: 5.0 V + 0.25 V,3.3V 0.3 V,20V +0.2V sand 15 V+0.2 V. There is generally an inverse relationship between propagation delay inthe gates and operational voltage. Therefore, the § V system processor and units are used in most high performance systems, ‘Certain systems do not have a power source of their own: they connect fo external power supply or are powered by the use of charge pumps (made up of acireuit of diode and capacitor that accumulate charge from the bus signals through which they connect or network to the host or from wireless radiation), Low voltage operations 1. Inportable or hand-held devices such as acellular phone [when compared to 5 V, a CMOS 2 V circuit power dissipation reduces by one-sixth, ~ (2 VS V}. Tis als inereases the time intervals needed for recharging a battery by a factor of six.) 2. Inva system with smaller overall geometry, low voltage system processors and IO circuits generate lesser heat and thus can he packed into a smaller space. A power supply source or a charge pump is essential in every system, 1.3.2 Clock Oscillator Circuit and Clocking Units ‘The clock controls the time for executing an instruction. After the power supply, the clock isthe basic unit of system. A processor needs a clock oscillator cireuit. The clock controls the various clocking requirements ofpe @) the CPU, of the system timers and the CPL machine cycles. The machine cycles are for fetching codes and data from memory and then decoding and executing them at the processor and for transferring the results to memory. For processing units, 1 highly stable oscillator is required and the processor clock-out signal provides the ‘lock for synchronizing all system units with the processor. 1.3.3 System Timers and Real-time Clocks A timer circuit is suitably configured as the system-clock, which ticks and generates system interrupts periodically; for example, 60 times in Is, The interrupt service routines then perform the required operation, A timer citeutis suitably configured the real-time clock (RTC) that generates system interrupts periodically for the schedulers, real-time programs and for periodic saving of time and date in the system. ‘The RTC orsystem timer is also used to obtain software-controlled delays and time-outs. An RTC funetions as driver for software timers (SWS). [Sections 3.6 and 38] Microcontrollers also provide internal timer circuits for counting and timing devices. To schedule the various tasks and for real-time programming, an RTC or system clock is needed. The ‘lock also drives the timers for various timing and counting needs in a system, 1.3.4 Reset Circuit, Power-up Reset and Watchdog-Timer Reset ‘The program counter (PC) holds the address from where the instruction is to be fetched for execution, In 80x86 processors, the instruction pointer (IP) holds that address. A code segment register (CS) holds the base address of the code memory segment. The CS address equals the code starting address when the IP = 0 atthe start of a code segment. The IP increments when the program executes the codes, Reset means that the processor begins the processing af instructions from a starting address. That address is one that is set by default in the processor PC (or IP and CS in x86 processors) on a power-up. From that address in memory, program-instructions are fetched following the reset of the processor. A program that is reset and runs on a power-up can be one of the following: (i) A system program that executes from the beginning. (i) A system boot-up program. (ii) A system initialization program In certain processors, for example, 68HCI1 and HC12, there are two start-up addresses. One is based on. the power-up reset vector and the other on the reset vector after the reset instruction or after a time-out (for example, from a watchdog timer). The processor fetches the bytes for the PC from the first power-up reset ‘vector on power-up. The processor fetches the bytes for the PC from the second reset vector on the watchdog timer timing out oF on executing the reset instruction, The reset circuit activates for a fixed period (a few clock cycles) and then deactivates. The processor circuit Keeps the reset pin aetive and then deactivates to let the program proceed from a default beginning address. The reset pin or the internal reset signal, if connected to the other units (for example, the 10 interface or the serial interface) in the system, is activated again by the processor; it becomes an outgoing pin to enforce reset state in other sister units ofthe system. On deactivation ofthe reset that succeeds the processor activation, 1 program executes from a start-up address Reset can he activated by an external reset circuit that activates on power-up, on switching-on reset of the system or on detection of a low voltage (e.g. <4.5 V when what is required is $ V on the system(®) Embed Sytem supply rails). This cireuit output connects to a pin called the reset pin ofthe processor. This circuit may be a simple RC circuit, an external IC citeut or a custom-built IC, Examples of ICs are MAX 6314 and Motorola, MC 34064. ‘Alternatively, it ean also be activated by any one of the following: (i) software instruction; ii) time-out by ‘a programmed timer known as a watchdog timer (or on an internal signal called COP in 68HC1I and 68HC 12 families); (ii) a clock monitor detecting a slowdown below certain frequencies. ‘The watchdog timer is a timing device that resets the system after a predefined timeout, It is activated ‘within the first few clock eyeles after power-up, It has a number of applications. In many embedded systems reset by a watchdog timer is very essential because it helps in rescuing the system if a fault develops and the program gets stuck. On restart, the system can function normally. Most microcontrollers have on-chip watchdog timers. The watchdog timer device is described in detail in Section 3.7 Consider a system controlling temperature. Assume that when the program stars executing, the sensor inputs work all right, However, before the desired temperature is achieved, the sensor cireuit develops some fault. The controller will continue delivering the eurrent nonstop if the system is not reset. Consider another example of a system for controlling a robot, Assume thatthe interfacing motor control eireuit inthe robot arm develops a fault during the run. In such eases, the robot arm may continue to move unless there is a watchdog timer control. Otherwise, the robot will break its own arm! When a program executes the program counter inerements or changes. An important circuit that associates ‘a system is its reset circuit that can change the program counter to a power-up default value. A program that is reset and runs on a power-up can be one of the following: (i) A system program that executes from the beginning. (ii) A system boot-up program, (ii) A system initialization program, ‘The watchdog timer reset is a required feature in control applications 1.3.5 Memory In system, there are various types of memory. Figure 1.4 shows a chat for various forms of memory that are present in systems, These ae as Follows: 1. Intemal RAM of 256 or 512 bytes in a mierocontoller for registers, temporary data and stack Internal ROM/PROM/E"PROM for about 4 KB to 64 KB of program (in the case of microcontroller) Extemal RAM for the temporary data and stack (in most systems) oF intemal eaches (inthe case of certain microprocessors. Various Forms of System Memory oo oo Intern RAMat Internal Extemal Flashy ROM! Memory Raw System. Caches RAM EEPROM PROM Adresses Micro ‘one = ccipts) * Contoier Chip Microprocessor ——* the System or Hold Copies Extemal Ports External of Systom andlor RAM Memory ‘tunel pages) Fig. 1.4 The various forms of memories in the systemIntroduction to Embedded Systems. 4, Intemal flash (in many system the results of processing can be saved in nonvolatile memory: for example, system status periodically and images, songs, or speeches after suitable format compression). ‘5. Memory stick (or card): video, images, songs, or speeches and large storage in digital camera and mobile systems. Sony memory stick Micro (M2) is of size 15x12.53c1.2 mm and has a flash memory of 2 GB. It has a data transfer rate of 160 Mbps (mega bit per second) and PRO-HG 480 Mips and 120 Mbps write [since Dec. 2006.) 6. External ROM or PROM for embedding software (in almost all systems other than microcontroller- based systems), 7. RAM memory bulfers at ports 8. Caches (in pipelined and superscalar microprocessors). ‘Table 1.1 details the funetions assigned in embedded systems to the memories. ROM or PROM or EPROM. embeds the software specific to the system, Table 1.1 Functions assigned to the memories in a system ‘Memory Needed Functions ROM or EPROM Storing application programs from where the processor fetches the instuction codes ‘or Hash Storing eodes for system booting, initializing, inital input data and strings. Codes for RTOS. Pointers (addresses) of various intemipt service routines (ISRS). RAM (internal and extemal) Storing the variables during program run and storing the stack. Storing input or output and RAM for buffer buffers, for example, for speech or image, Memory stick ‘A flash memory stick is inserted in mobile computing system or digital-camera. It sores high definition video, images, songs, or speeches after a suitable format compression and stores large persistent data. EEPROM oF Flash Storing nonvolatile results of processing. Cache Storing copies of instructions and data in advance fom exter primary memory and storing the results temporarily during processing. A system embeds (locates) the following either in the internal flash or ROM, PROM or in an external flash ‘or ROM or PROM of the microcontroller: boot-up program, initialization data, strings or pictogram for screen-display or initial state ofthe system, programs for various tasks, ISRs and operating system kernel. ‘The system has RAMS for saving temporary data, stack and buffers that are needed during a program run ‘The system uses flash for storing nonvolatile results, 1.3.6 Input, Output and IO Ports, IO Buses and IO Interfaces ‘The system gets inputs from physical devices through the input ports. Examples are as follows: 1. A system gets inputs from the touch screen, Keys in a keypad or keyboard, sensors and transducer circuits 2. A controller circuit in a system gets inputs from the sensor and transducer circuits. 3. Arreceiverof signals ora network card gets the input from a communication system. [A communication system could be a fax or modem, or a broadcasting service.) 4, Ports receives inputs from a network or peripheral(4) Embed Sytem ‘Consider the system in an Automatic Chocolate Vending Machine, I gets inputs from a port that collects the coins that aehild inserts. ‘Consier the system in a mobile phone. A user inputs the mobile number through the huttons, direetly or indirectly (through recall of the number from its memory). Keypad keys connect tothe system through an input port [A processor identifies each input port by its memory buffer addresses, called port addresses. Just as a ‘memory location holding a byte or word is identitied by an address, each input port is also identified by the andess, The system gets the inputs by the read operations at the port addresses, “The system has outpat ports through which it sends ousput bytes to the real world, Examples ure as follows: 1. Output may be sent to an Tight emiting diode (LED), liquid erystl display (LCD) or touch sereen display panel. For example, a calculator or mobile phone system sends the output-numbers or an SMS. message tothe LCD display. A system may send the ouput to printer ‘Output may be sent ta communication system or network |. control system sends the outputs to alarms, actuars, furnaces or boilers. . A robot is sent output for its various motors. Each output por is identified by its memory-baffer addresses (called port addresses). The system sends the ouput by a write operation to the port address ‘There ae also general-purpose port for both the input and output (10) operations. For example, a mobile phone system sends output as wells gets input through a wireless communication channel, A mobile computing system touch sereen system sends output as well as gets input when auser touches the menu displayed or key on the sereen, Each 1O port is also identitied by an address to which the read and waite operations both take place Portsean have serial or parle communication with the system adress and data buses. In serial communication ‘one-bit data line is used and bits are sent serially in sueeessive time slots. Universal Asynchronous Receiver and Transmitter (UART) is @ popular communication protocol for serial communication. In parallel communication, several data lines are used and bits are sent in parallel ‘A system port may have to send output to multiple channels. A demultiplexer or multiplexer eieuit is then sed, ‘A demultiplexer i a digital circutthat sends digital outputs at any instance to ane of the provided channel. ‘The channel to which the output is sent is the one that is addressed by the channel address bits at the demultiplexer input. A demultiplexer takes the input and transfers it wo a select channel output among the ‘multiple output channels. ‘A multiplexer is digital circuit that roceives digital inputs at any instance from multiple channels, and sonds data output only from a specific channel at an instance. The channel address bits are at multiplexer ‘input, A multiplexer takes the input from one among the multiple input channels and transfers a selected channel input tothe output. ‘A system unit (for example, memory unit or IO port or device) may have tobe selected from among the 1ultiple units in the sytem and activated, A decoder cieuit when used as an address decoder decodes the input aulesses and atiates the selected output channel from among the many outputs. For example there are 8 units of which one has 1 be selected, An addres-seeet input of 3 bits is input wo the decoder. Based on the input axldress, the output select line among the 8 activates. I the input address bit s 000, then the O* output is active and the O° unit activates, If the input address bit is 111, then the 7 output is active and the 7 unit aetivates, Bus A system might have w be connected 10 a number of other devices and systems. A bus consists of a common setof lines to connect multiple devices, hardware units and systems for communication between anyIntroduction to Embedded Systems. two ofthese at any given instance. A bus communication protocol specifies how signals communicate on the bus. A bus may’be a serial or parallel bus that transfers one oF multiple data bits at an instance, respectively. ‘The protocol also specifies the following: (i) ways of arbitration when several devices need to communicate through the hus; Gi) ways of polling bus requirement from each device at an instance: (il) ways of daisy chaining the devices so that bus is granted to a device according to the device-priority inthe chain Fornetworking the distributed unitsor systems, there are different types of serial and parallel bus protocol: FC, CAN, USB, ISA, EISA and PCI For wireless networking of systems there are 80211, IRDA, Bluetooth and ZigBee protocols. ‘Chapter 3 will eserbe the ports, devices, buses and protocols in detail ‘A system connects t0 external physical devices and systems through parallel or serial 1/0 ports Demultplexers and multiplexers facilitate communication of signals from multiple channels through 3 ‘common path, A system ofien networks to the other devices and systems through an VO bus: for example, PC, CAN, USB, ISA, EISA and PCI bus. 1.3.7 DAC Using a PWM and an ADC DAC isa circuit that converts digital 8 or 10 oF 12 bits to the analog output. The analog output is with respect to the reference voltage. When all input bits are equal to 1, hen the analog output is the difference between the positive and negative reference pin voltages; when all input bits equal 0, then the analog output equals ve reference pin voltage (usually 0 V) Suppose a system needs to give the analog output of a control circuit for antomation, The analog output ‘may be to.a power system for d.e, motor or furnace. A pulse width modulator (PWM) with an integrator circuit is used for the DAC. A PWM unit in the microcontroller operates as follows: Pulse width is made proportional to the analog-output needed. PWM. inputs are from 00000000 to 11111111 for an 8-bit DAC operation. The PWM unit outputs to an external integrator, which provides the desired analog output. From this information, the formula to obtain the analog ‘output from the its in a given PWM register with bits ranging from 00000000 to 11ILILIL is as follows: ‘Analog output V = K-pw, where K is constant and pw is the pulse width. ‘Suppose a circuit (external to the mierocontroller} gives an output of 1,024 V when the pulse width is 50% of the total pulse time period, and 2.047 V when the width is 100%. When the width is made 25%, by reducing by half the value in the PWM output control-register, the integrator output will become 0.512 V. The constant K depends on integrator amplifier gain, "Assume that the integrator operates with a dual (plus-minus) supply. The PWM unitin the microcontroller ‘operates by another method, which is as follows, Assume that when an integrator circuit gives an output of 1.023 ¥, the pulse width is 100% of the total pulse time period and of -1.024 V when the width is 0%, When the width is made 25% by reducing by half the value in an output control register, the integrator output will be (0512 V; at 50% the output will be 0.0 V. From this information, the formula to obtain the analog output from the bits ina given PWM register canging from 00000000 to 11111111 in both situations is as follows: Analog output V = 0.01. K’. (pw ~ 50), where K" is constant and pw is pulse width time in percentage with respect to pulse time period. K’ depends on integrator amplifier gain Analog to Digital Converter ADC is. circuit that converts the analog input to digital 4, 8, 10 or 12 bis. The analog input is applied between the positive and negative pins and is converted with respeet to the reference voltage. When input is equal to difference of reference positive and negative voltages, then all ‘output bits equal 1; when equals negative reference voltage (usually 0 V), then all output bts equal 0.Embed Sytem ‘The ADC in the system mierocontroller ean be used in many applications such as data acquisition systems (DAS), digital cameras, analog eonvol systems and voive digitizing systems. Suppose a system gets the analog inputs from sensors of temperature, pressure, heaft-beats and other sources in a DAS. Suppose a system gets the analog inputs from a digital camera. Ithas CCD (Charge Couple Device) which has tiny pixels that charge up on exposure to light. The charging ofeach pixel depends upon the light intensity a that point in the image. The analog inputs to the system generate from each pixel. Each pixel's analog input has to be converted int bis o enable processing in the next stage. Suppose a system nceds to read an analog input from a sensor or transducer circuit. If converted to bits by the ADC unit inthe system, then these bits after processing, can also give an output. This provides a contol for automation by a combined use of ADC and DAC features. “The converted bits can be given to the port meant for memory address, a serial port or a parallel por. [A processor may process the converted bits and generate a Pulse Code Modulated (PCM) output. PCM signals are used ta digitize voice into a digital format. Important points about the ADC are as follows. 1. Bither a single or dual analog reference voltage-source is required inthe ADC. It sets either the analog inputs upper limit or the lower and upper imits both, Fo a single reference source, the Tower limit is sett00 V (ground potential), When the analog input equals the lower iit, the ADC generates al bits 80s, and when it equals the upper limitit generates al its as 1s, (Asan example, suppose in an ADC the upper limit or reference voltage is set to 2.255 V. Let the lower limit reference voltage be 0.255 V. The difference in the limits is 2 V. Therefore, the resolution wil be 2/286 V. Ifthe 8-bit ADC analog- input is 0.255 ¥, the eonverted 8 bits will be 00000000. When the inpu i 0.255 V + 1.000 V = 1.255 V, the bits will be 10000000. When the analog input is 0.255 V + 0.50 V. the converted bits will be (01000000. (From this information, finding a formula to obtain converted bits for a given analog, input = v volt is as follows: Binary number n bits after conversion in an n-hit ADC corresponds to decimal number N. Then N =v. Vnc,~ V gg 28. Here, Vg the neference voltage that gives all the bits that ae equal to 1 and V,,¢ isthe reference voltage that gives all the bits that are equal to 0.) 2. An ADC may be of 8,10, 12, or 16 bts depending upon the resolution needed for conversion. 3. The start of the conversion (STC) signal of input initiates the conversion 108 bits Ina system, an instruction of timer signals the STC. 4. There is an end of conversion (EOC) signal. A flag ina register is set o indicate the end of conversion and the ADC generates an interrupt; the ISR reads the ADC bits and saves them in the memory buer. 5. There isa conversion time limit in which the conversion is definite 6. A Sample and Hold (S/1) units used to sample the input for a fixed time and hold til conversion i [An ADC unit can be repeatedly used after the intervals equal to the conversion time. Therefore, one ean digitizes the DAS sensor signals, CCD signals, voice, musi or video signals, or heartbeat sensor signals in different systems. An ADC unit in an embedded system microcontroller may have multichannels. I can then take the inputs in succession from the various pins interconnected to different analog sources, ital display. The bits may be transferred 10 a For automatic control and signal processing applications, a system provides necessary interfacing cireuit and software for the Digital to Analog Conversion (DAC) unit and Analog to Digital Conversion (ADC) A DAC operation is done with the help of a combination of a PWM unit in the microcontroller and an external integrator chip. ADC operations are required for data acquisition, image processing, voice processing, video processing, instrumentation and automatic control systems,Introduction to Embedded Systems. 1.3.8 LCD, LED and Touchscreen Displays A system requires an interfacing circuit and software to display the status or message fora line, for multiline displays, orfor flashing displays. An LCD sereen may show up a multiline display of characters or also show a small graph or ieon (called a pictogram), A recent innovation in the mobile phone system tums the screen blue to indicate an incoming call, Third generation system phones have both image and graphic displays. An LCD needs litle power. A supply or battery (a solar pane! in the calculator) powers it. The LCD isa diode that absorbs or emits light and 3 10 4 V and 50 or 60 Hz voltage-pulses with currents less than ~50 WA are required. ‘The pulses are applied with the same polarity on the crystal front and back plane for no light, and with ‘opposite polarity for light. Here, polarity means logic ‘1° or ‘0°. A display-controller is often used in case of matrix displays, To indicate the ON status ofthe system, there may bean LED that glows. A flashing LED may indicate that a specific task is under completion or is running or in wait status, The LED isa diode that emits yellow, green, red of infrared light in a remote controller on application of a forward voltage of between 1.6-2 V. It needs current up to 12 mA above $ mA (ess in flashing display mode). Itis much brighter than the LCD, making it suitable for flashing displays and for displays limited to a few digits ‘Atouchsereen is an input as well as an output device, which can be used to enter a command, a chosen menu 1 « give a reply. The information is input by physically touching ata sereen position using a finger or a stylus A stylusis thin peneil-shaped object. Itis held between the fingers and used just as a pen. The screen displays the choices or commands, menus, dialog boxes and icons, The display-sereen display is similar to a computer video display unit sereen, Newer touch screen senses the fingers even from proximity, for example, in Apple iPhone. Sections 3.3.4 and 3.3.5 describe the LCD and touchsereen devices and their connections to the system, ‘The system may need the necessary interfucing cireuit and software for the output to the LCD display controller and the LED interfacing ports or for the UOs with the touchscreen. 1.3.9 Keypad/Keyboard ‘The keypad or keyboard is an importam device for getting user inputs. The system provides the necessary inerfacing and key-ebouncing circuit as well as the sofiware for the system to receive input from a set of keys, from a keyboard, keypad or virtual keypad. A touchscreen provides for a virtual keypad in a mobile computing system, A virtual keypad is a keypad displayed on the touch screen where the user can enter the keys using a stylus or finger. ‘A keypad has upto a maximum of 32 keys. A keyboard may have 104 keys or more. The keypad or keyboard may interface serially or parallelly to the processor directly through ports or through a controller Mobile phones may have a T9 keypad. A T9 keypad has 16 keys and four up-down right-left menu keys. Using 0 10 9 keys text messages, such as SMS messages, are generated. For inputs, a keypad or board may interface to a system. The system provides necessary interfacing cireuit ‘and software to receive inputs directly from the key’ or through a controller. 1.3.10 Pulse Dialer, Modem and Transceiver For user connectivity through the telephone line, wireless or a network, a system provides the necessary interfacing and citeuits. I also provides the software for pulse dialing through the telephone line, for modemEmbed Sytem interconnection for fax, for Internet packets routing and for transmitting and connecting to a wireless cellular system or personal area wireless network. A transceiver is a circuit that can transmit as well as receive byte streams, In communication system, a pulse dialer, modem or transceiver is used. A system provides the necessary interfacing circuit and software for dialing and for the modem and transceiver, directly or through controller. 1.3.11 Interrupt Handler A timing device sends a time-out interrupt when a preset time elapses or sends a compare interrupt when the present-time equals the preset time. Assume that data have to be transferred from a keyboard to a printer, A port peripheral generates an interrupt on receiving the input data or when the transmitting buffer becomes ‘empty. Each action generates an interrupt. A system may possess a number of devices and the system processor has to control and handle the requirements of each device by running an appropriate ISR (interrupt service routine) for each, An interrupis-handling mechanism must exist in each system to handle interrupts from various processes and for handling multiple imerrupts simultaneously pending for service, Chapter 4 describes in detail the interrupts, ISRs, and their handling mechanisms in a system, Important points regarding the interrupts and their handling by the program are as follows. 1, There can be a number of interrupt sources and groups of interrupt sources in a processor. [Section 4.3] An interrupt may be a hardware signal that indicates the oceurrence of an event, [For example, « real-time clock continuously updates a value at a specified memory address; the lransition of that value is an event that causes an interrupt.] An interrupt may also occur through timers, through an interrupting instruction of the processor program or through an error ‘during processing. The error may arise due to an illegal op-code fetch, a division by zero result or an overflow or underflow during an ALU operation, An interrupt can also arise through a software timer. A software interrupt may atise in an exceptional condition that may have developed while running a program, ‘The system may pricritize sources and service them accordingly. [Section 4.5.] 3. Certain sources are not maskable and cannot be disabled. Some are assigned the highest priority during processing. 4. The processor's current program has to divert to a service routine to complete that task on the occurrence ‘of the interrupt, For example, if key is pressed, then an ISR reads the key and stores the key value in the processor memory address. Ifa sequence of keys is pressed, for instance in a mobile phone, then aan ISR reads the keys and also calls a task to dial the mobile number, . There is a programmable unit on-chip for the interrupt handling mechanism in a microcontroller. 6. The operating system is expeeted to contol the handling of interrupts and running of routines for the interrupts in a particular application, The system always gives priority to the ISRs over the tasks oF an application, ‘A system provides an interrupt handling mechanism for executing the ISRs in case of the interrupts from physical devices, systems, software instructions and software exceptions.pe “1.4 EMBEDDED SOFTWARE IN A SYSTEM “The software is like the brain of the embedded system, 1.4.1 Final Machine Implementable Software for a System ‘An embedded system processor executes software that is specific to « given application of that system, The instruction codes and data inthe final phase are placed in the ROM or flash memory for all the tasks that are executed when the system runs, The software is also called ROM image. Why? Tust as an image is a unique sequence and arrangement of pixels, embedded software is also a unique placement and arrangement of bytes for instructions and data, ach code or datum is available only in the bits and bytes format, The system requires bytes at each ROM adress, according to the tasks heing executed. A machine implementable software fite is therefore like a table having in each rows she address and bytes. The bytes are saved at each address of the system ‘memory. The table has to be readied as a ROM image for the targeted hardware, Figure 1.5 shows the ROM image in a system memory, The image consists of the boot up program, stacks address pointers, program counter address pointers, application programs, ISRs, RTOS, input data and vector addresses. 2 Bytes for PC-ADDR ‘Address from 2 Bytes for Sires ‘Where Sysiom see Stane bi -SP-ADDR Execution on a Power Up ie (Not Neesed in ADDR 80x86, 8057, 80196, / ) Intomupt Service ADDR-2 = Routine Vector ARS: mee ‘Aadrossos of es Inputs for each 2 Byles each Interrupt eke ADDR Sorvleo Routine Program Codes Machine Spectic ADDR-T Machine Codes for Real Time Operating ‘System (RTOS) ADDR-10 Fig, 1.5 System ROM memory embedding the software, RTOS, data and vector addressesEmbed Sytem Final stage software is also called the ROM image. The final machine implementable software for a product embeds in the once programmable flash or ROM (or PROM) as an image ina frame. Bytes at each address must be defined to create the ROM image. By changing this image, the same hardware platform will work differently and can be used for entirely different applications or for new upgrades of the same system, 1.4.2 Coding of Software in Machine Codes During coding in this format, the programmer defines the addresses and the corresponding bytes ot bits at each address. In configuring some specific physical device or subsystem, machine code-based coding is used. For example, in a transceiver, placing certain machine code and bits can configure it to transmit at specific _megahytes per second or gigabytes per second, using specific bus and networking protocols. Another example is using certain codes for configuring a control register with the processor. During a specific cade-section processing, the register can be configured to enable or disable use of its internal cache, However, coding in machine implementable codes is done only in specific situations because itis time consuming and the programmer must first have to understand the processor instructions set and then memorize the instructions and their machine codes. 1.4.3 Software in Processor Specific Assembly Language A program ora small specific part can be coded in assembly language using an assembler after understanding the processor and its instruction set. Assembler is software used for developing codes in assembly. Assembly language coding is extremely useful for configuring physical devices like ports, a line-display interface, ADC and DAC and reading into or transmitting from a buffer. These codes are also called low-level codes for the device driver functions, [Sections 1.4.7 and 4.2.4.] They ae useful to run the processor or device-specific features and provide an optimal coding solution Lack of knowledge of writing device driver codes or codes that utilize the processor-specific Features invoking codes in an embedded system design team can costa Tot. A venclor may charge for the APIs and also charge intellectual property fees for each system shipped out of the company. ‘To make all the codes in assembly language may, however, be very time consuming. Full coding in assembly may be done only Fora few simple, small-scale systems, such as toys, automatic chocolate vending machines, robots or data acquisition systems. Figure 1.6 shows the process of converting an assembly language program into machine implementable software file and then finally obtaining a ROM image file. 1, An assembler translates the assembly software into the machine codes using a step called assembling. 2. In the next step, called finking, a Tinker links these codes with the other codes required, Linking is necessary because of the number of codes 1 be linked for the final hinary file, For example, there are the standard codes to program a delay task for which there is reference in the assembly language program. The codes for the delay must link with the assembled codes. The delay code is sequential froma certain beginning address, The assembly software code is also sequential from acertain beginning address. Both the codes have 1o be linked at the distinct addresses as well as atthe available addresses inthe system. The linked file in binary for run on a computer is commonly known as an executable file cor simply an “.exe’ file. After linking, there has to be reallocation ofthe sequences of placing the codes hefore actually placing the codes in memory.pe @) — aa a], | eae ‘Specific [Assembler forthe 8 ready for. ee oO" mae ‘Language | —7 a 2 a coe es | | | athe Peca| 2 || fs ea la : We ypu earn Device £5, | une | ayes re Le Fe lector ao HSE oie lnm = —— eee Fig. 1.6 The process of converting an assembly language program into the machine codes and finally obtaining the ROM image 3. In the next step, the loader program performs the task of reallocating the codes after finding the physical memory addresses available at a given instant, The loader is a part of the operating system. and places codes into the memory after reading the ‘exe’ file, This step is necessary because the available memory addresses may not start from 0x0000, and binary codes have to be loaded at different addresses during the run, The loader finds the appropriate start address. In a computer, after the loader loads into a section of RAM, the program is ready to run. 4, The final step of the system design process is locating these codes as a ROM image. The codes are permanently placed at the addresses actually available in the ROM. In embedded systems, there is no separate program to keep tack ofthe available addresses at different imes during the tun, as ina compute. In embedded systems, therefore, the next step instead of loader after linking is the use of a locator, which locates the 10 tasks and hardware device driver codes a fixed addresses. Port and device addresses are fixed fora given system as per the interfacing circuit between the system huses and ports or devices. ‘The focator program reallocates the linked file and creates file for a permanent location ofthe codes in 4 standard format, Te file format may be in the Intel Hex fle format or Motorola S-record format. The designer has to define the available addresses to locate and create files to permanently locate the codes. ‘5. Lastly, either (i) a laboratory system, called device programmer, takes as input the ROM image file and finally burns the image imo the PROM or flash or (ii) at a foundry, a mask is created for the ROM. Of the embedded system from the ROM image file. [The process of placing the codes in PROM or Flash is also called burning, The mask created from the image gives the ROM in IC chip form. ‘To configure some specific physical device or subsystem such as the transceiver, machine codes can be used straightaway, For physical device driver codes or cades that uilize processor-specificfeatures-invoking ‘codes, ‘processor-specific’ assembly language is used, A file is then created in three steps using an Assembler, Linker and Locator, The file has the ROM image in a standard format, A device programmer finally burns the image in the PROM or EPROM. A mask ereated from the image gives the ROM in IC chip form,Embadded Systems 1.4.4 Software in High Level Language Since the coding in assembly language is very time consuming in most cases, software is developed in a high- level language, *C” or ‘C++” or visual C++ or ‘Java’ in most cases. ‘C” is usually the preferred language. The programmer needs to understand only the hardware organization when coding in high level language. As an ‘example, consider the following problem, Example 1.1 ‘Add 127,29 and 40 and prin the square root. ‘An exemplary € language program for all the processors is as follows. (i) # include i) # include (iit) void main (void) (iv) ine iD, i2, 13, a; float resule, (v) id = 127; i2= 20; (3 = 40; a= 11 +12 + 63; result = sqrt (a); (i) print (result) “The coding for square root will need many lines of code and can be done only by an expert assembly Preprocessor Commands language programmer. To write the program in a high Main Function level language is very simple compared to writing iin assembly language. *C” programs have a feature that Interrupt Service Routines adds the assembly instruetions when using certain a processor-specifie features and coding for a specific section, for example, a port device driver. Figure 1.7 Kemel and Scheduler Shows the diferent programming layer in atypical Stender Libry embedded °C’ software. These layers are as follows. Functions Including Gi) Processor Commands. (ii) Main Function Netmore Preset Gi) Inerrapt Service Routine. (i) Multiple tasks, sa, sony Sac ans 110 (e) Kernel and Scheduler (¥) Standard library ecavng Sn functions, protocol handling and stack functions. Figure 1,8 shows the process of converting a € program into the ROM image file, A compiler generates the object codes. It assembles the codes according to the processor instruction set and other specifications. The C compiler for embedded systems must, as a final step of compilation, use a code-optimizer that optimizes the codes before linking. After compilation, the linker links the object codes with other needed codes. For example, the linker includes the codes for the functions priuf and sgrt codes. Codes for device and driver (device control codes) management also link at this stage: for example, printer deviee management and driver codes, After linking, the other steps for creating a file for ROM image are the same as shown earlier in Figure 1.6. Fig. 1.7. The different program layers in the embedded software in C C, C+, Java, Visual C++ are the languages used for software development. AC program has various layers: processor commands, main function, task and library functions, interrupt service routines and kernel (scheduler). The compiler generates an object file. Using a linker and locator, the file for the ROM image is created for the targeted hardware,Introduction to Embedded Systems. © | Machine | _3 Program Codes in Funetions |" Compzer | Object File From Library e Byles for Needed Linked Machine [Lin Programs Codes: ‘Steps 9 and 4 shown in Figure 1.6 Embedded System ROM Momory Fig. 1.8 The process of converting a C program into the file for ROM image 1.4.5 Program Models for Software Designing ‘The program design task is simplified if @ program is modeled, ‘The different models that are employed during the design processes ofthe embedded softwareare as follows: 1. Sequential Program Mode! 2. Object Oriented Program Model 3. Control and Dataflow graph or Synchronous Data Flow (SDF) Graph or Multi Thread Graph (MTG) Model 4. Finite State Machine for data path 5. Multithreaded Model for concurrent processing of processes or threads or tasks UML (Universal Modeling language) is a modeling language for object oriented programming ‘These models are explained Chapter 6. 1.4.6 Software for Concurrent Processing and Scheduling of Multiple Tasks and ISRs Using an RTOS An embedded system program is most often designed using multiple processes or multitasks or a multithreads. [Refer to Sections 7.1 107.3 for definitions and understanding ofthe processes, threads and tasks.] ‘The multiple tasks are processed most often by the OS not sequentially but concurrently. Concurrent processing tasks ean be interrupted for running the ISRs, and a higher priority task preempts the running of lower priority tasks. ‘An OS provides for process, memory, devices, 10s and file system management. A file system specifies the ways in which a file is ereated, called, named, used, copied, saved or deleted, opened and closed. File system isthe software for using the files on a disk, lash memory, memory eard or memory stick. ‘OS software have scheduling functions for all the processes (tasks, ISRs and device drivers) in the system. Since the running of the tasks and ISRs may have realtime constraints and deadlines for finishing the tasks, an RTOS is required in an embedded system, The RTOS provides the OS functions for coding the system, provides interprocess communication functions and controls the passing of messages and signals to atask. RTOS functions are highly complex. There are a number of popular and readily available RTOSS. Chapters 8 to 12 describes the RTOS functions and examples of applications in the embedded systems.Embedded Systams RTOS is used in most embedded systems and the system does concurrent processing of multiple tasks when the tasks have real time constraints and deadlines 1.4.7 Software for Device Drivers and Device Management in an Operating System ‘An embedded system is designed to perform multiple functions and has to contro! multiple physical and virtual devices. In an embedded system, there may be numberof physical devices. Exemplary physical devices are timers, Keyboards, display, flash memory, parallel ports and network cards. A program is also be developed using the concept of virtal devices. Examples of viral devices are as follows. 1. A file (of records opened, read, written and closed, and saved as a stream of bytes or words) 2. A pipe (for sending and receiving a stream of bytes from a source to destination) 3. A socket (for sending and receiving a stream of bytes between the client and server software and between source and destination computing systems) 4. A RAM disk (for using the RAM in a way similar to files on the disk) Afile isa da device) which sends the records (characters or words) to a data sink (for ‘example, a program function) and which stores the data from the data source (for example, a program function). A file in a computer may also be stored in the hard disk and in flash memory in embedded system, ‘The term virtual device follows from the analogy that just as a keyboard gives an input tothe processor for ‘a read, file also gives an input to the processor. The processor gives an output 19 a printer for a write, similarly, the processor writes an output 10 the file. A device for the purpose of control, handling, reading and writing actions ean be taken as consisting of three components. (i) A control register or word that stores the bits that, on setting or resetting by a device river, control device actions. (ii) A status register or word that provides the flags (bits) to show the device status to the device driver. (iii) A device mechanism that controls the device actions. There may be input and ‘output data butfers in a device, which may be written or read by a device driver. Device driver actions are to get input into or send output from the control registers, input data buffers, output data butfers and status registers of the device, ‘A device driver is software for opening, connecting or binding, reading, writing and closing or controlling actions of the device. It is software written in a high level language, It controls functions for device open (configure), connect, bind, listen, read or write or close. The device driver executes after the programming of the control register (or word) ofa peripheral or virtual device. The programming is called device initialisation (or registration or attachment, The driver reads the status register, gets the inputs and writes the outputs. It ‘executes on an interrupt to or from the device. ‘A driver controls three functions. (i) Initializing, which is activated by placing appropriate bits at the ‘control register or word. (ji) Calling an ISR on interrupt or on setting a status flag in the status register and running (driving) the ISR (Loterrupt Handler Routine). (it) Resetting the status flag after an interrupt service. A driver may be designed for asynchronous operations (multiple use by tasks one after another) or synchronous ‘operations (concurrent use by the tasks). Using the functions of the OS, a device driver coding can be made such that the underlying hardware is hidden as much as possible. An API then defines the hardware separately. This makes the driver usable when the device hardware changes in a system.pe ®) A devive driver accesses a parallel or serial port, keyboard, mice, disk, network, display, file, pipe and socket at specific addresses. An OS also provides device driver codes for system-port addresses and for hardware access mechanisms. A device manager software provide codes for detecting the presence of devices, for initializing these and for testing the devices that are present. The manager includes software for allocating and registering port (in fae, itmay be a register or memory) addresses forthe various devices at dstinetly different addresses, including codes for detecting any collision between these, if any. It ensures that any device accesses to one task only at any given instant. It takes into account that virtual devices may also have addresses that are allocated by the manager. ‘An OS also provides and executes modules for managing devices that associate with an embedded system. ‘The underlying principle is that at an instant, only one physical or virual device should get access to or from one task only. Sections 4.2.4 and 8.6.1 will describe device drivers and device management in detail, The OS also provides and manages virtual devices such as pipes and sockels. Sections 7.14 and 7.15 describe these in detail For designing embedded-software, two types of devices are considered: physical and virtual, Physical devices include keypad, printer ot display unit. A virtual device could be a file or pipe or socket or RAM disk, Device drivers and device manager software are needed in the system. The RTOS includes device- drivers and a device manager to control and facilitates the use of the number of physical and virtual dovices in the system, 1.4.8 Software Tools for Designing an Embedded System ‘Table 1.2 lists the applications of software tools for assembly language programming, high level language programming, RTOS, debugging and system integration. Table 1.2 Software modules and tools for designing of an embedded system ‘Software Toole “application Bator For writing C codes or assembly mnemonics using the keyboard ofthe PC for entering the program. Allows the enty, addition, deletion, inser, appending previously writen lines oF files, merging record and files atte specific positions. Creates a soure file that stores the edited file. It ls0 has an appropriate name [provided by the programmer}. Inerpreter For expression-by-expression (line-by-Tine) translation to machine-executable codes, ‘Compiter Uses the complete set of codes It may also inelude codes, funetions and expressions from the library tines. It ereates a file called objec file Assembler For translating assembly mnemonics into binary opeodes (instructions) that is, into ‘an executable file ealld binary file and for making. list file that ean be printed. The list, file has address, source code (assembly language mnemonics) and hexadecimal object ‘codes. The file has addresses that reallocate during the actual run of the assembly language program, (Contd)Enbected Syste Software Tools Application (Cross assembler For converting object codes or executable codes fora processor to other codes for another processor and vice versa. The cross-assombler assembles the assembly codes of the target processor asthe assembly codes of the processor ofthe PC used in system development. Later, it provides the object codes for the target processor. These codes will be the ones ‘actualy needed in the final developed system. Simulator ‘To simulate al functions ofan embedded system circuit including tha or additonal memory ‘an peripherals. tis independent ofa particular target system. It also simulates the processes that will execute when the codes of a particular processor execute. Souree-code For source code comprehension, navigation and browsing editing, debugging, configuring ‘enginosring software (disabling and enabling the C++ features) and compiling. RTOS Refer Chapters 8 w 10. Stethoscope For dynamically tracking the changes in any program variable or parameter. It demonstrates the sequence of multiple processes (asks, threads, service routines) that exeeute and also records the entire time history. ‘Trace seape ‘To help in tmeing the changes in modules and tasks with ime on the X-axis. A list of ‘actions also produces the desired time seales and the time expected w be taken for different tasks Inegrated development ‘This isa development software and hardivare environment that consists of simulators with ‘environment editors, compilers, assemblers, RTOS, debuggers, stethoscope, tracer, emulators, logic analyzers, and application code burners in PROM or fas. Prototyper ‘This simulates and does source code engineering including compiling, debugging and, ‘browsing and summarizing the complete status of the final target system during the development phase Locator? ‘This uses a erss-assembler ouput and a memory allocation map an provides the locator program output as a hex-file. Its the final step of the software design process or an ‘embedded system, "The loeatr program ouput isin the Intl hex file or Motorola Seco format. Software tools are used to develop software for designing an embedded system. Debugging tools, such as a stethoscope, trace scope, and sophisticated tools such as an integrated development environment «and prototype development tools, are needed for the integrated development of system sofiwareand hardware, 1.4.9 Software Tools Required ‘Table 1.3 gives the various tools needed to design exemplary systems. Exemplary Cases RTOS is essential in most embedded systems to process multiple asks and ISRs. Embedded systems for ‘medium scale and sophisticated applications need a number of sophisticated software and debugging tools,Introduction to Embedded Systems. Table 1.3 Software tools required in exemplary systems Software “Automatic ‘Data ‘Robot Mobile Adaptive Voice Tools Chocolae Acquisition Phone Cruise Control Processor Vending System ‘System with Machine! Siring Stabiis® Editor Yes Yes Yes Yes Yes NR Inerpreter Yes NR Yes NR NR NR Compiter Yes Yes Yes Yes Yes Yes Assembler Yes Yes Yes No No No Cross Assembler NR Yes Yes No No. No Locator Yes Yes Yes Yes Yes Yes Simulator NR Yes Yes Yes Yes Yes Source code engineering NR NR NR Yes Yes Yes software RTOS Yes MR Yes Yes Yes Yes Stethoscope NR NR NR Yes Yes Yes Trace scope NR NR NR Yes Yes Yes Tniegrated development NR Yes Yes Yes Yes Yes Prototyper NR No No Yes Yes Yes Note: NR means not required. MR means may he required in a specific complex system but not compulsorily needed “1.5 EXAMPLES OF EMBEDDED SYSTEMS Embedded systems have very diversified applications. A few select application areas of embedded systems are telecommunieations, smart cards, missiles and satellites, computer networking, digital eonsumer electronics, and automotives, Figure 1.9 shows the applications of embedded systems in these areas. ‘A few examples of small scale embedded system applications are as follows: 1, Point of sales tetminals: automatic chocolate vending machine 2. Stepper motor controllers for a robotics system 3. Washing or cooking systems 4. Multitasking toys ‘5. Mictocontroller-based single or multidisplay digital panel meter for voltage, current, resistance and Frequency Keyboard controller /. SD, MMI and network access cards 8. CD drive or hard disk drive controllerEnbected Syste 9. The peripheral controllers of a computer, or example, a CRT display controller, a keyboard controller, a DRAM controller, DMA controller, a printer controller, a laser printer controller, a LAN controller, aa disk drive controller 10, Fax or photocopy or printer or scanner machine 11. Remote (controler) of TV 12, Telephone with memory, display and other sophisticated features Telecom Missiles Satellites { { “Mobile Computing = Banking Defence Mobile Access “secuniy “Aerospace Communication @ o @ ‘Computer Networkin Digital Automotive Systems and Peripher ‘Consumer Electronics | = Motor Control System - Networking Systems -DvDs “Cruise Control “Image processing + Set op boxes: “ EnpinetBody Sefety = Printers High detntion TVs Robotics in Assembly Line "Networks Cards Digital cameras Cor cntahrn Monitors and Displays "Car Multimedia i’ & 0 Fig. 1.9 Applications of the embedded systems in various areas 13. Motor controls systems—for example, an accurate control of speed and position of the de. motor, robot and CNC machine; automotive applications such as elosed loop engine control, dynamic ride control, and an antilock braking system monitor 14, Electronic data aequisition and supervisory control system 15. Electronic instruments, such as an industrial process controller 16. Electronic smart weight display system and an industrial moisture recorder eum controller 17. Digital storage system fora signal wave form or for electric or water meter reading system 18, Spectrum analyzer 19. Biomedical systems such as an ECG LCD display cum recorder, a blood-cell recorder cum analyzer, and a patient monitor system Some examples of medium scale embedded systems are as follows:pe 20. Computer networking systems, for example, a router, a front-end processor in a server, a switch, a bridge, a hub and a gateway 21. For Internet appliances, there are numerous application systems (i) An intelligent operation, administration and maintenance router (IOAMR) in a distributed network and (ii) Mail client card to store e-mail and personal addresses and to smardy connect to a modem or server 22. Entertainment systems such as a video game and a musie system 23. Banking systems, for example, bank ATM and credit card transactions 24. Signal tracking systems, for example, an automatic signal tracker and a target tracker 25. Communication systems such as a mobile communication SIM card, a numeric pager, acellular phone, a cable TV terminal and a FAX transceiver with or without a graphic accelerator 26. Image filtering, image processing, pattern recognizer, speech processing and video processing 27. Video games 28. A system that connects a pocket PC to the automobile driver mobile phone and a wireless receiver ‘The system then connects to a remote server for Internet or e-mail or toa remote computer at an ASP {application service provider) 29. A personal information manager using frame buffers in handheld devices 30. Thin client (A thin client provides disk-less nodes with remote boot capability]. Application of thin- client accesses 10 a data centre from a number of nodes; in an Internet laboratory accesses to the Internet leased line through a remote server. 31. Embedded firewall / router using ARM7/ multiprocessor with two Ethernet interfaces and interfaces support to PPP, TCP/IP and UDP protocols Examples of sophisticated embedded systems ate as follows: 32, Mobile smart phones and computing systems. 33. Mobile computer 34, Embedded systems for wireless LAN and for convergent technology devices 35. Embedded systems for video, interactive video, broadband IPv6 (Internet Protocol version 6) Intemet and other products, realtime video and speech or multimedia processing systems 36. Embedded interface and networking systems using high speed (400 MHz plus), ultra high speed (10 Gbps) and a large bandwidth: Routers, LANs, switches and gateways, SANs (Storage Area Networks), WANs (Wide Area Networks) 37. Security products and high-speed Network security. Gigabit rate encryption rate products 1.6 EMBEDDED SYSTEM-ON-CHIP (Soc) AND USE OF VISI CIRCUIT DESIGN TECHNOLOGY Lately, embedded systems are being designed on a single silicon chip, called System on chip (SoC), a design innovation. SoC is a system on a VLSI chip that has all the necessary analog as well as digital circuits, processors and software, ‘A SoC may be embedded with the following components: 1. Embedded processor GPP or ASIP core, 2. Single purpose processing cores or multiple processors, 3. A network bus protocol core, 4. An eneryption function unitEmbed Sytem 5. Discrete cosine transforms for signal processing applications, 6. Memories, 7. Multiple standard source solutions, called IP (Intellectual Property) cores, 8 9, . Programmable logic device and FPGA (Field Programmable Gate Array) cores, Other logic and analog units An exemplary application of such an embedded SoC is the mobile phone. Single purpose processors, ASIPs and IPs on an SoC are configured © process encoding and deciphering, dialing, modulating, demodulating, interfacing the key pad and multiple line LCD matrix displays or touch sereen, storing data input and recalling data from memory. Figure 1.10 shows an SoC that integrates internal ASICs, internal processors (ASIPs), shared memories and peripheral interfaces on a common bus. Besides 2 processor, ‘memories and digital circuits with embedded software for specific applications, the SoC may possess analog circuits as well, ASYSTEMON CHIP a onan ar racer, oe a ee Wi ccon | = = a Fig. 1.10 ASoC embedded system and its common bus with internal ASIPs, internal processors, IPs, shared memories and peripheral interfacespe ®) 1.6.1 Application Specific IC (ASIC) ASICS are designed using the VIST design tools with the processor GPP or ASTP and analog circuitsembedded into the design. The designing is done using the Electronic Design Automation (EDA) tool. [For design of an ASIC, a High-level Design Language (HDL) is used 1.6.2 IP Core On 4 VLSI chip, there may be integration of high-level components, These components possess _gate-level sophistication in circuits above that ofthe counter, register, multiplier, floating point operation unit and ALU. A standard source solution for synthesizing a higher-level component by configuring an FPGA core or a core of VLSI circuit may be available as an Intellectual Property called (IP). The designer or the designing company holds the copyright for the synthesized design of a higher-level component for gate-level implementation of an IP. One might have to pay royalty for every chip shipped. An embedded system may ‘ncomporate several IPs An IP may provide hardwired implementable design of a sransform, an encryption algorithm or a deciphering algorithm. © An IP may provide a design for adaptive filtering of a signal An IP may provide a design for implementing Hyper Text Transfer Protocol (HTTP) or File Transfer Protocol (FTP) or Bluetooth protocol to transmit a web page or a file on the Internet. © An IP may be designed for a USB or PCI bus controller. [Sections 3.10.3 and 3.12.2] 1.6.3 FPGA Core with Single or Multiple Processors ‘Suppose an embedded system is designed with a view 0 enbancing functionalities in future, An FPGA core is then used in the circuits, It consists of large number of programmable gates on a VLSI chip. There is asetof gates ineach FPGA cell, called macro cell, Each cell has several inputs and outputs, Allcellsintereonnect like an array (matrix). Each interconnection is programmable through the associated RAM in an FPGA programming tool. An FPGA. core can be used with a single or multiple processor, ‘Consider the algorithms for the following: Fourier transform (FT) and its inverse (IFT), DFT or Laplace transform andits inverse, compression or decompression, enerypting or deciphering, specific pattem recognition (for recognizing a signature or finger print or DNA sequence), We ean configure an algorithm into the logic gates of FPGA. It gives hardwired implementation for a processing unit. It is specific the needs of the ‘embedded system, An algorithm of the embedded software can implement in one of the FPGA sections and another algorithm in its other section. FPGA cores with a single or multiple processor units on chip are used. One example of such core is Xilinx Virtex-II Pro FPGA XC2VP125. XC2VP125 from Xilinx has 125136 logic cells in the FPGA core ‘with four IBM PowerPCs. It has been used as a data security solution with encryption engine and data rate of 1.5 Gbps. Other examples of embedded systems integrated with logic FPGA arrays are DSP-enabled, real-time video processing systems and line echo eliminators for the Public Switched Telecommunication Networks (PSTN) and packet switched networks. [A packet is a unit of a message or a flowing data such that it ean follow a programmable route among the number of optional open routes available at an instance.]Embadded Systems 1.7 “COMPLEX SYSTEMS DESIGN AND PROCESSORS 1.7.1 Embedding a Microprocessor A General Purpose Processor microprocessor can be embedded on a VSLI chip. Table 1.4 lists different streams of microprocessors embedded in a complex system design, Table 1.4 Important microprocessors used in embedded systems Stream Microprocessor Family Source (CISC or RISC or Both features Stream 1 68H Motorola case Stream 2 8x86 nel cise Stream 3 SPARC Sun RISC Stream 4 ARM ARM RISC with CISC functionality 1.7.2. Embedding a Microcontroller Microcontroller VLSI cores or chips for embedded systems are usually among the five streams of families given in Table 1.5. Table 1.5 Major microcontrollers® used in the embedded systems ‘Stream Microcontroller Family ‘Source (CISC oF RISC oF Both Sueam | 6SHCHXx, HCI2xx, HCI6xx Motorola csc Seam 2 $051, 8051MX Inte, Philips cise Stream 3 PIC 16F84 or 16C76, 164876 and PICI8 Microchip case Stream 4° Microcontroller Enhancements of CORTEX-M3— ARM, Texas, Philips, RISC Core with ARMO/ARMT from Philips, Samsung and Samsung and ST CISC functionality ST Microelectronics Microelectronics ete “ other popular microcontllers areas follows. (i) Hitachi 8 family and SuperH Tx. (i) Mitsubishi 740, 7700, MI6C and [M32 fais. ii) National Semiconductor COPS and CR16 /16C. Gv) Toshiba TLCS 9008 (+) Texas Instruments MSP430 for low voltage batery based system, (4) Samsung SAME. (vi) Zglog 780 and e780 1.7.3 Embedding a DSP. ‘A digital signal processor (DSP) is a processor core or chip for the applications that process digital signals. [For example, filtering, noise cancellation, echo elimination, compression and encryption applications] Just, asa microprocessor is the most essential unit of a computing system, a DSP is essential unit of an embeddedIntroduction to Embedded Systems. system ina large number of applications needing processing of signals. Exemplary applications are in image processing, multimedia, audio, video, HDTV, DSP modem and telecommunication processing systems. DSPs also find use in systems for recognizing image pattern or DNA sequence. DSP as an ASIP is a single chip or core in a VLSI unit, It includes the computational capabilities of a ‘microprocessor and Multiply and Accumulate (MAC) units. A typical MAC has a 16 x 32 MAC unit. DSP executes discrete-time, signal-processing instructions. It has Very Large Instruction Word (VLIW) processing capabilities; it processes Single Instruction Multiple Data (SIMD) instructions: it processes Discrete Cosine Transformations (DCT) and inverse DCT (IDCT) functions. The latter are used in algorithms for signal analyzing, coding, filtering, noise cancellation, echo elimination, compressing and decompressing, etc. Major DSPs for embedded systems are from the three streams given in Table 1.6 Table 1.6 Important digital signal processor® used in the embedded systems Stream DSP Family Source Stream 1 ‘TMS320Cxx, OMAP! Texas Strwam 2 ‘Tiger SHARC Analog Deviee Stream 3 '5000xx Motorola Stream 4 PNX 1300, 1500" Phitips $F example, TMS320C62NX a fxed pot 200 MHz DSP (Section 2.3) Malia processor, which besides multimedia DSP operations, sso docs network steam data packet processing 1.7.4 Embedding an RISC A RISC microprocessor provides the speedy processing of instructions, each in a single clock-cycle. This facilitates pipelining and superscalar processing. Besides greatly enhanced capabilities mentioned above, there is great enhancement of speed by which an instruction from a set is processed. Thumb instruction set is a new industry standard that also gives a reduced code density in ARM RISC processor. RISCs are used ‘when the system needs to perform intensive computation, for example, in a specch processing system, 1.7.5 Embedding an ASIP ASIP is a processor with an instruction set designed for specific application areas on VLSI chip or core. ASIP examples are microcontroller, DSP, 10, media, network or other domain-specific processor. Using VLSI design tools, an ASIP with instructions sets required in the specifie application areas ean be designed. The ASIP is programmed using the instructions of the following functions: DSP, control signals processing, discrete cosine transformations, adaptive filtering and communication protocol-implementing functions 1.7.6 Embedding a Multiprocessor or Dual Core Using GPPs In an embedded system, several processors or dual core processors may be needed to execute an algorithm fast within a strict deadline. For example, in real-time video processing, the number of MAC operations needed per second may be more than is possible from one DSP unit. An embedded system then incorporates two oF more processors running in synchronization. An example of using multiple ASIPS is high-definition television signals processing. [High definition means that the signals are processed for a noise-free, echo-cancelled transmission, and for obtaining a flat high-resolution image (1920 x 1020 pixels) om the television sereen.] A cell phone or digital camera is another application with multiple ASIPs.Embadded Systems In a cell phone, a number of tasks have to be performed: (a) Speech signal-compression and coding (b) Dialing (c) Modulating and Transmitting (d) Demodulating and Receiving (e) Signal decoding and «decompression (f) Keypad interface and display interface handling (g) Short Message Service (SMS) protocal- based messaging (h) SMS message display. For all these tasks, a single processor does not suffice. Suitably synchronized multiple processors are used, ‘Consider a video conferencing system. In this system, a quarter common intermediate format—Quarter- CIF—is used. The number of image pixels is just 144 x 176 as against $25 x 625 pixels in a video picture on ‘TV. Even then, samples of the image have to be taken at arate of 144 x 176 x 30 = 760320 pixels per second and have to be processed by compression before transmission on a telecommunication or Viral Private Network (VPN). (Nore: The number of frames are 25 or 30 per second (as per the standard salopted) for real- time displays and in motion pictures.) A single DSP-based embedded system does not suffice to get real-time images during video conferencing, Real-time video processing and multimedia applications most often need a multiprocessor unit in the embedded system, ‘Multiple processors or dual core processors are used when a single microprocessor does not meet the reeds ofthe different tasks that execute concurrently, The operations of all the processors are synchronized to obtain optimum performance, 1.7.7 Embedded Processor/Embedded Microcontroller An embedded processor is a processor with special features that allow it to embed multiple processes into the system Real time image processing and aerodynamies are two areas when’ fas, precise and intensive caleulations land fast context switching (from one program 10 another) are essential. Embedded processor is the term sometimes used for processor that has been a specially designed such that it has the following capabilities 1. Fast context switching and thus lower lateneies of the tasks in complex real time applications. [Section 4.6] Fast context switching means that the calling program or interrupted service routine CPU registers save and retrieve fast [Section 46] 2. 32-bit or 64-bit atomic addition and multiplication, and no shared data problem in the operations with large operands with each operand placed in two oF four registers. [Section 7.8.1] 3. 32-bit RISC core for fast, more precise and intensive ealeulations by the embedded software Embedded microcontroller is the term sometimes used for specially designed microcontrollers that have the following capabilities: 1. When a microcontroller has internal RAM, large flash or ROM, timer, interrupt handler, devices and peripherals and there is no external memory or device or peripheral required for the given application. 2. Fast context switching and thus lower latencies of the tasks in complex real time applications. For example, ARM and 68HCIx microcontrollers save all CPU registers fast, ‘An embedded processor is term used for processors with fast processing, fast context-switching and atomic ALU operations. An embedded microcontroller is the term used for a microcontroller that has internal RAM, large flash or ROM, timer, interrupt handler, internal devices and internal peripherals and there is no ‘external memory or device or peripheral required for the given application.Introduction to Embedded Systems. @ Complex System Embedded Processors Table 1.7 gives different processors that can embed in a ‘complex system. Table 1.7. Processors in complex embedded systems Processor “Application "Advantage "Disadvantage General Purpose Microprocessor Microcontrolier bsp. Single purpose processors and application specific system processor Dual core processor Accelerator When intensive ‘computations are required, caches ae used ‘and pipeline and superscalar operations are nooded and large ‘embedded softwar is 10 be located in the external memory cores or chips. Used with internal memory. devices and peripherals and when ‘embedded software isto be located in the internal ROM or flash. Used with signal rocessing-elated instructions for filters, image, audi, and video ‘and CODEC operations. Control 10 and bus ‘operations and peripherals and devices. ‘To significantly enhance the performance ofthe system. ‘To accelerate the ‘execution of codes. A Hoating point ‘coprocessor accelerates mathematical operations and Java accelerator ‘accelerates Java code execution. No engineering cost for designing the processor No enginoeting cos for designing the processor with internal memory devices and peripherals. No engineering cost involved for designing the signal processor. ‘They support other processing units in the system and execute specific hardware processes fast Reduced engineering cost Increases performance by co-processing with the ‘main processor. ‘Additonal redundant execution units that are ‘ot needed in the given system design ‘Adkliional ‘manufacturing costs and redundant application tits which are not needed in the given system design. ‘Manufacturing cost may be high. In-house engineering cost of development, royally payments for an IP core of processor and Manufacturing cost, ‘dual core processors are cont Engineering cost of evelopment or royalty payments for IP core of processor and time-to ‘market cosEmbed Sytem A DSP for mobile phones, for example, OMAP of Texas Instruments, uses the effective power dissipation methods of dynamic switching both for power supply voltage and operating frequency of the CPU core. For a number of applications, the DSPs cores may not sulfice. Domain specific ASIPs have specific instruction sets, For IOs, network, media or security applications, smartcard, video game, palm top computer, cell phone, mobile-Internet, hand-held embedded systems, Gbps transceivers, Gbps LAN systems, satellite or missile systems, We need special processing units in a VLSI circuit designed to funetion as a processor with ‘an instruction-set for programmability. These special units are called domain-specific ASIP. 1.7.8 Embedding ARM processor Examples of Stream 4 GPPs in Table 1.4 are ARM 7 and ARM 9. The core of these processors can be embedded onto a VLSI chip or an SoC. An ARM-processor VLSI-architecture is available either as a CPU, chip or for integrating it into VLST or SoC. ARM, Intel and Texas Instruments and several other companies have developed such processors. ARM provides CISC functionality with RISC architecture at the core, The cores of ARM7, ARM9 and their DSP enhancements are available for embedding in systems. [Refer to ttp:/ wwwsi-comse/ docs/asic/modules/arm7.htm and arm9.htm} ARM integrates with other features (for example DSP) in new GPPs, which are available from several sources, for example, Intel and Texas Instruments. Exemplary ARM 9 applications are setup boxes, eable modems, and wireless-devices such as mobile handsets, ARMB bas a single cycle 16 x 32 multiple accumulate unit, It operates at 200 MHz It uses 0.15 wm GS30 CMOSs. It has a five-stage pipeline. It incorporates RISC core with CISC functions. It integrates with a DSP when designed for an ASIC solution. An example is its integration with DSP is TMS320C35x from Texas Instruments, [Refer to hitp:/www.i.com/se/doeslasie/modules/arm7 hum and arm9.htm] ‘A lower performance but very popular version of ARM is ARM. It operates at 80 MHz, Ituses 0.18 jum based GS20 jim CMOSs. Using ARM7, ARM9 and CORTEX-M3, a large number of embedded systems have recently become available Lately, a new class of embedded systems has emerged that additionally incorporates ASSP chips or cores in its design, 1.7.9 Embedding ASSP Assume that there is an embedded system for real-time video processing. Real-time processing arises for digital television, high definition TV decoders, set-up boxes, DVD (Digital Video Disc) players, web phones, vvideo-conferencing and other systems. An ASSP that is dedicated to these specific tasks alone provides a {aster solution. The ASSP is configured and interfaced with the rest of the embedded system. ‘Assume that there is an embedded system that using a specific protocol interconnects, its units through specific bus architecture to another system. Also, assume that suitable encryption and decryption is required. [The output bit stream eneryption protects messages or design from passing to an unknown external entity) For these tasks, besides embedding the software, it may also be necessary to embed some RTOS features [Section 1.4.6} Ifthe software alone is used for the above tasks, it may take a longer time than a hardwired solution for application-specific processing. An ASSP chip provides such a solution, For example, an ASSP chip [from i2Chip (http:/Avww:i2Chip com)] has a TCP, UDP, IP, ARP and Ethemet 10/100 MAC (Media Access Control) hardwired logic included into it. The chip from i2Chip, W3100A, is a unique hardwired Internet connectivity solution. Much needed TCP/IP stack processing software for networking tasks is thus available as ‘a hardwired solution. This gives output five times faster than a software solution using the system's GPP. It is also an RTOS-4ess solution. Using the same microcontroller in the embedded system to which this ASSP chipIntroduction to Embedded Systems. interfaces, Ethernet connectivity can be ackled. Another ASSP, which is now available, isthe “Serial-to-Ethermet ‘Converter (TIMTI00). It does real-time data processing by a hardware protocol stack. It needs no change in the application software or firmware and provides the most economical and smallest RTOS-solution, ‘An ASSPis used as an additional processing unit for running application specific tasks in place of processing using embedded software. “1.8 “DESIGN PROCESS IN EMBEDDED SYSTEM ‘The concepts used during a design process are as follows, 1. Abstraction: Each problem component is first abstracted. For example, in the design of a robotic system, the problem of abstraction can be in terms of control of arms and motors. 2. Hardware and Software architecture: Architectures should be well understood beforea design. 3. Extra functional Properties: Extra functionalities required in the system being developed should be well understood from the design, 4, System Related Family of designs: Families of related systems developed earlier should be taken into consideration during designing, 5, Modular Design: Modular design concepts should be used. System designing is fast by «decomposition of software into modules that are to be implemented. Modules shoukd be sueh that they ean be composed (coupled or integrated) later, Effective modular design should ensure effective (i) function independence, (i) cohesion and (ii) coupling, (a). Modules should be clearly understood and should maintain continuity. (b) Also, appropriate protection strategies are necessary for each module. A module is not permitted to change or modify another modile functionality. For example, protection fom a device driver ‘modifying the configuration of another device. 6. Mapping: Mapping into various representations is done from software requirements. For example, data flow inthe same path during the program Flow ean be mapped together asa single entity. Transform and transaction mapping design processes are used in designing. For example, an image is input data to a system; it can have a different number of pixels and colours. The system does not process each pixel and colour individually. Transform mapping of image is done by appropriate compression and storage algorithms. Transaction mapping is done to define the sequence of images. 7. User Interface Design: \ser interface design isanimportant part of design User interface are designed as per user requirements, analysis ofthe environment and system functions. For example, in an automatic chocolate vending machine (ACVM) system, the user interface is an LCD multiline graphics display. It can display a welcome message as well as specify the coins needed to be inserted into the machine for cach type of chocolate. The same ACVM may he designed with touchscreen User Interface (GUD, or it ‘may be designed with Voice User Interfaces (VUIs), Any of these interface designs has tobe validated by the customer. For example, he ACVM customer who installs the machine must validate message language and messages to be displayed before an interface design can proceed tothe implementation stage. 8, Refinements: Each component and module design needs to be refined iteratively tll it becomes the most appropriate for implementation by the software team. ‘The software design process may require use of Architecture Deseription Language (ADL). Its used for representing the following: (i) Control Hierarehy (i) Stuctoral Partitioning (ii) Data Structure and Hierarchy Aiv) Software ProceduresEmbed Sytem Figure 1.11 shows the activities for software-design eyele during an embedded software-development process and the eyele may be repeated till tests show the verification of specifications. Development Process Medel/ Analyse 1 ooquirerents of ‘System } ft Data Structure, Software 2 ‘Architecture, Interfaces ‘and Algorithme ‘thew Sequence one Ute Cycle Test Internal log and Extomnal functions END a 1.8.1 Design Metrics ‘A design process takes into account design metrics. There are several design metres for an embedded system, and these are listed in Table 1.8, 1.8.2 Abstraction of Steps in the Design Process ‘A design process is called bottom-to-top design if it builds by starting from the components, A design process is called top-to-down design if it first stars with abstraction of the process and then after abstraction the details are created. Top-to-down design approach is the most favoured approach. The following lists the five levels of abstraction from top to bottom in the design process; 1.11 Activities for software design during an embedded software-development processpe (1) Requirements: Definition and analysis of system requirement. It is only by a complete clarity of the required purpose, inputs, omputs, functioning, design metrics (Table 18) and validation requirements for finally developed systems specifications that a well designed system can be created. There has 10 he consistency in the requirements. Table 1.8 Design metrics used in the embedded systems Design Metrics Deseription Power Dissipation Performance Process deadlines User interfaces Ske Engineering cost Manufacturing cost Flexibility Protonype development time Timesto-market System and user safety Maintenance For many systems, particularly battery operated systems, such as mobile phone or digital ‘eamera the power consumed by the system is an important feature The battery needs t0 be recharged less frequently if power dissipation is smal. Instructions execution time in the system measures the performance, Smaller execution time means higher performance. For example, a mobile phone, voiee signals processed between antenna and speaker in 0.18 shows phone performance. Consider another. For example, a digital camera, shooting a 4M pixel sill image in 0.5s shows the eamers performance. ‘There are number of processes inthe system, for example, Keypad input processing, graphic display refresh, audio signals processing and video signals processing. These have deadlines within which each of them may be required to finish compatations and give results ‘These include keypad GUIs and VU. Size ofthe system is measured in terms of () physieal space required, (i) RAM in kB and internal flash memory requitements in MB or GB for running the software and for data storage and (i) number of million logic gates in the hardware Initial eost of developing, debugging and testing the hardware and software is ealled engineering cost and isa one-time non-recurring cost. (Cost of manufacturing each unit Flexibility in design enables, without any significant engineering cost, development of Giferent versions of a product and advanced versions later on. For example, software enhancement by adding extra functions necessitated by changing environment and software re-engineering. ‘Time taken in days or months for developing the prototype and in-house testing for system ‘functionalities. I includes engineering ime and making the prototype time, Time taken in days oF months alter prototype development to puta product for users and System safety in tems of aecidental fall from hand or table, theft (e.., a phone locking ability and tracing ability) and in terms of user safety when using a product (tor example, ‘automobile brake or engine), ‘Maintenance means changeability and additions to the system: for example, ang or updating software, data and hardware. Example of software maintenanee is additional service oF Functionality software. Example of data maintenanee is additional ring-tones, wallpapers, ‘video-clips in mobile phone or extending card expiry date in ease of smartcard. Example of ‘hardware maintenance is additional memory or changing the memory tick in mobile computer and digital camera,Embed Sytem (2) Specifications: Clear specifications of the required system are must. Specifications need to be precise. Specifications guide customer expectations from the product. They also guide system architecture, The designer needs specifications for (i) hardware, for example, peripherals, devices processor and memory specications, i) datatypes and processing specifications, i) expected system ‘bchaviour specifications, (iv) constraints of design, and (¥) expected life cycle specifications, Process specifications are analysed by making lists of inputs on events, outputs on events and how the processes activate on each event (interrupt (3) Architecture: Data modeling designs of attributes of data structure, dataflow graphs (Section 6.2), program models (Section 6.1), software architecture layers and hardware architecture are defined. Software architectural layers areas follows: 1 The first layer is an architectural design. Here, a design for system architecture is developed. The question arises as to how the different clements—data structures, databases, algorithms, control Funetions, state transition fanetions, process, data and program flow—are to be organised. 2. The second layer consists of data-design. Questions at this stage are as follows. What design of data structures and databases would. be most appropriate for the given problem? Whether data organised as a tree- like structure will be appropriate? What will be the design of the components in the data? [For example, video information will have two components, image and sound] 3. The third layer consists of interface design. Important questions a this stage are as follows. What shall be the interfaces to integrate the components? What is the design for system integration? ‘What shall be design of interfaces used for taking inputs from the data objects, structures and databases and for delivering outputs? What will be the port structure for receiving inputs and transmitting outputs? (4) Components: The fourth layer is a component level design. The question at this stage is as follows. ‘What shall be the design ofeach component? There isan additional requirement in the design of embedded systems, thateach component should be optimised for memory usage nd power dissipation. Components ‘ofhardware, processes, interfaces and algorithms. The following lststhe common hardware components: 1 Processor, ASIP and single purpose processors in the system 2. Memory RAM, ROM or internal and external flash or secondary memory in the system 3. Peripherals and devices internal and external to the system 4. Ports and buses in the system 5. Power source or battery in the system Daring software development process we can model the components as object-oriented, Table 1.9 lists the stages as components-based object-oriented software development process (5) System Integration: Built components ae integrated in the system. Components may work fine independenty, but when integrated may not fullil the design metrics. The system is made to function and validated. Appropriate tests are chosen. Debugging tools are used to correct erroneous functioning. Each component and its interface system is integrated alter the design stage. Program implementation isin ‘language and may use an integrated development environment (IDE), and source code engineering tools, which should follow the model, software architeeture and design specifications. Program simplicity should ‘be maintained during the implementation process. ‘The design stages range from abstraction to detailed designing to verification activities. Continuous ‘refinement in design can he made by effective communication between designers and implementers, Software design can be assumed to consist of four layers: architecture design, data design, interfaces design and ‘component level design.pe @) Table 1.9 Components-based object-oriented software development process Bort ‘Activities Model Deficiency Stage | Components that could be ase in software development identified Suge 2 Selection of available clases (single logically bonded groups) from a Need for robust interfaces software components resource library and slow development in Stage 3 Sort components, which are available and reusable by e-engineering and case the reusable Which are unavailable ‘components ae rot Suge 4 Re-engineer components and create unavailable components pebeeenkd Stage 5 Construct sofivsre from the components an test them Stage 6 Meratively construct tl final validation of software Actions at each step Research by software engineering experts have shown that on an average, a designer needs to spend about 50% of the time for planning, analysis and design, 40% for testing, validation and debugging and 10-15% on coding, Action required to be taken at each step in the design process is listed in Table 1.10. Table 1.10 Action to be taken at each step of design process Design Metrics Description Analysis Design is analyzed ‘Steps for improvement ‘The result of analysis is used to improve design w meet specifications and metres Verification ‘Systom design must be verified to ensue that it moots the design mets given in Table 1.8 1.8.3 Challenges in Embedded System Design: Optimizing Design Metrics Following are the challenges that arise during the design process. Amount and type of hardware needed: Optimizing the requirement of microprocessors, ASIPS and single purpose processors inthe system om the basis of performance, power dissipation, cost and other design metrics are the challenges in a system design. A designer also chooses the appropriate hardware (memory RAM, ROM or internal and external flash or secondary memory, peripherals and devices internal and external ports and buses and power source or battery) taking into account the design metrics given in Table 1.8; for ‘example, power dissipation, physical size, number of pates and the engineering, prototype development and ‘manufacturing costs Optimizing Power Dissipation and Consumption: Power, consumption during the operational and idle state of system should be optimal. The following methods are used to meet the design challenges. Clock Rate Reduction Power dissipation typically reduces 2.5 wW per 100 kHz of reduced clock rate So reduction from 8000 kHz to 100 kz reduces power dissipation by about 200 HW, which is nearly similar to when the clock is nonfunctional. [Remember, total power dissipated (energy required) may not reduce. ‘This is because on reducing the elock rate, the computations will take a longer time and total energy required ‘equals the power dissipation per second multiplied by computation time],Embadded Systems ‘The power 25 pW is typically the residual dissipation needed to operate the timers and few other units. By ‘operating the clock ata lower frequency or during the power-down mode of the processor, the advantages are as follows: (i) Power loss du to heat generation reduces. (i) Radio frequency interference also reduces due to the reduced power dissipation within the gates, [Radiated RF (Radio Frequency) power depends on the RF current inside a gate, which reduces due to increase in “ON” state resistance between drain and channel of each MOSFET transistor and that reduces heat generation, Voltage Reduction In portable orhand-held devices such asa cellular phone, compared w 5 V operation, a CMOS circuit power dissipation reduces by one sixth, ~(2V/SV)", in 2.0 V operation, Thus the time intervals. needed for recharging the batlery increase by factor of six Wait, Stop and Cache Disable Instructions An embedded system may need w be run continuously, without being switched off: the system design, therefore is constrained by the need to limit power dissipation while it is ON but is in ide state. Total power consumption by the system while in running, waiting and idle states should be limited. A microconuoller must provide for executing Wait and Stop instructions for the power-down mode. One way to reduce power dissipation i to cleverly incorporate into software the Wait and Siop instructions. Another isto operate the system atthe Towest voltage levels inthe idle state nd selecting power-down mode in that state, Yet another method isto disable use of certain structural units ofthe processor— for example, eaches—when not necessary and to keepin disconnected state those structure units that are not needed during a parcular software execution, for example timers or 10 units ‘Operations can be performed at low voltage or reduced clock rate in order to control power dissipation, For ‘embedded system software, performance analysis during its design phase must also include the analysis of power dissipation during program execution and during standby. An embedded system has to perform tasks continuously from power-up to power-off and may even he kept ‘ON’ continuously. Clever real-time programming by using “Wait” and ‘Stop’ instructions and disabling certain units when not needed is one method of saving power during program execution. Process Deadlines Meeting the deadline of all processes in the system while keeping the memory, power dissipation, processor elock rate and cost at minimum is a challenge. Flexibility and Upgrade ability Flexibility and upgrade ability in design while keeping the cost ‘minimum and without any significant engineering cost is a challenge. Flexibility and upgrade ability allow different and advanced versions of a product to be introduced in the market later on. Reliability Designing a reliable product by appropriate design, testing and thorough verification, is a challenge. The goal of testing isto find errors and to validate that the implemented software is as per the specifications and requirements, Verification refers to an activity to ensure that specific functions are correctly implemented. Validation refers to an activity to ensure thatthe system that has been created is as per the requirements agreed upon atthe analysis phase, and to ensure its quay “1.9 “FORMALIZATION OF SYSTEM DESIGN Formalization of system design is done using a top-down approach by abstraction (Section 1.8.2) and by ‘© Detailing requirements and specifications of hardware and sofwareIntroduction to Embedded Systems. ‘© Defining architectures of hardware and software ‘© Coding and implementation as per architecture ‘© Testing, validation and verification of system Since a diagrammatic model clears the design concepts better than abstraction, a modeling language, for formalization ean be used. The Universal Modeling Language (UML) is used. In UML, a designer deseribes the following 1. “User Diagram’, ‘Object Diagram’, ‘Sequence Diagram’, ‘State Diagram’, ‘Class Diagram’ and “Activity Diagram’ Classes and Objects, which describe identity, attributes, components and behaviour Inheritances of the classes and objects, Interfaces of the objects and their implementation atthe objects Structural description of the design components Behavioral description in terms of states, state machine and signals (Section 6.3) Events description Section 6.5 will describe UML in detail. Chapters 11 and 12 will describe the mode design examples in deta “1.10 “DESIGN PROCESS AND DESIGN EXAMPLES 1.10.1 System Design Process Examples Chapters 11 and 12 will deseribe design examples in detail 1.10.2 Automatic Chocolate Vending Machine (ACVM) Let us consider an automatic chocolate vending machine. This interesting example given here helps a reader 1 understand several concepts of programming an embedded system as a multitasking system. Figure 1.12 shows the diagrammatic representation of ACVM, Assume that ACVM has following component 1, Ithas keypad on the top of the machine, That enables a child to interact with it when buying a chocolate ‘The owner ean also command and interaet with the machine. 2. Ithas an LCD display unit on the top of the machine. I displays menus, text entered into the ACVM. and pictograms, welcome, thank you and other messages, It enables the child as well as the ACVM ‘owner to graphically interact with the machine. It also displays time and date. (For GUIs, the keypad and LCD display units or touch screen are asic units.) Ithas a coin insertion slotand a mechanical coin sorter so that chil ean insert coins to buy a chocolate. thas a delivery slot so that child can collect the chocolate and eoins, if refunded. It has an Internet connection port using a USB based wireless modem so that owner can know status of the ACM sales from a remote location, ACVM Functions Assume that ACVM functions are as follows: 1. The ACM displays the GUIsand ifthe chikd wishes to enter contact information, birthday information or get answer to FAQs, it displays the appropriate menu, 2. Itdisplays a welcome message when in idle state, It also continuously displays time and date at the right botiom comer of display screen. It ean also intermittently display news, weather data or advertisements or important information of interest during idle stateEmbadded Systems 3. When first coin is inserted, a timer also stars, The child is expected to insert all required coi 2 minutes, 4. After 2 minutes the ACVM will display a query to the child if the child does not insert sufficient coins. If the query is not answered the coins are refunded, 5. Within 2 minutes if sufficient coins are collected, it displays the message, “Thanks, wait for few moments please!”, delivers the chocolate through the delivery slot and displays message, “Collect the chocolate and visit again, please!” Hardware units ACVM embeds the following hardware units, Microcontroller or ASIP (Application Specifie Instruction Set Processor) . RAM for storing temporary variables and stack ROM for application codes and RTOS codes for scheduling the tasks Flash memory for storing user preferences, contact data, user address, user date of birth, user identification code, answers of FAQs ‘Timer and interrupt controller A TCPAP port (Internet broadband connection) 10 the ACYM for remote control and for the owner 10 get ACYM status reports 7. ACYM specific hardware to sort coins of different denominations. Each denomination coin generates set of status and input bits and port-interrupts. Using an ISR for that port, the ACVM processor reads the port status and input hits, The bits give the information about which coin has been inserted. After ceach read operation, the status bits are reset by the routine 8. Power supply evra ecu ‘or Touch Sereen for user Koved LCD Display Touch Seren for mame ‘Microcontrler based hardware Coin Sorter USB Wireless. RTOS Embedded Sofware Modem Fig. 1.12 Diagrammatic representation of the ACVM Software components ACVM embeds the following software components . Keypad input read task >. Display task Read coins task for finding eoins sorted Deliver ehocolate task 5. TCPIP stack processing task 5. TEPIP stack communication task 1.10.3 Smart Card ‘Smart card is one of the most used embedded system today. It is used for eredit-debit bankcard, ATM card, purse or e-Wallet card, identification card, medical card (For history and diagnosis details) and card for ape ®) number of new innovative applications. [Reader may refer to a frequently updated website, htip:// ‘worw.sguihery @tise.net forthe answers of frequently asked questions about cards,] The security aspect is of paramount importance for smartcard use, when used for financial and banking-related transactions. [Reader may refer to hup:/www-home.hkstarcom/~alanchan/papersismantCardSecurity/ and hitp/iwww.esearch. ibm.com/secure_system/scard.him for details of the card-security requirements] ‘The smart card isa plastic eard ISO standard dimensions, 85.60 x 53.98 x 0.80 mm. It is an embedded system on a cand: SoC (System-On-Chip). SO recommended standards are IS07816 (1104) for host-machine contat-hased cards and ISO1443 (Part A or B) for the contactless cards. The silicon chip is just a few ‘multimeter in size and is concealed in-between the layers. Is very small size protec the card from bending. Figure 1.13 shows embedded-system hardware components fora contactless smart card. [An Embedsed System Contac-ess Smart Card Components RAM ROM EEPROM (Temporary (Application (Applicaton Variabies) and RTOS) ‘ariabies) Data, Address, Conta Internal Buses [Account Number, Expiry Date, Card Number I |_| iets “s Theron seme] [oneve clue mores | | Amamce | | mp Sanit Conn ‘Shifted Circuit key Wado Sea | | Sten Power suppy Tame ina Fig. 1.13 Embedded hardware components in a contact less smart card Embedded Hardware ‘The embedded hardware components are. follows: Microcontroller or ASIP RAM for temporary variables and stack One time programmable ROM for application codes and RTOS codes for scheduling the tasks Flash for storing user data, user adress, usr identification codes, eard number and expiry date ‘Timer and interrupt conttoller ‘Acattir fequency ~16 Miz generating Interfacing citeuit forthe 10s Charge pump for delivering power tothe antenna for transmission and for system circuits. The charge Pump stores charge from received RF (radio frequency) at the card antenna in its vicinity. [The charge pump isa simple citeuit that consists ofthe diode and high vale ferroclcttics materal-hased capacitor] ‘The details ofthe basic hardware units are as follows: cuit and Amplitude Shifted Key (ASK) modulatorEmbed Sytem 1. The Microcontroller used can be MC68HCI1DO or PICIGC84 or a smart card processor Philips Smart XA ora similar ASIP Processor. MC6SHCIIDO has 8 KB internal RAM and 32 kB EPROM and 2/3 wire protected memory. Most cards use &-hit CPUs. The recent introduction in the cards is of a 32-bit RISC CPU, A smart card CPU should have special features, for example, a security lock. The lock is fora certain sections of the memory. \ protection bit at the microcontroller may protect | KB. ‘or more data from modification and access by any extemal source or instructions outside that memory. ‘Once the protection bit is placed at the maskable ROM in the microcontroller, the instructions or data ‘within that part of the memory are accessible from instructions in that part only (internally) and not accessible from the external instructions or instructions outside that part. The CPU may disable access by blocking the write cycle placement ofthe data bits on the buses for instructions and data protection a the physical memory after certain phases of card initialization and before issuing the card to the user. Another way of protecting is as follows: ‘The CPU may access by using the physical addresses, which are different from the logical address used in the program, 2. ROM is used in the card. The usual size is 8 or 64 KB for usual or advanced eryptographie features in the card, respectively. Full or part of ROM bus activates only after a security check. The processor protects a part of the memory from access. The ROM stores the following i, Fabrication key, which is a unique secret key for each card, Its inserted duting fabrication ii, Personalization key, which is inserted after the chip is tested on a printed eircuit board. Physical addresses are used in the testing phase, The key preserves the fabrication key and this key insertion preserves the card personalization, After insertion of this key, RTOS and applications use only logical addresses. ili, RTOS codes iv. Application codes v, A utilization lock to prevent modification of two PINs and to prevent access to the OS and application instructions. It stores after the card enters the utilization phase 3. EEPROM or Flash is scalable, These means that only that part of the memory required fora particular ‘operation will unlock for use. The authorizer will use the required part; the application will use the ‘other part. It is protected by the access conditions stored therein. It stores the following: i, PIN (Personal Identification Number), the allotment and writing of which is by the authorizer (for ‘example, hank) and its use is possible hy the latter only by using the personalization and fabrication keys. It is for identifying the card user in future transactions. Card user is given this key. Alternatively, « modifiable password is given to the user and password opens the PIN key, ii, An unblocking PIN for use by the authorizer (say the bank). Through this key, the card circuit idemifies the authorizer before unblocking. Data of the user unblocks for the authorizer and storing of information on the eard is possible by the authorizer through the host. iii, Access conditions for various hierarchically arranged data files. iv, Card user data, for example, name, bank and branch identification number and account number or health insurance details, ¥. Data post issue that the application generates. For example, in case of e-purse, the details of previous transactions and current balance, Medical history and diagnosis details and/or previous insurance claims and pending insurance claims record in case of a medical card ‘vi, It also stores the application's non-volatile data vii, Invalidation lock sent by the host after the expiry period or eard misuse and user account closing request. It locks the data files of the master or elementary individual file or both 4. RAM stores the temporary variables and stack during card operations by running the OS and the application,Introduction to Embedded Systems. 5. Chip power supply voltage exiracts by a charge pump circuit, The pump extracts the charge from the signals from the host analogous to what a mouse does in a computer and delivers the regulated voltage to the card chip, memory anc! IO system. Signals can be from antenna or from elock pin. In a typical ‘card operation using 0.18 4m technology, 1.6 05.5 V isthe threshold limit and for 0.35 um technology, 271053 V. 6. IO System of chip and host interact through asynchronous serial UART (Section 3.2.3) at 9.6 k or 106 k or 115.2 k aue/s. The chip interconnects to a card hosting system (reader and writer) either ‘through the gold contacts or through a centimeter sized antenna on each side. The latter provides ‘contactless interconnection between the [O pins, which are meant for conract-based imeraction, RST (Reset Signal from host) and Clock (from host). ess Communication for 10 interaction is by radiations through the antenna coils for contactless interaction, The card and host interact through a card modem and a host modem, The application protocol data unit (APDU) is a standard for communication between the eard and host computer. ‘Modulation is with 10% index amplitude modulating carrier of 13.66-13.56 Mbps ASK (amplitude shifted keying) is used for contactless communication at data rates of ~1 Mbps, One-sixteenth frequency subcarrier modulates through BPSK (Binary Phase Shifted Keying). Embedded Software Smart card embeds the following software components: Boot-up initialisation and OS programs Smart card secure file system Connection establishment and termination ‘Communication with host . Cryptography algorithm Host authentication Card authentication Saving addition parameters or recent new data sent by the host (for example, present balance left) ‘The smart card is an exemplary secure embedded system with security software. The eard needs eryptographic software, Embedded software in the card needs special features in its operating system over and above the MS DOS or UNIX system features, Special Features needed are as follows: Protected environment. It means software should be stored in the protected part of the ROM. . Restricted run-time environment Its OS, every method, cass and run time library should be scalable. Code-size generated should be optimum. The system needs should not exceed 64 kB memory. Limited use of data types: multidimensional arrays, long 64-bit integer and floating points and very limited use ofthe error handlers, exceptions (Section 4.2.2), signals (Sections 6.5 and 7.10), serialization, debugging and profiling. (Serialization is the process of converting an object into a data stream for transferring it to network or from one process to another. The de-serialized data are the receiver end] 6. A three-layered filesystem for the data. One file forthe masier file to store al file headers. A header means file status, avcess conditions and the file lock. The second file is a dedicated fle o hold a file ‘grouping and headers of the immediate successor elementary files of the group. The thid file is the elementary file o hold the file header and its file data. 7. There is either a fixed length file management or a variable length file management with each file having a predefined offset. 8. Classes for the network, sockets, connections, data grams, characterinput output and stream, security management, digital-ertfication, symmetric and asymmetric keys-based cryptography and digital signatures,Embed Sytem 1.10.4 Digital Camera Digital cameras may have 4 to 6 M pixel still images, clear visual display (ClearVid) CMOS sensor, 7 em wide LCD photo display sereen, enhanced imaging processor, double amt blur solution and high-speed processing engine, 10X optical and 20X digital zooms and can also record high definition video-clips. It therefore has speaker microphone(s) for high quality recorded sound. It has an audio/video out port for connecting t a TV/DVD player or computer Let us assume that the camera is still just a camera. Figures 1.14(a) and (b) show hardware and software components in a simple digital camera, Assume that the eamera has the following components: LGD or Touoh sore for frame view Keys: eco DAC ‘ADC z ash Mor Microcoriroer, Bluetooth Flash Memory ae ASIP CODDSP USB Pont Embedded Software Serial COM Microcontrolior ‘Computer a) ght, flash and display device drivers ‘CCD signal processing task Pixel co processing task JPEG coder “JPEG decoder LGD, Bluetooth, COM and USB Por device aivers (0) 1.14 (0) Digital camera hardware components (b) Digital camera software components 1. thas keys on the camera, That enables a user to operate the camera. Ithas navigation keys wo navigate ‘through the images hack and forth, 2. Shutter, lens and charge coupled device (CCD) array sensors for images in sizes 2592 x 1944 pixels = 5038848 pixels, VGA (E-mail) 640 x 480 = 307200 pixels, 2592 x 1728 = 3.2 M pixels, 2048 x 1536 pixels = 3 M pixels, of 1280 x 960 pixels = IM pixels, 3. Ithas a good resolution photo quality LCD display unit on the back of camera to show photographs ‘oF recorded video-clips. It displays text such as image-title, shooting data and time and serial number. It displays messages. It displays the GUI menus when the user interacts with the camera, 4. Ithas a self-timer lamp for flash. ‘5. Internal memory flash to store OS and embedded software, and limited number of image files 6. Flash memory stick of 2 GB or more for large storage.pe 7. Ithas Universal Serial Bus (USB) port (Section 3.10.3) or Bluetooth interface, which connects it to a ‘computer and printer. Camera Functions Assume that the camera functions is as follows 1. It displays the frame view on the LCD screen so that user can adjust the camera inclination before shooting the Frame. 2. Itdisplays the saved images on the LCD using navigation keys. 3. When a key for opening the shuter is pressed, the flash lamp glows and the self-timer cireuit switches off the lamp automatically 4. The frame light falls on the CCD array, which transmits the bits for each pixel in each row in the frame through an ADC. Bits from dark area pixels in each row are used for offset corrections in the CCD. signal for light intensities in each row. ‘5. The CCD bits of each pixel in each row and column are offset corrected using a CCD signal processor (CCDSP). 6. The processed signals are compressed using a JPEG CODEC and saved in one jpg file for each frame. ‘A DSP does compression using the the discrete cosine transformations (DCTS) and decompression by inverse DCT. Thereafter, it also does Huffman coding for JPEG compression, 7. A DAC sends the inputs for the display unit. The DAC gets the input from the pixel processor, whieh {gets the inputs from the JPEG files for the saved images and gets input directly from the CCDSP through the pixel processor or the frame in the present view Digital Hardware units ‘The camera embeds the following hardware units Microcontroller or ASIP Muitiple processors (CCDSP, DSP, pixel processor and others) RAM for storing temporary variables and stack ROM for application codes and RTOS codes for scheduling tasks ‘Timer, flash memory for storing user preferences, contact data, user address, user date of birth, user identification code, ADC, DAC and interrupt controller (Sections 1.3.3, 135, 1.3.7 and 1.3.11) . USB controller (Section 3.10.3) Direct memory access controller (Section 4.8) LCD controller (Section 3.3.4) Battery Software components The camera embeds the following software components: |. CED signal processing for off-set correction . IPEG coding JPEG decoding |. Pixel processing before display ‘Memory and file systems Light, flash and display device drivers COM, USB port and Bluetooth device drivers for port operations for printer and computer communication control 1.10.5 Mobile Phone “The mobile phone today has a large number of features. It has sophisticated hardware and software,Embed Sytem Hardware units _ A mobile phone embeds an SoC (System-on-Chip) integrating the following hardware units. 1. Microcontroller or ASIP [An ASIP is configured to process encoding and deciphering and another does the voice compression. Third ASIC dials, modulates, demodulates, interfaces the keyboard and touch screen or multiple line LCD graphic displays, and processes the data input and recall of data from memory] DSP core, CCDSP, DSP, video, voice and pixel processors Flash, memory stick, EEPROMs and SRAMs Peripheral circuits, ADC, DAC and interrupt controller Direct memory access controller (Section 4.8) LCD controller (Section 3.3.4) Battery Software components The mobile phone software development tools are as follows: 1. OS (Windows Mobile, Palm, Symbian) or BREW 2. Java 2 Micro Edition (J2ME) along with KVM as a Java Virtual Machine (S 3. Jaya Wireless toolkit with JDK (lava Development Kit) ‘The mobile phone embeds the following software components: 1. Memory and file systems 2. Keypad, LCD, serial, USB, 3G or 2G port device drivers for port operations for keypad, printer and computer eommunication control 3. SMS (Short Messaging Service) message creation and communicator, contact and PIM (personal information manager), task-to-do manager and email ‘Mobile imager for uploading pictures and MMS (multimedia messaging service) Mobile browser for access to the Web Downloader for Java games, ring-tones Simple camera with (Section 1.10.4) Bluetooth synchronization, IrDA and WAP connections support (Section 3.13) sction 5.7.4) ‘games, wall papers 1.10.6 Mobile Computer ‘The mobile computer has Windows CE or Windows mobile as OS. It has a touch sereen for GUI, The user _use$ a stylus to enter commands, It has a virtual keypad (the keypad displayed on the screen and entries of text and commands is through the stylus, In addition to phone, a mobile computer has following software components: 08 (Windows CE, Windows Mobile, PocketPC, Palm OS or Symbian OS) ‘Touch screen GUls, memory and file systems Memory stick Outlook, Internet explorer, Word, Excel, Powerpoint, and handwritten text processor Applications or enterprise software 1.10.7 A Set of Robots Consider a set of 8 robots. One robot is the master robot (music director) and seven are slave robots (conductors). Assuine tha the sets used t0 play an orchestra, Figures 1.14) and (b) show hardware and software components in the set of robots, Assume that the robot has the following components, 1, The master robot signals the commands and slave robots play accordingly.pe @) 2, Bach robot is assumed to have five degrees of freedom. Each robot has @ mechanical system of five degrees of freedom. At each degree of freedom, there is @ servomotor. A servomotor controls by PWM method (Section 1.3.7). Each motor is controlled in a sequence to let the robot perform the desired action, 3. Bach robot has a microcontrolier with expansion ports, PO, .., P8. Actually a single ASIC can perform multiple port functions of a microcontroller. However since the engineering cost of ASIC development, is high, a general purpose microcontroller 68HC12 or 8051 is used. |. The port outputs connect the motors and PWM outputs drive the motors in each robot. 5. Bach robot has a serial 1O with IrDA protocol. (Section 3.13.1) Internal memory flash to store the OS, embedded software and limited amount of music. /. There is a music file processor for playing the music. Slave robots have speaker outputs for playing ‘Master Robot Functions Assume that master robot functioning is as follows: 1. Itreceives commands from a remote controller to start and stop the musie and the code for the specifie orchestra to be played It sends PWM signals to the ports for moving the sticks in both hands as per the program. Itestablishes and binds the sockets (the viral deviees) connection withthe slaves. It sends the signals through sockets using IrDA protocols. The byte streams response to the clients are as per the music file to be played by the slave, ‘Slave Robot Functions Assume that slave robot functioning is as follows: 1. Itestablishes and binds the sockets (the viral devices) connection with the master 2. Itreceives from a master socket the commands aceept (and write (: it also receives commands to start and stop music and the code forthe specific orchestra to be played. 3. Itreceives the signals through sockets using IrDA protocols. The byte streams from the server are as per the musi file heing played. Hardware units Robots embed the following hardware units Microcontroller or ASIP Music file processor RAM for storing temporary variables and stack ROM for application codes and RTOS codes for scheduling robot actions and tasks ‘Timer, flash memory for storing user preferences and music files [EDA controller (Section 3.13.1) Direct memory access controller (Section 4.8) .. Power supply source or battery Software components Robots embed the following software components Socket fonctions Musi coding Music decoding Memory and file systems Light, lash and display device drivers InDA and socket port device drivers Motor drivers 10 ISRsEmbadded Systems Sees aa Nolo Buewoh || Rashiemory ieaosonvoer, Terr, bhi Pat WA Robot @ Cent and sever sookeis Musi fe processing [HDA protocol stack Bluetooth protocol «| LAs nswument and Bstoth or WDA devew divers 11.15 (a) Hardware components in the set of robots (b) software components in the set of, robots in which a master robots signals the commands and slave robots play according to the signals from the master “1.11 “CLASSIFICATION OF EMBEDDED SYSTEMS ‘We can classify embedded systems into three types as follows, 1. Small scale embedded systems: Those systems are designed with a single 8- or 16-bit microcontroller: they have little hardware and software complexities and involve board-level design. ‘They may even be battery operated. When developing embedded software for these, an editor, assembler and eross assembler an integrated development environment (ISE) tol specifi t the microcontroller fr processor used, are the main programming tools. Using °C” language, programs are compiled into the assembly and executable codes are appropriately located in the system memory. The software has to fit within the memory available and keep in view the need to limit power dissipation when the system is running continuously. Medium scale embedded systems: These systems are usually designed with a single or a few 16- or 32-bit microcontrollers, DSPs or RISCs. These systems may also employ the readily available single purpose processors and IPs (explained later) for the various functions—for example, bus interfacing. [ASSPs and IPs may also have to be appropriately configured by the system software before being integrated into the system-bus.] Medium scale embedded systems have both hardware and software complexities. For complex software design the following programming tools are available: C/C+4/Visual C+4Hava, RTOS, source code engineering tool, simulator, debugger and an integrated development environment. Software tools also provide solutions to hardware complexities. 3. Sophisticated embedded systems: Sophisticated embedded systems have enormous hardware and software complexities and may need several IPs, ASIPs, scalable processors or configurable processors and programmable logic arrays. They are used for cutting edge applications that need hardware and software co-design and components that have to be integrated inthe final system. They are constrained by the processing speeds available in their hardware unis, Certain software Functions such as eneryptionIntroduction to Embedded Systems. and deciphering algorithms, diserete cosine transformation and inverse transformation algorithms, TCPY IP protocol stacking and network driver functions are implemented inthe hardware to obtain additional speeds. The software implements some of the functions of the hardware resources in the system. Development tools for these systems may not be readily available ata reasonable cost or may not be available at all In some cases, a compiler or retargetable compiler might have to be developed for these. [A retargetable compiler is one that configures according to the given target configuration in a system. “1.12 “SKILLS REQUIRED FOR AN EMBEDDED SYSTEM DESIGNER "An embeded system designer hs o develop a product using the available tools within the given specifications, cost and time frame. {Chapters 6, 13 and 14 will cover the design aspects of embeded systems.} 1. Skills for Small Scale Embedded System Designer: Author Tim Wilmshurst in his book states thatthe following skill are needed in the individuar::?°" or team that is developing a small- scale system: “Full understanding of microcontrollers with abasic knowledge of computer architecture, digital electronic design, software engineering data communication, control engineering, motors and actuators, sensors and measurements, analog electronic design and IC design and manufacture Specific skill ill be needed in specifi situations. For example, contol engineering knowledge willbe needed for design of control systems, and analog electronic design knowledge will be needed when designing the system interfaces. The basic aspects of the following topies will be described in this book to prepare the designer who already has a good knowledge of the microprocessor or microcontroller to he used. (i) Computer architecture and organization. (ii) Memories. (iii) Memory allocation (iy) Interfacing memories. (¥) Burning (a term used for porting) the exceutable machine codes in PROM or ROM, (v} Use of decoders and demultiplexers (vi) Direct memory accesses. (vi) Ports. (vi) Device drivers inassembly. (x) Simple and sophisticated buses. (x) Timers. (i) Interrupt servicing mechanism. (xi) C programming elements. (xii) Memory optimization. (xiv) Selection of hardware and mierocontoller (xv) Use of Ia-Circut-Emulators (ICE), eros-assemblers and testing equipment. (avi) Debugging the software and hardware bugs by using test vectors. Basie knowledge in other areas—software engineering, data communication, contol engineering, motors and actuators, sensors and measurements, analog electronic design and IC design and manufacture—ean be obtained from the standard text books available, A designer interested in small-scale embedded systems may not need at all concepts of interrupt latencies and deadlines and their handling, the RTOS programming tools described in Chapters 9 and 10 and the program models given in Chapter 6. 2. Skills for Medium Scale Embedded System Designer: Knowledge of ‘C'/C-++/Java programming, RTOS programming and program modeling skills are must to design medium-seale cmbedded-system, Knowledge of the following ate critical. () Tasks or threads and their scheduling by RTOS. (ii) Cooperative and preemptive scheduling. (i) Inter processor communication functions. iv) Use of shared data, and programming theertical sections and e-etrant functions.) Use of semaphores, mailboxes, queues, sockets and pipes. (i) Handling ofinterrupt-latencies and mectng task deadlines. (vi) Use of various RTOS funetions, (ii) Use of physical and virtual device drivers [Refer to Sections 4.2.6, 7.10 and7.11,] Chapters 410 10 give detailed descriptions of these seven along with examples, and Chapters, 11 and 12 provide on understanding of ther se withthe help of ease stdies. A designer must have access to an RTOS programming tool with Application Programming Interfaces (APIs) for the specific microcontroller to be used. Solutions o various functions like memory-alloation, timers, device drivers, and interrupt handing mechanism are readily available as the APIs of the RTOS. The designer needs toEmbadded Systems {know only the hardware organization and use ofthese APIs. The microcontroller or processor then represents a small system element for the designer and alittle knowledge may suffice. 3. Skills for Sophisticated Embedded System Designer: 4 team is needed to co-design and solve the high level complexities of hardware and software design, Embedded system hardware engineers should have skills in hardware units and basie knowledge of ‘C'sC++ and Java, RTOS and ‘other programming tools. Software engineers should have basic knowledge in hardware and a thorough knowledgeof ‘C’, RTOS and other programming tools. final optimum design solution is then obtained. by system integration. ‘= An embedded system is one that has embedded software in a computer-hardware, which makes it a system 0 transition (negative edge) on the line for a period equal to reciprocal of baud rate. The baud rate is preset at both receiver and transmitter. The receiver detects the start it at middle of the interval, logic 0 state of the transmitter stat bit, 3. UART bits, when sending a byte, consist of start bit, 8 data bits (for example, for an ASCH character ‘or for a command word), option programmable bit (P-bit) and stop bit, each during the interval BT. ‘When sending or receiving a byte, the logic states during interval 10 8T or 11 BT are as shown in Figure 3.1(c) as a function of time t. A bit period, BT is equal to the reciprocal of baud rate, the rate at Which the bits from UART transmitter are sent. One extra bit before the stop bit is programmable Dit P and is called TBS at the transmitter and RBS atthe receiver. ‘The data bits in certain specific cases can be 5 or 6 or 7 instead of 8. ‘The stop bit can be for a minimum interval of 1.5 BT or 2 BT instead of 8T in certain specific cases. Optional programmable bit (P-bit) can be used for parity detection or can be used to specify the purpose of the serial data hits that are before the P-bit, For example, P can specify bits as the bits of a control or command word when P = 1 and data bits when P= 0, Bit P can specify the address of receiver when P= | and data when P = 0 so that only the addressed receiver wakes up and receives the «data in the subsequent data transfers. When P is used as addresvdata specification, it provides a means, to interface a number of UART devices through a com ART bus. UART 16550 includes a 16-byte FIFO buffer and is nowadays used more commonly as compared to the ‘original IBM PC COM port, which had an 8-bit register at UART port and was hased on 8250 and did not include the FIFO butter jon set of TxD and RxD lines and form a UARTT serial port communication is usually either in 10 bits or in 11 bits format: one start bt, 8 data bits, ‘one optional bit and one stop bit. UART communication can be full duplex, which is simultaneously both \ways, of half duplex, which is one way. tis an important communication mode. 3.2.4 HDLC Protocol ‘When data are communicated using the physical devices on a network, synchronous serial communication ‘may be used. HDLC (High Level Data Link Control) is an International Standard protocol for a data link network, It is used for linking data from point to point and between multiple points. It is used in telecommunication and computer networks. It is a bit-riented protocol, The total number of bits is not necessarily an integer multiple of a byte or a 32-bit integer. Communication is full duplex. Table 3.3 gives the synchronous network device port bits in an HDLC protocol, The reader may refer to a standard textbook, for example, “Data Communications, Computer Networks and Open Systems” by Fred Halsall from Pearson Education (1996) for details of HDLC and is field bits.Table 3.3. Format of bits in synchronous HDLC protocol-based network device ‘SNe. ‘Bi! at Part Present Compulsory ‘Explanation ‘or Optional 1 Frame start and end sign- Compulsory Flag bits at start as well as at end are (01111110) ling fag bits 2 Address bits for ‘Compulsory '8-bis in standard format and 16-bits in extended destination format Sa Control bits Case 1 ‘Compulsory as per First bit 0, next 3 bits N(S), next bit P/F and, information frame cease 1 or 20r3 last 3 bits N(R) in standard format N(R)? and NGS) = 7 bits each in extended format 36 Control bits case 2: — Fist two bits (10), next 2 bits RR? or RNR or supervisory frame [REI or SREJ, next bit P/F and last 3 bits N(R) in standard format. N(R)* and N(S)* = 7 bits ‘each in extendd format 3e Control bits Case 3: an — First two bits (11), next 2 bits M’, nex bit PAE rhumbered frame ‘and last bit remaining bits for M. [8 bis are ‘immaterial alter M bits in extended format] 4 Data bits Compulsory 1m frame bits transmit such that each bits atthe line for time AT or, each frame is atthe line for time m.AT and also there i bit stuffing 5 FCS (Frame check Compulsory {6-bits in standard format and 32 in extended sequence) bits format 6 Frame end flag bits Compulsory Flag bits at end are also (01111110) “Bits re given in onder oftheir transmission or reception 2PAF = and P means when a primary station (Command device) i polling the secondary satin (teceiving device). PIF = 1 and F means when receiving device has no data to transmit, Usual itis Jone inks frame. SRR, RNR, REJ and SREJ are messes to convey ‘Receiver realy” "Receiver nt read.” “Rejc’ and ‘Seletive rej. RED ‘or SREJ isa negative acknowledgement (NACK). NACK is sent nly when the ae i vejected {Achill ries only hen mile {snot give om need, else it remains sil "Reject means thatthe receiver received a Irame ot-of-sequence: its ejected and ‘repeat transmission o ll the ames fom the pint of fame rejection is requested using REI Sclectve ree” moans that 8 Frame is received out-of sequence: To he rejected aaa selective repeat transmission i requested fo this frame Using SRE N(R) and N(S) means received (earlier) and sending (now frame sequence numbers, These are module 8 or 128 in standard ‘or extended format frame, respectively, SM five bits ae fora command (or respons) from & transmits Examples of command are reser, disconnect or sta defined ‘mode 1ype: examples of a response area message from the receiver fra disconnect mode aeepted, ame rejected, command ‘ejectod, and for an unnumbered acknowledgement. When five Is transmit for the data, one 0 is stuffed aditionally. This prevents misinterpretation by receiver the data bits as flag bits (0111110). 3.2.5 Serial Data Communication using the SPI, SCI and SI Ports Microcontrollers have internal devices for SPI or SCLor SLas explained below. Each device has separate registers forcontrol, status, serially received data bits and transmitting serial bits, Each device is programmable as described below. The device ean be used in programmed IO modes or in interrupt driven reception and transmission. Synchronous Peripheral interface (SPI) Port Figure 3.3) shows an SPI port signals. Figure 3.3(b) shows SPI port in 68HC11 and 68HC12 microcontroller. It has foll-duplex feature for synchronous ‘communication, There are signals SCLK for serial clock, MOSI and MISO output from and input to master.Embedded Systams [Section 3.1]. Figure 3.3(b) shows programmable features and DDR feature of Port D. An SPI feature is programmable rates for clock bits, and therefore for the serial out of the data bits down to the interval of 5 ps for an 8 MHz crystal at 68HCI. SPI is also programmable for defining the occurrence of negative and positive edges within an interval of bits at serial data our or in, Its also programmable in the open-drain or totem pole output from a master to a slave and for device selection as master or slave. This can be done by a signal to hardware input SS (slave select when 0) pin, In the hardware the slave select pin connects wo ‘I’ at the master SPI device and to “0° at the slave, Defining SPI as slave or master ean also be done by software, Programming a bit at the device control register does this. ‘68HCI2 provides SPI communication device operations at 4 Mbps. SPI device operates up to 2 Mbps in 6sHClI. Serial Connect Interface (SCI) Port Figure 3.3(c) shows an SCI port programmable features and DDR, port bits in 68H1C11/12, SCI isa UART asynchronous mode port. Communication is in fll-duplex mode forthe SCT transmission and receiver. SCT band rates are fixed as prescaling bits. Rate not programmable separately for individual serial in and out lines. A band rate can he selected among 32 possible ones by the three-rate bits and two prescaling bits. The SCI receiver has a wake up feature and is programmable by RWU (Receiver wakeup Unavailable) bit. 1s enabled if RWU (1* ht of SCC2, Serial Communication Control Register 2) is set, and is ‘Butter Ful ome ce, fous ‘ata — Fig. 3.4 (a) Parallel input port, output port, and a bi-directional port for connecting the device (b) The handshaking signals when used by the IO ports Example 3.4 IBM personal computer has a parallel port with a25 pin connector. There are 8 10 pins, 5 input pins for status signals (our active high $3 to $6, one active low ST) from external device po. (for example, printing device port) and 4 output pin for control signals (one aetive high C2 and three active low G0, Ci and C3. The $ pins are ground pins (Pins at D V), The status pins and eontol pins are provided for handshaking between peripheral and computerDevices and Communication Buses for Devices Network Figure 3.4(b) shows the handshaking signals. An external input device to the device port makes a strobe request, STROBE, after itis ready to send the byte and the system IO device sends the acknowledgement, PORT READY when BR, (receiving buffer) is empty. ‘An external output receiving device sends the message ACKNOWLEDGE when the IO device port ends the BUFFER FULL signal. The processor is sent the INTERRUPT REQUEST message when BR, transmitting buffer is empty not full (available for next write) or when the receiving buffer is full (available for next read). ‘This enables the processor to interrupt and retransmit next byte(s) in next cycle or receive the byte(s) from input using the appropriate service routines for output or input from the por, respectively. Example 3.5 Inte! $255 is a programmable peripheral interface (PPI) chip. A PPI device has four addresses, three for the ports and one for the control word. There are three 8-bit ports: pott A, B and C. Port C can also be programmed to function in bit set-reset mode. Each bit of this port can be set to 1 or reset to 0 by an ‘appropriate control word, Alternatively, the ports can be grouped as Group A (Port A and Port C upper four bits) or Group B (Port B and Port C lower four bits). 1. In mode 0 programming for a group, each port group does not use handshaking signals. 2. Mode 2 programming is used for port A as input as well as output. In mode 2 programming for the group A, port A uses handshaking signals, STROBE, PORT READY, BUFFER FULL, ACK and INTERRUPT and port A functions as a bi-directional 1O port. 3. Mode | programming is either for port as input or as output. In mode I programming for the group A or B, port A or B uses only one of the two handshaking signal pai, either (STROBE, PORT READY) or (BUFFER FULL, ACK) plus one INTERRUPT signal ‘The following characteristies are taken into consideration when interfacing a device port. 1. A device port may have muli-byte data input buifers and data output buffets. Suppose there is an coight-byte buffer. Assuming thata device (as in the 80196 microcontroller) can generate three interrupts, ‘one on receiving a byte, one on receiving the fourth byte and one when the buffer is full, then the deadline for servicing these interrupts increases up to eight times compared to the ease when there is 4a single byte register instead of buffer, ‘A port may have a DDR (Data Direction Register) (a8 in the 68HCII microcontroller) This is an advantage since each bit of the port is now programmable. It can be set as input or output. DDR programs the port bits. 3. Port LSTTL-driving capability and port-loading capability are important characteristics. A port may be an OD (open drain) port. Ithas zero driving capability unless the drain connects the positive supply voltage. Ifthe given port has OD gates, an appropriate pull-up resistance or transistor is connected to ‘each port pin to provide the driving capability. The drain or collector connects to the supply voltage 10 provide the pull-up. 4, Ia given port is guasi bé-directional (as in 80196), then the port pins have limited driving eapability, ‘which suffices for a period of one or a few clock cycles and drivesa LSTTL gate for that period. When this device port connects to more than one LSTTL, then an appropriate pull-up eircuit will he required for the port pins. ‘There may be multiple or alternate functionality in the port pins; for example, 80196 input port pins. Each pin of P2 has analternative use as multi-channel analog input facility for 8 analog inputs. Another ‘example is 8051 two ports PO and P2. These port bits also have an alternate function in that they bring ‘out when needed the internal multiplexed buses for the external program and memories whenever theEmbedded Systams intemal memory is insufficient. Each pin of P3 in $051 has multiple uses. These are used during serial ‘communication, timerleounter signals, nterrupt-signals. and RD and WR control signals for extemal memories. 68HCII ports B and C are of & bits each and have alternative uses for the port pins init ‘One of the alternate functions isto bring out the internal address and data buses, respectively 6. A port may have provision for multiplexed output to connect to multiple systems or units, 7. A port may have provision for demultiplexed inputs from multiple systems oF units A parallel device port can have parallel inputs, parallel outputs, bi-directional and quasi-bi-directional TOs, A parallel device port can have handshaking pins. A parallel device port can also have contol pins for ‘control-signal outputs to external circuit and status pins for inputs of status signals to external circuits, 3.3.1 Parallel Port Interfacing with Switches and Keypad A 16 keys keypad has many applications. A mobile smart phone device has 16 keys and four menu: select up, down, left, right keys. Assume that an 10 device has two ports, A and C. The device hasa processing element ‘which functions as a keypad-controlling device (controller). Figure 3.5(a) shows low a set of switches or a keypad of 16 keys and four menu-select keys ean interface to the device. Four bits of an $-bit input port A (Ay-A7) can be used forthe four menu select keys. Assume that the idle state logic state equals 1. The 16 keys can be considered as arranged in four rows and four columns. ‘The other four bits of A (Ay-A,) are inputs from sense lines from four rows. Assume that the idle state logic state is equal fo 1. The four bits of output port C (CC) ate output to sense lines in four columns. ‘The processing element in device activates for polling the output port C ten times each second and sends (Ci-Cy= 0000; aftera wait it reads Dy-D, and A,-A>, The processing element computes the code of the pressed key and generates a status signal when a key’ is found pressed, From the bit pattern found at Ao-A;y the processing element computes 7-bit ASCII code of the pressed key at that instance and can output that code at y-Dg, It also outputs D, = 1 when a specific key is found pressed, else D, = 0, The processing element also processes the bounces when a key is pressed. This takes eare of bouncing effects. The processing element is thus functioning as a keypad controller, as it is keypad specific. Example 3.6 ‘A mobile phone keypad is smart and is called T9 keypad. Nine keys are used to enter not only the numbers but also text of messages. The processing element is programmed as a state machine to compute the ASCII code to be sent. A state machine generates the states. For example, a key marked as number Sis in tate (0, 5) in reset state, which is also its ide state. The key-state undergoes transition to state (1, 5) when iis pressed first time. When itis pressed second time within | ,the ey state becomes (1,j). This state corresponds to character j IF itis pressed third time within Is, the Key-state becomes (1, k). The state of the key changes ina cyclic fashion. (1, 5) —>(1,j) > Uk) — (1, 1) ~ (0,5) 9 (I, The transition of akey state occurs ‘only if tis found pressed within | sof the previous transition and the appropriate action takes place as per the state. The processing element computes the ASCII eode from the read valve of Ay-Ay and key state at an instanee, After processing is over or after Is, the key-state resets 10 (0,5). ‘Two key states simultaneously or separately undergoing transitions can define a transition to another state, For example, when there is transition to (1. j) state after another key state is (1, #) then (1, j) undergoes another transition to (1, j), and when that key state is (0, #) it remains at G.).Devices and Communication Buses for Devices Network 147 iMeniseiect ines Phe tudo erat oy) Databus 2 senso vos, [ 18Keys0.1, Keypad Pho 14,18 infour column lines (ae ay PAS | Rows | (Poling or Scan ines) and four pee 03 | sense ines Processor PG: Pos Pollines 0:3 Ports into @ us, “Adjaconi racks Phase angio] Pa a detector intrtace ocean _lEatarten Pa Bracks 0,1, 23,46 [77] phototransistor outputs wre N PAs [= Index sot detector at 360° PB: Pes | __. toe eps o Poa ace intraco POe |__| iputto stopper mater cols atdonce Poy liver transtors “int © Fig. 3.5 (a) Parallel input port A and a four bit output port C used for interfacing a set of 16 keys in keypad and four menu select keys (b) Parallel input port A connected to an encoder circult which senses the rotated or linear position of a moving shaft and port B connected to 6 LEDS (c) Four bit parallel output port C connected to a stepper motor {A parallel device having @ number of input and ontput bits can he used to find the code of the pressed key in a matrix of keys. A keypad controller has a processing element to compute the code of the pressed key ‘and to generate a status signal when any key is found pressed. A mobile phone keypad controller processes the states of the keys to enable application of same keypad for dialing as well as editing SMS messages. 3.3.2 Parallel Port Interfacing with Encoders Encoder is a device that measures angular or linear position ofa rotating oF moving shal. It has application in rohots and industrial plants, A rotatory-angle encoder has multiple tracks on a rotating disk. Bach track has half ofthe segments transparent and half opaque. A Tinear encoder has a mult-slotted plate. set of n infrared (IR) LED and phototransistor pairs generate n-bit inputs for a port. The encoder connects to parallel port, as shown in Figure 3.5(b).Embedded Systams 3.3.3 Parallel Port Interfacing with Stepper Motor A stepper-motor rotates by one step angle when its four coils are given currents ina specifie sequence and that sequetice is altered. For example, assume that currents at an instance equal + i,0,0, (in four evils X, X°, Y, YY". The motor rotates by one step when the currents change to 0, +i,0,0. The sequences at intervals of T are changed as follows: 1000, 0100, 0010, 0001, 1000, 0100, ... . [The bits in the nibble (set of 4 bits) rotate by right shift.| Here 1 corresponds to + i The motor thus rotates n step angles in interval of (n-T). The sequences are changed to rotate the motor in the opposite direction, as follows: 0001, 00010, 0100, 1000, 0001, 0010, -.. [The bits in the nibble (set of 4 bits) rotate by eft shift] Alternately, the coils are given the currents in the sequence of 1100, 0110, 0011, 1001, 1100, 0110, ..., or 0011, 0110, 1100, 1001, 0011, 0110, .... The motor tates (n/2) steps in interval equals to (n.T/2). Ti the period of lock pulses that drives the motor by change of coll currents to the next sequence. ‘The coils connect to parallel port 4 output pins, as shown in Figure 35(c). Alternatively, a processing clement called stepper-motor deriver ean be used. The driver is given two outputs from the por: elock pulses and a rotating direction bitr. For example, ifr = 1, motor rotates clockwise and if t=0 then motor rotates anti- clockwise. The motor rotates as long as clock pulses are given at the output PC,-PC;. 3.3.4 Parallel Port Interfacing with LCD Controller An LCD controller has a processing element that needs three control signals as inputs and 8 inpuVoutput bits {or parallel set of $10 bits. Bight-bit parallel ouput port B pins PB,-PB, connect LCD controller, as shown in Figure 3.6(a). LCD controller also connects to one bit PC, at an output port for RS (register select) signal Mcroconvoer . eosr an |O Bes _ Display: ntoter pc, aS PC BIW. Font table, CGRAM, (eo ave Peo | Data LoD Display Controler @ int Por E tatoo [_PCe Display 1} PCO BS wi Ei Font table, CGRAM, . = (eb ave coor ey we (ND converter v ‘Touch Screen Display processor NTR Data bus for display, control and status words bea ietoee boca o Fig. 3.6 (a) Eight bit parallel output port B connected to an LCD controller (b) 8-bit parallel output port B and 8-bit parallel input port A connected to a touch screen control circuit‘When RS is reset as 0, PB,-PB, communicates control word to contol register of the LCD controller. When RS is set as 1, PBy-PB, communicates data to the LCD controller. ‘The LCD coniroller also connects to a one bit PC; at output port for R/ W (read/write). PCy is sot t0 | ‘hen status register of LCD controller is rea from PB,-PB,;-PC is reset o 0 when writing into LCD eonuroller the PB,-PB, bis. The processing element generates all signals requted for LCD displays. ‘The LCD controller is sent conirol words and data words for initialization and programming PB, PB, bits, PC, and PC, outpus foreach word to LCD controller. The controller then has to be enabled by sending I at E pin. Itconnect o one bit PC: at output port for E (enable). There is an interval in which the eonteoller may bein Cisabled state. During this interval, it cannot accept instructions or data through the output of control word or | Line" GNT | 0x00 BA in =e =~ | = 5 = | —cacisp > | ssvio| sso | oxo =e, > | se ~ | sem > | + er > Joo vio | oo | cr] sa | mo | +c» Jou] ir|ur| Bist oxo (x0 x) pee Fig. 3.13 64 bytes at standard device independent configuration registers in a PCI device or host A PCI controller must access one device ata time. Thus, all the devices within host computer can share 1, port addresses and memory locations but cannot share the configuration registers. That means that a device ceannot modify other configuration registers but can access other device resources or share the work or assist the other device. If there are reasons for it doing so, a PCI driver can change the default bootup assignments ‘on configuration transactions, A device can initiatize at booting time. This helps in avoiding any address collision. A PCT device on ‘bootup disables its interrupt. Its address space is inaccessible and only the configuration registers space remains accessible. PCI BIOS with the device performs the configuration transactions and then memory and address spaces automatically map to the address space in host computer. PCI parallel bus is popular in distributed embedded devices. PCI and PCIIX buses are used for parallel bus ‘communication and these are independent from the IBM architecture. PCUX is an extension of PCI and supports 64/100 MElz transfers. PCI bus new version support 132/528 MB/s data transfer with synchronous! asynchronous throughputs. 3.11.3 ARM Bus ARM processor interfaces the memory, external DRAM (dynamic RAM controller and on-chip 10 devices, which connect to 32-bit data and 32-bit address line at high speed using AMBA (ARM Main Memory Bus Architecture)-AHB (ARM High Performance Bus). Figure 3.12(b) shows AMBA-AHB and AMBA-APB bridges. The bridges interface the memory and extenal-chip IO devices, which operate at low speed using AMBA-APB. The maximum AHB bps bandwidth is sixteen times the ARM processor clock,Embedded Systams A switch, popularly called the AMBA-APB bridge, switches ARM CPU communication with the AMBA bus to APB bus. The ARM processor-based microcontoller has single data bus in AMBA~AHTB that connects to the bridge, which integrates the bridge onto the same integrated circuit as the processor to reduce the ‘numberof chips required to build a system. This reduces the system cost. The bridge communicates with the ‘memory through an AMBA-AHB, a dedicated sot of wires that transfer data hetween these two systems. A separate APB 0 bus connects the bridge to the I devices. Separate AMBA-ATIB and APB 10 buses are used because the IO system is generally designed for maximum flexibility, to allow as many different 10 5, it means there exists words for options and padding. Padding refers to bits used for filling the remaining part of the available field. For example, the option field may indicate the application to be run by the destined node. An acknowledged flow means that the messages communicate in « point-to-point network mode and that there is an acknowledgment for fist establishing a conneetion. Full duplex means that ata given instance, messages {20 10 and fro from sender to receiver, and that the receiver acknowledges receipt. A request and its response do not form a separate transmission, TCP is virwal-connection oriented. It does not permit multicasting but point-to-point virtual connection.Embedded Systams 3.12.3 User Datagram Protocol (UDP) ‘TCPAP also supports at the transpor layer a simpler protocol than TCP. When a message is connectionless and stateless, then the transport layer protocol in the TCP/IP suite is User Datagram Protocol (UDP). UDP supports the broadeast networking mode. An example is application for communicating header before a data stream, The hheader specifies the bits for source and destination ports, total length of message including header and check sum (optional). During reception, this message to upper layer flows after deleting the header bits from the received transport layer header. Header bits add at the transmitting time in the application or session layer bytes. 3.12.4 Internet Protocol (IP) Al Internet enabled devices communicate using Internet protocol (IP). The transport layer data transmits on the network, divides into the packets at the network layer. Fach packet transmits through a chain of routers on the Internet. A acket is minimum unit of data that transmits on the Internet through routers. Several pacets forming a source can reach a destination using different routes and can have different delays. The packet consists of IP header plus data or IP header plus routing protocol along with the routing messages, The packet has « maximum of 2! bytes (2! words, | word = 32 bits = 4 bytes), Network routing is as per standard IPv4 (version 4) or IPv6 (version 6). 1Pv6 is a broadband protocol ‘Table 3.11 lists the fields in IPv4 protocol header. Table 3.11 Various fields at IPv4 header for routing the packets through routers to destination node Ftd atthe 1 header Explanation Version IP version bits are 0100 for IPv4 (presently in wide use) and O110 for IPv6 (Pag IP ‘ext genation for broadband Inert) Precedance Precedence type i between 8° to 10" bit Bits 111 specifies highest precedence. For example, for steaming aio or video, 000 specifies common dat. Service Service type is between 11810 15™ it (QoS (Quality of Service) Bits are for QoS (Quality of Service) specification in terms of security, speed, delays and cost desited or must be achioved. Fragment 1D Each message may have many packets fragmented through the routers. Each fragment ‘must thus provide a unigue ID for identification for reassembly atthe receiver end, Flags Flags indicate whether present fragment is last one, whether fragments are permitted and whether more fragments wil follow. Let q = Number of header words (1 word = 32-bit) Flag bit! indicates whether more fragments ofthe packet will succeed this fragment. Flag bit 2idemifies tas a test fragment or not. Flag bit checks whether the fragmentation is permited oF not. ‘Header checksum checks errors in header transmission. ‘Time tlie indicates numberof retcansmission hops permite in ease of failed delivery. Protocol type ‘Type indicates whether the packet i transmitting a UDP byte stream or a TCP stream {rom transport layer. The important routing protocols that encapsulate after the IP header in an TP packet are (Comd)Devices and Communication Buses for Devices Network Field atthe IP header Explanation IGMP (Intemet Group Management Protocol). IGMP is a protocol to manage dats transmission between select host groups, Several host join a group. Group mlticasts ‘use routers that uses the IGMP. ICMP CInernet Control Management ProtocoD. ICMP isa protocol to contol routing between networked hosts ICMP data byte stream is inside an IP packet (datagram). Is format i as follows. First, 20 bytes minimum are the IP hear. Next follows the fields of I-hyte each for Type and Code, successively. Next two bytes are for Checksum. Then follows the ICMP ‘messages the format and length of which is variable, Interior routing protocols, for example, the RIP (Routing Information Protoeo!) and OSPF (Open Shortest Path Firs) protocol Inter-Domain (exterior routing) protocols, for example, EGP (Exterior Gateway Protocol), BOP (Border Gateway Protocol) and GGP (Gateway to Gateway Protocol, Header length “The IP header length (data offiet) p <2 q Here 4 5. equals the numberof woes (data-ffet in the header and is elle the data offset [Number of word after which data bits start inthe steam.) Source and Destination IP Source and destination IP adsesses Iq 5, there exist words for options, ‘addresses options and padding. Padding refer obits that ae used for filing the remaining pat ofthe available field. For example, option 4 will mean put time slamp at all the stoppages of ‘the packet during transit to destination through routers. Time stamping enables packet delay measurements to caleulate Network Performance Quality 3.12.5 Ethernet ‘The inventor of Ethernet LAN is Robert Metcalfe. At present, about one third of the LANs in the world are the Ethernet LANS, and in each frame, there isa header like in a packet. In Ethernet LAN standard is IEEE 802.2 (ISO 8802.2). It is a protocol for local network of computers, workstation and devices. LAN is used for shating local computers, systems and local resources such as printers, hard disk space, software and data, Table 3.12 gives the features of the Ehernet LAN devices. ata for transmission fragments into the frames. Each frame has a header, Firstly, the header has eight bytes, which defines a preamble. The preamble indicates the start ofa frame and is used for synchronization. Then the header has six bytes of destination address. Six bytes of source address then follows the destination address, Then there are six bytes. These are for the type field. These are meaningful only for the higher network layers and the length definition. The minimum 72 bytes and maximum 1500 bytes of data follow the length definition. Lastly, there are 4 bytes for CRC cheek for the frame sequence check. 3.13 “WIRELESS AND MOBILE SYSTEM PROTOCOLS Figures 3.15(a), (b) and (c) show a handheld device or computer system connected (o other handheld devices for computer through IrDA, Bluetooth and ZigBee wireless protocols, respectively. Sections 3.13.1 10 3.134 describe the IrDA, Bluetooth, WLAN (wireless LAN) 802.11 and ZigBee protocols.Embedded Systams Table 3.12 Ethernet LAN features Feature Ethernet LAN ‘Topology and transmission mode Bus Speed LO Mbps, 100 Mbps (unshielded and shielded wires) and 4 Gps (in wistod Pair wiring mode) Broadeast Medium Passive. Wired connections-based. Frame format like the IEEE 8023. SNMP (Simple Network Yes “Management Protoco) System (Open (therefore allows equipment of different specifications) Operation Each one connocted to a common communication channel in the network. Thlistens and ithe ehannel sie then transmits. I not idl, waits and tries again. Mult acess is lke in a packet switched network Contr Passive, connection-based ‘Adaress Resolution Protocol (ARP) Yes, There is a mesa access control (MAC) aude for transmiting and for resolving 32-bits Intemct protocol forwarding frames onthe same LAN, We ean also se malticast addressing audesses with the 48-bit destination 10 send frames to all or few select types of Ethemet devices. host media addres, ‘Connectivity to Internet and Intranet Yes, Outside a LAN the Intemet Protocol addresses are sent. 3.13.1 Infrared Data Association (IrDA) Infrared (IR) is electromagnetic radiation of wavelength greater than visible red light. An infrared source consists of a gallium-arsenic-phosphorus junction-based diode. An infrared receiver consists of a gallium~ arsenic—phosphorus junction-hased phototransistor, which conducts electric current when the IR beam falls ‘on it and does not conduet when IR does not fall on it. The eollector or drain has voltage close to 0 V when it ‘conducts and is close to supply voltage when it does not conduct. InDA (infrared Data Association) recommends a protocol suite as standard, It supports data transfer rates ‘of up tod Maps, Itsupports bi-directional serial communication over viewing angle between 15° and distance of nearly 1m, AtS m, the IR transfer data can be up to data transfer rates of 75 kbps. There should be no obstructions or wall in between the source and receiver. Figure 3.15(a) shows a handheld device connected to other computer through using IDA protocol. Protocol- processing hardware device and the protocol sofiware embeds in the system, which support line of sight communication using infrared I:DA supports $ levels of communication, Level | is minimum required communication. Level 2 is access- hhased communication. Level 3 is index-based communication, Level 4 is synehronized communication. ‘Synchronization software, for example, ActiveSync or HotSync is used. Level 5 is SyncML (synchronization ‘markup language)-based communication. A SyneML protocol is used for device management and synchronization with server and client devices, which are connected by IrDA. [EDA is used in mobile phones, digital cameras, keyboard, mouse, printers to communicate to laptop computer and for data and pictures download and synchronization, IrDA is also used for control TY, air- conditioning, LCD projector, VCD devices from a distance. IrDA supports several protacols at three layers. Lower layer is physical layer 1.0 or 1.1. Tt supports data transferrates of 9.6 kbps t 115.2 kbps and 115.2 kbps to4 Mbps in HDA physical layer 1,Oand 1.1, respectively.Devices and Communication Buses for Devices Network ogee] _ | eer enpedied onion Vonriwrace peal aen @ Bivetooth protocol : basal Computer in po oo ae foe ena (OCT com ron ei ee ee ere | 1 Boao pubes Blase pao le aa Ta paps eae ese ies Te Sn Ta oar Tybee pomen ere ee @ Fig. 3.15 (a), (b) and (c) A handheld device connected to other handheld devices or computer through IrDA, Bluetooth and ZigBee wireless protocols, respectively Intermediate layer is data-link layer. At data Tink layer, it specifies IFLMP (IR link management protocol) "upper sublayer and IrLAP (IR link access protocol) lower sublayer, An IrLAP is HDLC synchronous communication (Section 3.2.4). ‘An IrDA upper layer protocol is Tiny TP (transport protocol). Another upper layer protocol is IKLMIAS (IR, Link Management Information Access Service Protocol). transport layer protocol during transmission specifies ‘ways of flow control, segmentation of data and packetization. During reception, it assembles the segments and packets. The upper layer protocol forthe session layer is IrLAN, IrBus, IMC, IrTran, ItOBEX (Object Exchange) ‘and standard serial port emulator protocol COMM (IR communication). IrBus provides serial bus access to ‘game ports, joysticks, mice and keyboard. Application layer protocol is for security and application and as specified by the IrDA. For example, IEDA Alliance Syne protocol is used to synchronize mobile devices personal information manager (PIM) data. It supports Object Push (PIM) or Binary File Transfer. ‘Windows and other operating systems support IDA protocol-hased communication devices, An infrared ‘monitor in Windows monitors the IR port of the IR device, It detects a nearby IR source. It controls, detects and selects the IR communication activity. An IR device on command sets up connection using IrDA, and starts the IR communication. When IR communication is inactive, the monitor enables plug and play (unless disabled). [EDA protocol overhead is between 2% to 50% of Bluetooth device overhead. The communication setup latency is just few milliseconds. The requirement of line of sight and unobstructed communication isthe li 3.13.2 Bluetooth Bluetooth hardware is connected to embedded system buses and Bluetooth software embeds in the system to support WPAN using Bluetooth wireless protocol. Figure 3.15(b) shows a handheld device connected toEmbedded Systams other computers through wireless protocol using Bluetooth, A large number of CD players and mobile devices are Bluetooth-enabled. Bluetooth is also used for handsfree listening of Bluetooth-enabled iPod or CD music player or mobile phone by using Bluetooth-enabled era buds. Bluetooth isan IEEF standart 802.15.1 protocol. The physical layer radio communicates at carrer frequencies in 2.4 GHz band with FHSS (frequency hopping spread spectrum). Hopping interval is 625 is and number of hopped frequencies are 79, Data transfer is between two devices oF between a device and multiple devices. It supports range up 10 10 m low power and up to 100 m high power. Range depends on radio interface at physical layer. Bluetooth 1.x data transfer rate supported is 1 Mbps. Bluetooth 2.0 has enhanced maximum {data rate of 3.0 Mbps over 100 m. Bluetooth protocol supports automatic self-discovery and self-organization ‘of network in number of devices. Bluetooth device self discovers nearby devices (<1) m) and they synchronize and form a WPAN (wireless personal area network). Bluetooth protocol supports power control so that the ‘devices communicate at minimum required power level. This prevents drowning of signals by superimpositions ‘oF high power signals with lower level signals ‘The physical layer has three sublayers: radio, baseband and Tink manager or host controller interface. ‘There are two types of links: best effort traffic links and real-time voice traffic links. The real-time traffic uses reserved bandwidth. A packet is of about 350 bytes. The link manager sublayer manages the master and slave link. I specifies data encryption and device authentication handling, and formation of device puirs for Bluetooth ‘communication. It gives specifications for state transmission-mode, supervision, power level monitoring, synchronization, and exchange of capability, packet flow latency, peak datarate, average data rate and maximum burst size parameters from lower and higher layers ‘The Host Controller Interface (HCD interface is a hardware abstraction sublayer. It is used in place of the link manager sublayer. It provides for emulation of serial port, for example, 3-wire UART emulation, A Bluetooth device can thus interface to the COM port of a computer. Its communication lateney is 3s. It has large protocol stack ovethead of 250 kB. Provision of encrypted secure communication, self-discovery and self-organization and radio-based communication between tiny ‘antennae are three main features of Bluetooth. 3.13.3 802.11 Wireless LAN uses IEEE standards 802.11 to 802.11g. Data transfer rates are | ancl 2 Mbps. The 802.11 is called wireles fidelity (WIFI). 802.11b support data rates of 5.5 Mbps by mapping 4 bits and 11 Mbps mapping 8 bits simultancously during modulation, A given set of the LAN-station access-points network together and the set is called extended service set (ESS). itis a backbone distribution system. A backbone set may network through the Internet. ESS supports fixed infrastructure network. ‘There are two types of wireless service sets 1. One service set has one wireless station, which communicates to an access point, also called a hotspot. ‘The service set i called basic service set (BSS). WLAN supports ad-hoc network, which, as and when anodes come nearby in range, it forms the network. BSS supports ad-hoe network which, when nodes ‘come nearby with in range of the access point, forms the network through ESS. A node can move from one BSS t© another. ‘The other service set has several stations. Its called independent basic service set (IBSS). It has no access point. It does not connect to the distribution system. It may have multiple stations, which also cannot communicate among themselves. IBSS supports ad-hoc network. 802.11 provides specifications for physical layer and data link layers, ‘The data link layer specifies « MAC layer. The MAC layer uses carrier sense multiple aceess and collision avoidance (CSMA/CA) protocol. A station listening to the presence of the carrier during a time interval isDevices and Communication Buses for Devices Network called distributed inter-frame spacing (DIFS) interval. Irthe carrier is not sensed (detected) during DIFS, then the station backs off for a random time interval to avoid collision and retcies after that interval. A receiver always acknowledges within a short interframe spacing (SIFS). Acknowledgment is made after successful CRC (cyclic redundancy check). If there is no acknowledgement within SIPS, then the transmitter retransmits and upto 7 retransmission attempts are made ‘There is a packet called request to send (RTS), whic is first sent, Ifthe other end responses by the packet call elear to send (CTS), then the data is transmitted. MAC layer specifies power management, handover and registration of roaming mobile node within the backhone network at a new BSS within the ESS. ‘There are three communication methods at the physical layer. WLAN can use FHSS or DSSS or Infrared 250 ns pulses. The physical layer has two sublayers. 802.11 has three sublayers: one is Physical Medium Dependent (PMD) protocol which specifies the modulation and coding methods; the second is the Physical Layer Convergence Protocol (PLCP), which specifies the header and payload for transmission. It specifies the sensing of the carrier at receiver and how packet formation takes place at the transmitter and packets assemble atthe receiver, It specifies ways to converge MAC (Medium Access Control) to PMD at transmitter and separate MAC (Medium Aecess Control) from PMD at the receiver. An additional sublayer in 802.1 Ib specifies Complementary Code Keying (CCR). 3.13.4 ZigBee ZigBee is an IEEE standard 802.15.4 protocol. The physical layer radio operates at 2.4 GHz band carrier frequencies with DSSS (direct sequence spread spectrum). It supports a range up to 70 m. Data transfer rate supported is 250 kbps. It supports sixteen channels. Figure 3.15(c) shows a handheld device connected to other devices through wireless protocol using ZigBee. ‘The ZigBee nework is self-organizing and supports peer-to-peer and mesh networks. Sell-organizing ‘means that it detects nearby ZigBee devices and establishes communication and network, Peer-to-peer network ‘means the each node at network functions as a requesting device as well as a responding device. Mesh network means that each network functions as x mesh, A node can connect to another directly or through ‘mutually interconnected intermediate nodes, Data transfer is between twa devices in peer-to-peer of between device and multiple devices in the mesh network. ZigBee protocol supports large number of sensors, lighting devices, air conditioning, industrial controller and other devices for home and office automation and their remote control and formation of WPAN (wireless personal area network). ZigBee network has a ZigBee router, end devices and coordinator. ZigBee router transfers packets from « neighboring source to a nearby node in the path to destination. The coordinator connects one ZigBee network with another, or connects to WLAN ot cellular network. ZigBee end devices are transceivers of data, Its communication latency is 30 ms, Protocol stack overhead is 28 KB. ‘Summary ‘Important poins dealt with in this chapter are a follows. ‘+ 10 ports 10 devices and timing devices are essential in any system. ‘+ An embedded system connects tothe devices like keypad, touchscreen, multiline display unit printer or modem. ‘or motors through ports. During a read oF write operation, the processor accesses that adress in a memory- _mpped IO, a if it accesses a memory adress, A decoder takes the system memory or 1O address us signals as the input and generates port or device select signal, CS and selects the port or device.Embedded Systams ‘+ There are two types of 10 ports and devices, serial and parle. Serial communication sin synchronous (master slave) mode or asynchronous mode + Adve connects and asesses from and to the system-proessor though ether a parallel or serial IO por. A device port may be fall duplex or hal-duplex + A device or porthas an assigned por addres using whch the procesor acess the devew port contol ester cr stats rgistr or data. device can use the handshaking signals before storing the bisa the pot buffer before accepting the its from the port ber. + Serial communication bis are receive atthe receiver aeconling othe clock phases ofthe transite Synerono serial communication bits from the master carry the clock information also to slave. Asynehronous sri counmunication bits froma device donot cary theeock information w recive. Receiver clock pases independent forthe tranomite lock However, the rcsver clock adjust its phase according t the received bis, for example, the sta i ‘+ HDLC protocol fora synchronous communication data ink network between the devices +A popula asynchronous serial communication mode is UAREE. Bits are received a the receiver independent of tn lock phases atthe UART (asynchronous sera input and ouput por) transmit. UART in mirocontlers usually sends and receives a byte in 10-bit fomat oF HI-bit format ‘+ Another popular asynchronous serial communication mode is RS232C, which is based on UART and is used to connect the dita communication equipment such as modem with daa terminal equipment such as compute + UART and RS232C can also use handshaking signal DCD and a pair of handshaking signals, (DSR, DTR) and (TS, CTS). ‘+ Other popular serial port inthe devices are SP, SCI, Stand SDIO. + Parallel communication i without or with handshaking signals. The numberof embedded systems perallel por or device imeracest switches, keypad, encoders, motors, LCD conolls ad touchscreen Special purpose pots exstat miereontole fr their interfacing. On-chip peripheral devies internally interface withthe processor in mierocontoler ‘+ A timers essentially a counter geting the count inputs (ticks) at regular ime intervals. Timing and counting deviees havea large number of uses ina system. There hao be at east one hardware timer ina sytem, Software timer sa vital ming device. A pogzan can use numberof softwae imers in a syste + ote programmable imingdevies with a processor cicrocontollr unit can be used for many applications and to generate interop or the ticks for software timer. + Watchdog timer is special mer which timeouts and generates inteupts incase certain specified event doesnot occur during the preset interval. The watchdog timer is used o take cre of a system suck ina certain section of ‘tsk for an unnecessarily long time de fo some enor o harware fie. + Realtime clock generates ticks and interrupts the system a regular interval + The use ofbuses simplifies he interacing o mukiple devices. Several devices canbe placed ona common serial ‘us. Popular sei uses are FC, CAN, USB and FireWire. Each devie hasan assigned device des ot sl of aMdresacs Using the device adkeses othe receiver or sine, a muster-processor accesses the remote deviees + FChusis usa otween maple ICs forimer Integrated Circuit communication. A device, which nts the comm 'mcation and sends the lock poles, isthe master at aninstanc, A master ean commonicate to maxima 127 saves. ‘The CAN bus is popularly used in centrally controlled networkin automobile electrnies. + USB (Vaiversal Serial Bus) is standard fr serial bus communication between th sjsem and devices lik scam, keyboard, printer and mouse. There i roo-hub and all nods havea toe-ke stuctre + Several devices can be placed on common pale bus. Popular parallel buses ae ISA, PCI and ARM buses + Vay shot distance devices intrconnest oa PC or embeded system iain bus though te ISA or PCL or ARM ‘us ean be used. These buses connect 1 main memory bus through abridge (wit). ‘+ Ifemet-nabled embeded systems netvork though protocolsina TCPAP protocol suite, Popularly wsd protocols aac HTTP, TCP, UDP IP and Ethernet. + Wireless communication is use for networking handheld devices over wireless personal area netwovk. {+ Embedded systems can interconnect and network without wires using IDA, Bluetooth, 8021 or ZigBee protocol compatible hardware and soRware support.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.a You have either reached 2 page thts unevalale fer vowing or reached your ievina tit for his book.(BEE 1394) isa (SCH Port 140 (SFRS) 63 (Sh Port 140 (USB) isabus 163 STPChecksumi6 582 *OSMboxAccept 438 *OSMboxCreale 437 *OSMboxPend 438 sO8MemCreate 424, 425 *OSMemGet 424,25 *OSQRush 46,447 *OsQPend 446, 447 *QMspPoiner 447 cn 16550138, 226, 16cI6 8 16C76, 1687632 6Es76 8 6sticosios 4 6SHCIT 12, 145, 157, 201, 205, 207, 217, 223, 224 OSHCH 74,75,77, 117 6SHCII RTC 227 GBHCLIxx 8 68HICI 14x, HCI2xs, HCIoxx 32 esHCI2 12,117 6sHcle LIT 6SHCxx 32 8.103.455 80196 117, 145 802.11 WLAN. 151 S02.1a to 802178 son IIb 178 8051.63, 64, 65,66, 67. 69, 70,71, 72,72, 7, 204, 205, 206, 209, 217 8051 Wo 14S 8051, SUSIMX 32 165, S0SIMX 517 Soest 4 80886 7,32, 89,200, 201, 202, 205, 209, 211, 226, 39 8250 138 8255145, 8255 pons 69 A aciteular queue 328 CMOS 10 ACODEC 9 ‘critical section 214 Uesign process 37 fee running counter 227 function 31L plobel variable 258 Abash table 247 keyboard 79 Alinker 625 alist file that 63 A lis is adata structure 249 ‘locator program = 111 ‘mobilehone 385,375, 380 robile phone device 377 APCLdsiver 168 ‘pipeline of 87 Queue for 446 realtime clock | 18 serial 160 serial bus 160 serial TO bus 159) software timer 18 Atak 309 ausk 310 ‘A timer cum counting device 153) touch screen 380) A watchdog timer 158 a wireless protocol 160) ‘D217 AG-AT 75 abstract class 593 class 297 [Abstraction 37,38 ACC S74, $75, 576, 577, S78, 579, 580, S81, 582, 583, 584, 585, 86 tasks 585 Accelerator 9, 35, ‘Accept 338 function 491 ‘Active class 297 ‘object 297 Activesyne 176 ACVM 43, 193,274, 275 276, 277, 278, 283, 284, 308, 312,315, 321, 373,374, 388,512, 513, 514, 515, 516,518, 519, 519,520, ACVM Hardware Architecture S17 ADO, ADI 75 ADO-AD7 68 adaptive control 580, 582 ‘eniise control $79 ADC 15, 16, 48, 82, 88 531, $32, 533, 536, 637 ADC, DAC 49 ‘Add number 607 ‘Adress Bus 72, 73, 84 resolution 627 ADFG 278 ADV 73 AHB 90 Airbag $78 alarm signals 576Index: ALE 68,73 Alignment 101 Allocation 378, 424 ALU. 7, 18,34, 84, 85 AMBA "90, 169 ‘AB 169 APB 166, 169, 170, analog to digital conversions 305 ‘anonymous object 296, 298 ‘AOU 84,87 APEG 292, 293 aperiodic 401 tasks 385, APIs 267, 353, 489, applet 268. application 28, 2 ‘Specific Instuetion-Set Processor as 6 Specific System Processor (ASSP) 6 architecture 40, 63, arguments 256 ‘Arithmetic and Logieal Unit (ALU) 5 instructions 65 Avithmotical 91 ‘ARM. 8, 32,36, 89, 99,93, 101 102, 114, 208, 410, 623, 636, 641 ARM family Cortex-M3, Atmel 9 ARM, 68HCxx, 80x86 7 ARMIL 93 ‘ARM7 91, 202, 208, 200, 212,213, 217 ARMIN 92 array 245,246 (one dimensional vector) 250 ARS 84, 85 AS 73 as mutex 426 object-oriented 40 per user requirements 37 ASCIL 373,608, 639 ASCH code 146 ASCII codes 149 ASIC 31 ASICS 30,31, 652 ASIP 33,49, 31, 573, 635, 636 Assembler 20,21, 25,27, 621 622,624 assembly language 21,25 Language Programming 235 language using 20 Assert 650 ASSP. 3,37 faxynchronous 365, 366, 381 10 366 serial 130 Serial input 132 Serial Output 132 ‘atomic 327 ‘operation 257, 326 anributes 276 ‘Automatic 119, Chocolate Vending Machine (ACVM) 43, 299, Automobile $74 Ranking 28 Baud of Bit Rate Contwol 154 per second 132 fate 137, 138, 140, rates 14 BCC 494, 583, 584, 386 beled 266 before the actual 108 behaviour 276 BG 80 BGO 82 BG) 81 Big Endian 102 binary 315 semaphore! 463 Bind funetion 491 Bit Manipulation 65 rate meter 655 Transfer 91 BIU 84,85 Blind Counting Synchronization 152 block 229 river 223 file system 365 blocking 420 Bluciooth 48, 137, 143, 195, 177, 178, 569, 590, $72, 573, 574,576 ‘device 49 Bootps 171 bottom-to-op design ifit 38 “up-design approach 256 ‘pounded butter 325, 326 BR 81,82 Branch target cache 86 BSD 363, BT Cacho 84 buffers 321, 391 Buming 632 bus 14,15 ‘Aabitration 80,81, 82 controller 81 rmastor 80, 82 request. 81 Requests 80 width 84 busy wait loop 396 Button 488, 493 byte codes. 266 ‘Manipulation 65 order 641 € © 237, 238, 239, 242, 250, 252, 256,264 Tanguage program 22 ores 236 program 23 cree 268 Cee 263, 264, 383 Cache 13 Disable Instructions 42 caches 12, 103 Call 190, 191, 193 called wireless 178 camera 49, 337 CAN 161,164 Bus 162 isa 163 capture register 153 card $96, 397 catch 195 CCD 48, 49, 194, 531, 532, 533, 535, 567 Preprocessor 534 ceppsp 48. CCDP. 535, ecpsP. 49 eDe 267DRG. 280 C-Bativor 624 cellular 479 Challenges 41 char 229, driver 223 Charaeteristes 4 charge 47 pump 10 Pump Circuit 45 Checksum 32, 174, 548 circuit glitches 384 circular 639) queue 242, 245 CISC 62, 88,98 class 263, 265, 266,268, 276, 295, 296, 297, $16, 539, ‘570,571, 572, 608 iagram 298, 209, 515, 516, ‘533, 534, 538, 539, 570,580 582, 593, 608 inheriinee 622 Task $40, 609 clases 262, 267, 517, 570 Classification $2 classify embedded 52 CLDC 267, 268 clock 10, 84 frequency 6,7 ‘oscillator eireuit 10 Rate Reduction 1 lose 340, 364, 365, 554 close () 343 Close socket 492 MB 579 eMOss 36 co 640 code 19 segment rogistr (CS) 11, 85, CODEC 10, 305, 532,535, 634 codesigning 6M CodsTest 654 CCollabonstion diagram 208 collision mitigation brake 575 COM. 48, 49, 136, 138, 221 COM port 137 com 78 COM? 77, 226 command 605, 610 Command key 604, 611, 612 ‘compare register 152 compares 637 Compile 651 compiler 27, 621, 622 ccomponentization 480 Computer Networking 28 ‘computers and mobile 479 Concurrent processes 275 processing 23 processing program 276 concurrently processing 289 condition 282 Conditional statements 254 Conditions 251 Conductor class diagram 571 Configuration files 239 Conformance 494 connect 340 function 492 cconnectionless 342 ‘connection-oriented protocol 342 Consiinis 5 contact-less 593 CONTEXT 211 context 212, 305, 306, 310, 311, 312, 313,314, 315, 355, 372, 388, 390, 391, 384, 395, 386, 638, at 213, switch 244, 305,310, 311,327, 300,396 switching 211, 212, 213, 309, 355,381 Saving 217 Control 489) ‘Area Newwork 576 Bus 72,73, 8 register "78, 640 controller 80,82, 83, 143 and on 169 Controls 492 Cooperative schedulers 392 scheduling 385, 386 Cored 88 CORTEX-M3 32 cos. 357 ‘counting deviee 152 semaphore 321, 325, 331, 426, 434,463, 467 covenige "654 Index crcl 167 PSR 212,213, CPU 7,34, 307, 310 Toad 642 ‘machine eyeles. 11 register 305, 3906, 311, 313 ERC 163, 164, 175,179 CRE32_ 548, 562 Create 338 critical 330, 396 section 214, 318, 328, 329, 395, 398, 397, 465, 467, 487, 495 cross 650 compiler 649 ‘Assembler 27, 621, 624, 625 Compiler 621, 625 cs 88 CSW 248, 249 Cursor key 604, 605,610, 612 cyclic onler in an 258, scheduling 386 D DOD? 68, 75, DAC 15,16, 48, 82,83 daisy chaining 80,81 DAS $76,583 Data 241 ‘Acquisition Systems 118, being 101 butter 640) Bus 72,73, 88 cache $4, 86 Direction Register 145 encapsulation 262, 375 flow 275 Flow Graph (SDFG) 281 memory 68,74 Register 78 structure 243,244, 246,247, 288 Transfer 65, 91 Transfer Instructions 64 type declarations 236 types 266, 641 Datagram 342, S41 DCE 137 DCT 335 aver) 33 DCTs 49, 533,535Index: DDRO ML eadline 215, 262, 392, 216 Deadlock 329, 330 eaallocation 372, 424 Debug 651 ebuager 627, 650, 659 Sebugzing 595, 622, 652 tools 26,40 Declare 525 Decoder 69) Decryption engine 9 Definition 3 Delay ziters 643 eloting 245 Seletion 246 deletions 247 demultiplexers 14,53, 74 De-Registering 498 DES 395 design 5 Metres 38, 39, 513,532, 570, S78, $94,607 Process 37, 38,41 stages 40 evioe 370, 408, 489 address 78 addresses 77, 631 buffer management 362 contr 639 data 639 ‘river 24,25, 199,200, 2 224, 285, 256, 400, 498, driver ISR 221, 363, rivers 211, 222, 220, 223, 22 228, 354, 372, 408, 480, 497 Management 24, 354, 361,363 manager 25, 364 programmer 21, 627, 630, 632, 633, 631 software optimization 410 status 639 butter addresses 306 river 195, 382 river modules 496 rivers 195 sensitive 640 DFG 277, 278, 279,282 DFGs 275,280 DHCP 171 Dhnystone for 6, 642 bi 207 digital 194 camara 9,48, 94, 12 532, 533, S44, 536, 631 camera hardware architecture $35 (Camera Software Architecture Signal Processor (DSP) 32, 96 Direet memory 50 pemory aveess 73 ‘memory access controller SI director robot 389 Disable the interrupss 328 disabling 329 discrete cosine transformation cn 9 dispatch table 306 display co-processor 533, DISR 370 dissembler 624 distributed embedded systems 160 division by zero 210 DLL ast DLLs 480 DMA. 99, 218, 327 chip 8237167 controller 218 MAC 219 DPCS 260 DRAM 109 DRAM, EDO RAM, SDRAM 109 driver "639 DSP_ 32, 33,35, 50, 93,96, 104, 635, 626, 637, DSPs 36,95, 577 DSSS_ 152,179 Dal Core 33, 88 ore processor 35, 289 dynamic binding 360) ata memory 360 ‘memory S01 programming model 400 scheduling 290 ESMS 600,612 EQPROM. 12 279,531, each frame 175 ECB. 427, 428, 420, 437, 438, 439, 6, 447, 48, 463, 467,469, 470 ECG. 118 EDF 385,398 Eat 651 editing 622 Editor 25, 621, 622 Euittestdebug 620 EDN 612 EDO RAM 108 EEPROM 13,110, $97 EL 207 EISA 168 Embedded hardware 45 Java 267 processor 5,4 Soltware 19 system 3.4.5 system hardware 5 systems 28 ception 381, 394 empiive scheduler 375, 496 emulator 620,623, 650, 656, 657. 658 encoder 147 Eneryption engine 9 Engineering cost 39 software 26 EPROM 106, 107, 633,634 Ethernet 175, 190 Ethernet adapter, GPS 143 event 284, 368,61 joni 356 Control Blocks */ 440 fag-group 412 Functions 358, 487 OssemCreate 427 register 359 controled Program Flow 282 Flag 359 events 368, 494, $13,539, $70, 606 Examples of 27 exception 192, 195, 197, 202, 211, 266 bbandlee 203 handling signals 486 [Exceptional handler 195 handling 264exception-handling functions 460 exceptions 201, 204, 333 execution time 401 expecting 455 external interupt 72 interrupt pins 63 Memory 68 F Fabrication key 46 fast 369 Td 534 FDSET 473 FHSS. 132, 178 fields 276 FIFO. 214,215, 244,245, 246, 247, 260, 321,445, 456, 467, 470, 4472, 01, $02, 503, 508 method "412 FIFOs 504 file 24, 22,223, 483 seseriptor, Fd 306, ‘management 354 System 47, 364, 365, 496, 95 Finite impulse response FIQs 209 FIR 298,279, 280 FireWire 165 Firs-level interrupt service routine 199 Fixed priority scheduler $02 time scheduling 399) flash 12, 13,20, 120,121, 63 631, 632 for 45 memory 19,451,107, 194.625 FLISR 198, 369) Floating Point Processing Units. 7 FLPU 84, 85,99 FM 135 for 237,282 JPEG compression 49 RAM and ROM. 101 Soc 90 super harvard architecture single 95 the priority inversion 330 fork (497 FFormalization of system design 42 a foundation classes are GUIS 264 FPGA 31, 74,75 FPGAs 634 fee running counter 153, 159 frequencies 151 FRS 84, 86,99 FSM 283, 285, 286, 288, 296 State Table 285 FIP 171 Full Duplex 131, 133, 140, 142 function 239, 240, 256, 257, 258, 259, 260, 261, 262, 294, 312, 313,314 function argument 257 Calls 258 Pointers 259 queues Queues 260, 261 functions 258, 241, 263, $31 call 257 G GAL 74,75 same 479 General Purpose Microprocessor 35, Purpose Processor 6, 86 tlobal variables 237 gluc-ireuit 74 Goal 351 of testing 42 cpr 7 GPS 576 Grophie Accelerator 10 Graphies processor 9 GUL 254, 408, 497, GUI notification? 573 GUIs 305, 410, 696, 624 H hale 142 Duplex 131, 133, 140 Handle 482,483, 484,485,486, 493, 496 handshaking 145 Hand-shaking signal 144, 225 Hard RealTime 380 realtime systems 381 3,531 Index hardware 5,313, 518, S41 Architecture 534 components 52 imeral timer 156 interrupt 192, 200,201 scheduling 290 software tradeoff 634 Harvard 629 ‘Architecture 89, 103 memory 630 hash able 242,248, HDLC 138 header 237 UDP 552 Tiles 238 heap 482 Deavyweight 307 Heuristic 400 ex 627 Pile Intel 632 File S-Recoed 632 Hierarchical RTOS 378 High definition 33 level language 22 performance 106 performance processors 84 processor performance 104 ‘Speed Serial 569 level Language Programming 236, 237 level program | 237 host 623, 624, 625, 649, 650 HoxSyne 176) SDFGs 293 HSDPA 96 HSTL 150 HTTP 171,172,173 Hutfman 534 Hugtiman coding, 533,535 Ho 639 Device 629, 639 instructions. 641 ‘management 354 stream 264 Subsystems 365 be 162 12C bus 66, 161, 162Index: IBM 136, 137, 138, 144 integprocess 354 498, 437,439, 445, 449, 455, ICE 620, 626, 627, 689, 652, 656 Communication 330, 463 4459, 462, 470, 486, 494,50, IDE 408, 620, 622, 623, 624 ‘communication model 254,275 522. 636 identity 276 inwrrupt 18, 207 functions 339 IE 216 Mags 208 IPCs 23, 30, 290, 326, 328, 356, IEE 582 Handler 18 2371, 372,440, 469, 472, 484, TEM 90 latencies 215, 381, 400, 401 495, S41, $43, 544, 584,596 if else, elseif 237 latency 213,214 IPHleaderSelPkt S61 image pixels 34 mask 212 TPPKL 539, $43,546 in DSP, TMS320Co4x DSP 98 mechanism 198 IppkrStream $45, linker 627 Pending Register 208 Wed 174 Unix 352 Request 145 IPNerttar 559 Cirevit-Emulators $3 service 496 Ig 4 include 238 Serviee Deadline 215 IR souree 151 “pretllandlerse 238 Service Functions 461 COMM. 177 jective 237 sorvice routine 18, 240,261,280 IrDA. 51, 175, 196,179 Infinite 252, 254, 304 Service Threads 373 adapter 143 Loop 251, 373, Servicing (Handling) protocol 152 inheritance 276,277, 278 Mechanism 203 IRQ_ 209 Input captures 637 signal 145 Is 361 InpuvOutput (VO) Subsystem 366 source 200, 208, 209, ISA 168 insering 248, vector 203 ISA Bus 167 insertion 246, 247 ‘Vector Table 205 Isossynchronous 134 Inst. Cache 84 handling functions 461 ISR. 71, 192, 193, 194, 195, 197, Instance field 265 inerrupts 4 198, 199, 200, 201, 202, 204, method 265, in 805171 208, 206, 207, 208, 210,213, Instruction eache 86 handing 18 214, 215, 216, 217, 218, 221 cache Data cache 99 intLock 590 222, 224, 25, 227, 255, 260, level parallelism unit 86 intUnlock 590 312, 313, 314, 315, 316, 317 pointer 85 inversion problem 318 2327, 329, 366, 367, 368, 370, pointer IP) 11 10 Addresses Mapped 10.77 2372, 373, 394, 414, 439, 448, queue 86 bus 76 454, 461, 462, 498, 16, S18, Level Parallelism 104, 105 Byte Programming 66 519, $20, 531, 578, 600, 643 instructions 91, 101, 385 device 79, 130, 151 call 212 INTO 69,72 eves map _ 109 Tateney 262 INT 69.72 Interfaces 13 Queues 259 Ineprated development 26,27 Port Bit Programming 66 TL 008 Intel 636, Ports 66 ISRs._18, 196, 326, 328,395, 383, Hex 628, 629 Ports, 10 Buses 13, ‘354, 358, 359, 360, 362, 377 XScale 94 stream 268 2388, 395, 411, 494, 515.640, 642 Inver Processor Communication System 47 ISRS and device drivers 23 aPC) 291 mapped 629 IST 198, 369) inerface 277 IP 31, 174, 216, $39,555, 560, IST 260, 353, 384, 377 inerfacing 68,72 643, 652, circuit 68 address 2, 170, 171 J Internal RAM 12 Instruction 88 Internet Enabled Systems 170 Pai 542 DME 383 layer 543 IPC 293, 312,316,317, 319.331, Java 236, 263, 266, 265, 267, 268, interoperability 382 1382, 333, 334, 335, 337,340, 307, 395 Interpreter 25,27. 621, 624 ML, 342, 345, 354, 373, 408, 2 267accelerator 643 Card 267, 268, 98 embedded card 110, 111 objects 268. PipelnputOutputStreams 339 Jarelle Java execution accelerator 4 INI 267 JVM 94, 266,267, 268, 595 K kemel 307,312, 313, 330, 353,354, 408) smode 352 space 370) sack 311 Timeslice 458 Keyboard 82 is 17 keypad 17, 285, 286 ey-sate 146, 608 KVM. 267 L LAN 175,176 language 299 Latency 214, 643 LED 14, 17,48, 50, 143, 195, 199, 2383, 97,513, 521, 532 Contoller 50, 148, 149 display 82, 83 Display or Touch Sereen S18 LED and touchscreen 82 LED. 14,17 Tests 653 less than 286 brary 22, 23, 236 library functions 264, 381 life eyele 64 LIPO 243, 445, 456, 637 lightweight 307 Linked lists 641 Tinker 20, 21, 622, 627 Vink-register 203, 211, 217 Linux 312,332, 681 26x 496, 400 Device Drivers 229 Internals 228 kernel 497, 498, Modules 498 Lis 370 Hist 242, 250 Listen funetion 492 Lite Endian 102 Load 101 loader 21, 625,626 locator 21, 26,27, 109, 621,622, 627, 628, 629, 631, 632 Lock 334,396, 455 locking 335 Logic 65, ‘Analyzer 622, 624, 655 Instructions 65 Probe 683 Logical Instructions 91 Look-up 639 lookup table 242 loop 252 back 223 contol instuetions 66 Loosely coupled 291 Low-voltage operation 384 LST 14s LyCMOS 130 LVITL 150 MAC 96, 176, 198, 179 MacOSX 370 MAC unit 33 MACIOctal_ 97 machine 19 code 19, 20 or Real ime 119 Macro 240, $89,590, 600 MACROS 239 ‘mailbox. 240, 337, 338, 339, 368, 409, 437,438, 445, 439, 440, 441, 42,443, 444, 449,523, 525 Main "240,261 function 237 Mapping 37 maps 631 mask bits 207 smaskable 18, 207 Index master 132 ‘master device 135 mCOS-IT_ 308, 409 nCOSL RTOS 337 Mealy model 283 Media processor 33 Median sale embedded 52,53 rmomory 12, 68,372 459,406, 631, 639 Adérese Mapped 10, Operations 75 allocation 359,378, 371, 412 ‘map 109 ike 424 circuits 69 Imanagement 354,359,371, 482 ‘manager 361 Managing 360 snap 110, 1,112, 13, 629, 30 Onsnicaton 78,101 protection "360 Blick 13,50, 120 tater “14 management Unit 86 rapped 629 Memscope 654 Message 387, 609 on 493,568, 569,612 pointer “399 Gueue 487, $00,572 method everlding, 263 overriding 263 MrLOPs. of2 MIM. 135 ricwarchitectre 93 Miwehip 636 Microcontroller 5,6, 7. 89, 35,4445, 7.115, 117,517,518 535,573,374, S77, 582,583 595, 635,636,637 Core 625 Selection 114 iicrokerel 354 Imiroprocenoe 4,5, 6.7.32 MIDI $68, 569,970, $71,572, S73, sm MIDP. 268 Million insructons Per Second MPs) 6 MIMD 290, 636Index: MIME 171 MIPS 542 MIPS RSOO0 are other 94 Miso. 130. MISRA C495, 585,586 MISRA C version 585 MMU 84, 98, 00, 360, 361 mobile 286 computer 50 Phone $0, 119, 195,285,383, 440 phone device 331 phone keypad 146, 147 ‘hone LCD. 337 mode key 604, 605 models 23 Modem 18, 17 Modifier 250, 251 Modular Design 37 programming approach 236 module initialization 498 Monitor 621, 625, 658, 659 codes 657 MOST 130, 132 Motorola 627, 628, 636 MPEG. 10 MSG_ 470 rmsgQCreate 469, 471, 547, 554 smsgQSend 470,471, 550, 551 352, 553 MUCOS 408,411, 412, 413, 414, 415, 416, 417, 422, 437, 440, Ho, 449, 456, 459, 498, 498, 522 Multibyte Store "101 ‘Malt-dimensional aray) 250 Multilevel Buses. 75, Multiple inheritance 264 multiplexer is 14 multiprocessor 33,292, 642 MULTIPROCESSOR SYSTEMS 288, 293 ‘multirate operations ‘multitasking 319, 328, 330, 354, 408, 479,485 program 284 ‘multithreaded 307, 479, 485 Music file $1 Musical Instrument Digital Interface S68 Mutex. 318,323,329, 331, 334, 396, 397, 500) priority inversion 455 semaphore 463 rnanoslcep 500 rested function 244 Nesting 368 rework 652 river 237 Interface Card 10 [Networked Embeclded Systems 159 NMI 210 Non-maskable 207 notification 486, $13, $32, 539, 570, $77, 606, NTP 171 null 248, 440, 463, pointer 241, 523 oO object 262, 276, 277, 278, 296, 207, 87, 517, 540, 372 Giagram | 298, 299 le 624 store 482 oriented design 295 of 80X86 88 general purpose registers 88 interrupt sources 18 RISC 87 tokens 281 OMAP of 36 fone master 161 dimension array 24 dimensional array 639 OOP 262, 263, 264, 265, 276 open 340, 36, 365, 473, 354 drain port 145, operating system 18, 340 System Interface 364 ‘operator overloading 263 optimize 385 Optimizing 41 the Power 383 or critical section 316 PROM 20 ORCHESTRA 567 forehestra 369 Playing Robots 326, 343, 389 Orchestrator 368, 569, 572, 573, 374, 608,609, 610, 613 ordered list 387, 388 organization 84 (OS 23, 24,307, 308, 309, 310, 311 ‘312, 313, 316, 318, 320, 321 322, 329, 381, 332, 333, 334, 2385, 336, 337, 338, 341,342, 345, 351, 392,353, 354, 385, £356, 357, 358, 359, 360, 361, 362, 363, 368, 365,367, 368, 382, 389, 390, 395, 396, 397, 398, 399, 400, 401, 402, 4494, 496, 585, 595, S98, 642 (kernel) 305 functions 340 pipe 339 scheduler 388 ENTER_CRITICAL 396, 413, 415 EXIT_CRITICAL 413,415 NOLERR 439) TASK_CREATE 418 TASK_RESUME 418 ‘TASK SUSPEND 418 TICK_PER 357 os’. 47 Oscilloscope 654 OSEK 495, 496, 983, $85, 586 OSes 330 OsEventDelete 359 Query 359 S-Hardware interface 641 OSInit 414, 418, 526 OSIntEmter 368, 414 OStniEmer ("431 OSIntExit 368, 415, OSISRSemPost () 367 OSMboxAccept 437, 444, $30, OSMboxCreate 441,526 OSMboxPend 39, 388, 439, 43, 444, 836 OSMBoxPost 337, 338, 438,443, 444, 528 OSMboxQuery 438, 439 OSMBoxWait 338) OSMemPut 424, 426 OsMemQuery OSMsgPend 573 126OSMseQAccept 336, 571, 611 Pp OSMsgQPend $71, 611 OSMseQPost 373,571, 373,611 Pand V_ 323,324,326 sq 380 OSQAccept 335 OsQCreste 335, 336, 380, package 290, 298 446, 50 picket is 31 OsQFIush 335, 336 PAGE_SIZE 641 OSQPend 335,336, 337. 452,456, Palm OS 50 602 PAN aso OsQPost 335,336, 446,447, 451, parallel bus 160, 166, 167, 169 601, 608, 604 device 147 COsQPositiont 335, 446, 447 1O bus 160 OSQQuery 335, 336, 380, 446,48 port 130, 133, 145, 146, 223, O88 374,379 225 OSSchedLock 396, 416 Port Inerfacing 149 OSSchedUnloek 4, 413, 416 partition 424 OSSemAccept 428,444, 527 Passing the references 258 OsSemCreate 430,432, 441,450, the Values 257 335 PC 211, 243, 244, 305, 306, 307, OsSemPend 314,316,317, 318, 308, 310, 311,323, 385,631 ‘319, 320, 321, 331, 358, 374, 640, 619, 630 379, 427,431, 432,433,436, PCB 306, 312, 385, 356, 365 442, 451, 436, 527, 528, 529, 603 or resource "2 OsSemPost” 316,317, 318,320, PCL 166, 167, 168, 169 2374, 428,429, 431, 432,43 PCL 217 434,436, 442, 528, 529, 602. 603 PCM. 16 OssemQuery 428, 429,443,444 PCS 151 OSstat 413,414, 419, 526 PDAs 268 Ossiat() 430 Performance 39, 01, $32 OSTask Resume 530 ‘Accelerators 643 OsTaskCreate 417.419.435.442, Index 612 4450, 459, 526, 527 Metric 400 OSTaskDelete () 377 periodic 385 OsTaskResume 417, Peripheral Transsctions Server 100 OSTaskSuspend 417.420, 456, persistence memory 60S, 605, 607 527, $28, 529, 530 Personalization Key 46 OsTiektnit” 413,419, 421 Patri net 307 OSTimoDIy 422, 423,431,436, PECU 8s 443, 445, 452, 456, 530, 602 Phillips 636 OsTimeDIyesume 432 physical 24,25 OSTimeDIyHMSM 422, 424 Device 24, 221 422, 436,437, PIC 16FS4_§,32 529, 603, 604 PICs 8,32 OsTimeset” 417, 421 Piconet 570, 372,573, 574 OTP 106 PIM. 46, 482 ROM 107 pipe 24, 223, 242, 247, 340, 41, Ourstream $45,553 472,473 Overtiding 6 pineDevCreate 473, Index pipeline 86,90, 104, 289 Pipelining 105 Pipes 331 PISO 13 Pixel coprocessor 9, $35 Platform independence 266 dependency 641 PLO 635 Unit 6536 PLD 75, PMA 151, 228 PocketPC. ‘$0, 149, 479, 482, 489 pointer 241, 242, 243, 244, 285, 246, 247, 248, 249, 637 polled bas “168 Polling 80,81, 82,100, 210, 255, 274, 361 pop 243 port 518,521, 533 by devices 582 Deliver $15 ISR 223 poruability 382 ports 14, 514,515, 516, 519. POSIX 226, 364, 366, 153,409, 499, 626 Loa 326, 1003.1 322 FIPO 484 ‘queues 472 Tes 485 posting the mailbox IPC 338 power 384,385, Dissipation 39,41 ‘manager 480 supply 10.47 PPL 18S preempt 392 preemption 368, 394,395 preemptive 313, 385, 401, 412,461 scheduler 386 Scheduling 392, 395 Prefeich contol unit 86 preprocessor 237 constants 239 eclarations 237 directive 238 Directives 239Index: slobal variables 239 Pre-Scalar 155, Primary 4 Princoton 629 Architecture 103, 630 memory 89 printer. Assume 79 priorities 330, 303, 499, 525 priority 209, 210, 211, 307, 308, 310, 318, 321, 334, 417,418, 456 eviling 408 inperitance 330 Inversion 32 scheduling 461 based 387 ‘based scheduling 388 procedure-based language 262 Process 305, 307,313, 323, 2341, 345, 355, 479, 486, 496 1 x 1 306 3326 © 324 control block 305 Creation 385 eadlinos 39, 42,513 wD 497 management 384,355, 371 manager ereates 356 for task oF thread 240 state 305, structure 308, 307 processes 23, 289, 312, 325, 342 351, 352,353, 485, 497 processing "18 processor 5,6, 72 organization 86 PROCESSOR SELECTION 113 Tess 635 sensitive 638 sensitive memory-sensitive 640 Process-state signal 306 producer-consumer 325, program 23, 65, 74 sounter (PC) 11,62, 84, 85, ‘313, 324,387, 388, 391, 305 low Control Instructions "66 layers 22 memory 68, 482 Model 23 306 counter 84 programmed: busy-wait 189 Programming model 255,258 PROM 12,13, 21, 106, 107, 108, 632 property 276 Protection 402 protocol 15, 62,344 stack processor 9 Prowwiype 39, 650,653, Protoryper 26, 27 PSEN 68 PSW 3 pthread_matex 500 wait” 503 pump 47 push 243 pushing 244 PWM 15,51 a QAM 135 QEnor 336 Qos 174 Qrio 567 Quarter CIF 9,34 quasi bidirectional 145 Query 338 queue 240, 242, 244, 246,247, 249, 335, 336, 378, 380, 409, 445, 47, 448, 450, 451, 452, 683 queue-telated 49 mailboxes 331 Queuing 260 R RAM. 12,45, 45, isk 223,482 memory 13 parity error 210 Rate Monotonic 398 ‘Monotonic Scheduler 399 RD 68.73. RDRAM 109 read M0, 364, 365, 473, 554 038 Posts $17,520 Range 583 09, 110 Realtime clock 158, 159 Time Linux 496 time Robotic 115 time 497 time clock 11, 248, 356 time FIFO 504 Time Program 642 time programming | 385 time task $02 ‘Time Video Processing 117 Recursive funetion 240 Reev 492 reentrant 313, 328 function 240 Registering 498 Registering, De-Registering 503 Registry 483,484 Reliability 42, 585 Remote procedure 331 requeney hopping 178 Requirements 513, 531, 570, 593, 604, 605, 606 fof sae card” 594 Reset IT reset value 85 Resource 318, 323 Key 316, 317 type 385 resources 334 Rest Vectors 624 restricted runtime 268 RETI 65 return 190 return 191, 193 RI 205 Right Platform 635 RISC 33, 88,98 formats 89 RKE 375 Robert Metcalfe 175 Robin Time 389 time-slice 461 robot 51, 52, 117, 631 Functions "St forehestra $68, $70, $72 orchestra 569 Robotic 116 ROM 12, 19, 21, 45, 46, 106, 107, 108, 109, 10, 116. 117, 482 ROM Emulator 649image 19,20, 10, 626 image are "22 image fle 118 ROS 314 Round Robin 388, 390 (time slicing) scheduling 385, time 390) routers 174 RS232C 136, 137, 634 RS2H2C Port 632 RSAKS 138) RSA. 595 RIC 257,263, 588, 389, 390 RTLinux 496, 501, 502,503, 504 RTO. 478 RTOS 24,27, 333, 359, 363, 369, 370, 371, 372, 373, 395, 376, 2377, 378, 381, 385, 392, 393, 304, 397, 409, 410, 411,412, 413, 415, 453, 454, 478, 515, $22, $77, 621, 623, 642 RTOS kernel 415 mCOS-I 360, 368, provides 23 scheduler 375 timer functions 387 VxWorks 537 Windows CE 352 RTOS's 408) RTOSes 332 RxD 633 RARDY 79,80 s Scalable 378, 454 hierarchical RTOS 382 scheduler 313, 385, 386, 387, 389, 390, 391, 392, 394, 395, 397, 2398, 401 408, 486 Scheduling 385, 386, 393 funetions 23 Schmitt tigger 150 SCI 142, 576 SCLK. 130 ScopeProfile 654 Seratchipad Memory 607 Screen State 254 SDF graph 291 SDFGs 291, 293, SDIO_ 142, 143, 165 card 133 SDK 4x0 Secondary memory 4 level 207 second-level interrupt service ‘head 199 Section 314 Section 3.12.1 170 selt-host 410 semaphore 240, 284, 314, 315, 3ho, 317, 318, 319, 320, 323, 325, 328, 329, 330, 31, 332, 375, 39, 409, 412, 426, 428, 4448, 455, 463, 494, 49, 599 functions 487 SEMAPHORES 322, 378, 409, 525 somel 326 semBCreate 463, 464,467, 546 Cereate 468 Flush 463, 485, 467 Give 463, 464, 465, 466, 467, 469, 540, $51, 952, 553, S91, 592,593 MCreale 465,466, 467 Pend 602 Take 463, 464, 465, 466, 468, 470, 349 ‘Take 380, 951, $52, 393,554, 501,592 Send funetion 492 Sequence diagram 208 sequential model 280 ‘program model 274 programming model 275 SerDes 151 Serial asynehronous output 134 lock 161 Data Communication 139 line device 78 por 130 Port Drivers 226 pons 69,70 SERVICES 351, 353, servo motors 67 SHARC 95, 105 Shared 327,328 ‘bus 290, 201 Data” 329, 652 Index memory _ 455, 496, 500, 501, 502 Shooting 532 show 175 SE 69, 70,71, 72,215 SigACC 587 sigHlandler 462 signal 199, 201, 204, 284,297, 1306, 31, 332, 335, 462, 499, 5313, $39, 570, 606 Ihandier "203 Signals, events $32, 377 Events and Notifications S04 SIMD 33, 89,94, 636 SIMDs 290 Simulated annealing method 400 simulates 623 Simulator 26,27, 621, 650, 683, (651, 652, 620, 625, 649 Single Purpose Processors 6, 8, 635 purpose processors and ‘application specifie 35 stepping 210 siP0135, Six Tasks 523 Skills 54 for Small Seale 53, slave doviee 135 slice 392 SLISR 198 SLISRs 370 slow-level ISR 369 ‘Small scale embedded 52 smart 45, 602 cud 44, 47, 110, 111, 267,268, 3409, 341, 593, 595, 631 card processor 46 ‘mobile phone 254 os 603 OsTickinit 601 SMS 50,147, 604, 606, 607, 608, 610,611, 613 SMS Create 607, 608 SoC 29,30 socket 24, 342, 345, 489, 491, 492 descriptor 306, 343, sockets 51, 331, 3, 344 soft real time 372, 381 software 25, 211 Architecture 519, 541, $72 components 52Index: evelopment process 41 exceptions 202 instctionelated sources 201 imerrupt 18, 192 interrupt (SW) 196 imtecrupt instruction (SWL) 195 timer 155, 156, 157 timer 606 Tools 25, 26,620, 622, 627 traps 202 Sophisticated embedded systems: 52 Source 27 Code Engineering 622 files 237, 239 SP_ 84, 244, 305, 306, 308, 310, 311, 312,355 Specifications 40, 514, 515 SPI. 14,142 spin 381 Lock 334, 335, 371, 396 sporadic 385, 399, 401 Sporadic tsk | 398 SPSR 212,213 SRAM 108 Scrocord 628 SRS 84, 86 SSTL 150 stack 191, 244, 249, 637 pointer 62, 211, 243, pointer 85, 217 stacks 321, 643 standawd file 482 Start Timer 526 state 276, 286, 287, 296, 298, 305, 300,355 diagram 298, 299, 517, $40, ‘572, 373,610 smacine 282 ‘machine model 275 of akey 613 table 285,286, 288 transition 285 ‘wansiion function 282, 284 ‘ransition-fonetions (Moore model) 283. states 282, 284, 285, 288, 308, 309, 336 ‘machine (FSM) 284 of atimer 283 state-transition 607 ‘TranstionFunetion 285 static 251 scheduling 281, 290 scheduling issue 250 Status flag 155 register 78, 640 stepper motor 67, M47, 148, 578, 382 stereotype 296, 207 Stethoscope 26,27, 654 stop 117 storage 655 Store 101, 102 string 639 StrongARM SA-110 04, 114 structural 383 structuse 352,353, SuperHt 410) Superscalar 105 processor 289) Units 108 Supervisory’ mode 352, 353, SWI 197, 202, 204, 254, 287, 288 switch 254 case 237 switching 391 SWT 155, 227,228, 257, 263 SWI 155 Symbian OS 50 Synchronization Diagram S21 37 model 522, 536, 542, 574, 583, 585, 396, 575, $97, 613 synchronous 135 Communication 134 HDLC provoco! 139 input 133 10 operations 365 serial 130 Serial Input-Output 132 Serial Output 131 serial port registers M42 SyneML 176 SysC_ 397 SysCiklnir 356 system 3, 343 Bus 72, 74,76 buses 80,81, 85 clock 155,159, 414, 460 design 41 imerrupts 159 Timers 11 call 3 T T 606 T 68,09,70,71 TL 68, 70,71 TH in 8051 68 12 68 19 keypad 61L ‘To-koys 604 table 242,247, 248 Target 620,623, 624, 62: (649, 652, 656, 657, 659 targeted 632 tusk 282, 283, 289, 294, 308, 312, 313, 314, 315, 316, 318, 2323, 325, 385, 396, 494, Si, ‘517, $20, $21, $24, 525, 526, 5520, $30, $71, $72, 574, 580, ‘581, $82, 587, 588, $90,591, ‘592, 593, 595, 596, 598, $99, 601,602, 603, 608 1299 2 322 A3i7 fcontrol 311 create 376 Delay 412, 549, 550, 551,352, 333 delete 376, 459 Function S84 so 290 stacks 308, 317, 524 User 519 3395 Conductor 570 ieonet $71 1.397, 398 SMS_Create 608 3 320 Delete (). 467 Lock () 458: Priority 417 PrioityGet 458 PriorityGet () 458. PrioityPat 458 PrioviySet () 458Resume 457, 550, 551, 552,553 tasks 23,295, 319, 320, 325, 326, 372, 386, 515, $16, 543, 38, 507, 613 taskSafe 459 scheduler 307 Spawn 456, 468, 588 Suspend 459 Unlosk () 438 TCR 38, 310, 31 356, 454, 459 TCP 173, 174, 42, $37, 530, S40, 545, 585 header S41, 556 or UDP 338 TCPAP 44,171, 173, $38, 39, 581 ‘TCPAP network "170 TTCPAP stick $39 Checksuml6 357 Flag S46, Hd 556 Header $55,387 ‘TELNET 171 Template 263 ‘Test 513,539, 607, 651 ‘and validation $32, 578,570,595 testing 622 Tests 650 test-vectors 623 Text Messages 605 fextospecch converters 576 the internal RAM, SFR 68 latency 361 pixel processor 49 process 308 resource 316 semaphore as 449 thread 307, 386, 486, 499, 30S period $01 stack 308 Priorities 479 scheduler 308 stack 307 ‘Threads 306, 485, 496, 502 throttle $78, $79, $81, 584, $85 throughput 643 throwing 195, 197 Thumb 93 Thumb 91,93 313, 315,355, T1205 TigerSHARC 96, 114 tightly coupled processors 290, 291 Time 388 sivision matiplexing 154 functions 500 slices 499 slicing 154, 371 Triggered Provocol 582 Timer 153, 154, 156, 157,158, 215, 221,227, 494 Functions 356 interrupt 208 fime-slice 461 torlive 174 to-market 39 TIPS 455 TMS320062XX 33 to quewe 356 tokens 284 tool 650 Top-down design 235, top-to-down 38 {ouch screen 14, 17,50, 209, 268, 369, 480, 488, $32, 576 Trace scope 26.27 TraceSeope 654 track S71 transceiver 597 transition 608 fap 192, 202 tus 204 Tree 250 lwiggering 623 ‘Tworst 390 TxD 633,604 TxDE_ 79,80 type checking 237 typeder 241 u UART 14, 130, 132, 133, 136, 137, 138, 140, 141, 189, 201, 226, 236, 257, 366, 637 16550 226 8250226 UDP 342, 539, 541, 543, $46, 555 UDPDatagram 538,540, 542, 545 Index UML 23,43, 295, 296, 297, 298, S15, 517, $40, 653 unblocking 420, PIN 46 Unicode 639 Unified 299 Unix 307,31 sevice driver ‘operating 459 unlock 334, 435 unlocks 335 USB 49, 50, $35, bas 194) bus cable 164 isaserial 165 or FireWire 560 port 532,533, 48 User mode 352 UWB. 165, v Validation 42, $13,539 Vector 206 ‘Address. 204, 71 ‘addresses 19 table 207 Verification 41 video graphic adapter 9 viral 223, 25 base classes 264 eviee 223, 24 machine 266 memory 480 VLIW 33,97 in TMS320C6. 200 VLIWs. 295 VLSI design 31 Voice Data Compression 117 recorder 120 void main 252 Ostnit 413 OStntE mer 413 OstuExit 413 resetTask 601 VoIP 392, volatile 251 Volt Ohim Meter 653 VPN 3t= VxSim 650,654 o-while, beak 237 WLAN 179 ‘VaWorks 308, 332, 453,454, 455, WiFi 181, 576, WLAN 802.11 569 456, 458,459, 460, 467,469, Win? 484, 492,493 WNet API 489 472, 495,499, 538,586, APL 492 WNeis 491 623, 626, 654 eaphies 493 Worst case lateney 214 VaWorks scheduler 494 wind 499 cxccuton time 400 aWorks 409 Window NT 365 latencies 387 vaWorksh 464, 466 Windows 409, 651 lateney 329, 386, 308 CE 50,478, 480, 481, 482, 485, WPAN 160, 177 w 4897 WR 73 CEO 485 write M0, 364, 365, 473 woitig 304 CE Features 479 vite () 343 state 383 CCE Serial Communication 490 ‘watchdog timer 12,154, 157,329, CENET 478 x 461 Controls 488 timerrelaed 460 Management 482 XCITE 150 timers 376 Menus 489 Xilinx | 150 WCE 483, 484,486, 488,489, 491, Mobile 50 X-Windows 497 492, 493,494 WindRiver 458, WCE serial port 489 Winsock 489 Zz fits tarmacee “a Wireless devices 151 ‘while loop 252 TAN tea Le Zighee 181, 175,177,179 USB. 165