Verilog program for dual rom:

module romc ( clk, addr1, addr2, dout1, dout2 );

input clk ; // Declare I/Os.

input [2:0] addr1 ;
input [2:0] addr2 ;

output [63:0] dout1;

output [63:0] dout2;

reg [63:0] dout1_next ; // This is the next value that will

// be loaded into dout1_reg1.
reg [63:0] dout2_next ;
reg [63:0] dout1_reg1 ; // First pipeline registers.
reg [63:0] dout2_reg1 ;
reg [63:0] dout1; // Second pipeline registers,
reg [63:0] dout2; // i.e., final outputs.
wire [63:0] loc0 ; // ROM data declared as nets.
wire [63:0] loc1 ;
wire [63:0] loc2 ;
wire [63:0] loc3 ;
wire [63:0] loc4 ;
wire [63:0] loc5 ;
wire [63:0] loc6 ;
wire [63:0] loc7 ; //2 × C or 2 × CT ROM table organized as 8 × 64 bits.

assign loc0 = 64'h5B5B5B5B5B5B5B5B ; // ROM data -

assign loc1 = 64'h7E6A4719E7B99682 ; // eight numbers
assign loc2 = 64'h7631CF8A8ACF3176 ; // of 8 bits data
assign loc3 = 64'h6AE782B9477E1996 ; // per location.
assign loc4 = 64'h5BA5A55B5BA5A55B ;
assign loc5 = 64'h4782196A96E77EB9 ;
assign loc6 = 64'h318A76CFCF768A31 ;
assign loc7 = 64'h19B96A827E9647E7 ;
always @ (loc0 or loc1 or loc2 or loc3 or loc4 or loc5 or loc6 or loc7 or addr1 or addr2)
begin
case (addr1) // Addressed data is accessed whenever there is a change
// in any of the inputs in the always statement.
// addr1 serves as the address to read C matrix
data.
3'b000 : dout1_next = loc0 ;
3'b001 : dout1_next = loc1 ;
3'b010 : dout1_next = loc2 ;
3'b011 : dout1_next = loc3 ;
3'b100 : dout1_next = loc4 ;
3'b101 : dout1_next = loc5 ;
3'b110 : dout1_next = loc6 ;
3'b111 : dout1_next = loc7 ;
default : dout1_next = loc0 ;
endcase

case(addr2)
// addr1 serves as the address to read C matrix
data.
3'b000 : dout2_next = loc0 ;
3'b001 : dout2_next = loc1 ;
3'b010 : dout2_next = loc2 ;
3'b011 : dout2_next = loc3 ;
3'b100 : dout2_next = loc4 ;
3'b101 : dout2_next = loc5 ;
3'b110 : dout2_next = loc6 ;
3'b111 : dout2_next = loc7 ;
default : dout2_next = loc0 ;
endcase
end

always @ (posedge clk) // First pipeline stage

begin
dout1_reg1 <= dout1_next ; // Pipeline registers.
dout2_reg1 <= dout2_next ;
end
always @ (posedge clk) // Second pipeline
begin
dout1 <= dout1_reg1 ; // Data outputs read using addr1
dout2 <= dout2_reg1 ; // and addr2 respectively.
end
endmodule
 verilog program for romq:

module romq (clk, a, d);

input clk; // Declare I/Os.
input [5:0] a; // This is the 6-bit address and

output [7:0] d; // data output of ROM.

reg [7:0] d; // Declare as the register.

reg [63:0] mem [7:0] ; // ROM organized as 8x64
reg [7:0] byte_data [7:0] ; // bits, but read byte-by-byte.

wire [7:0] d_next ; // Declare as the wire.

wire [63:0] mem_data ; // Declare ‘assign’ outputs as wire.
wire [63:0] loc0 ;
wire [63:0] loc1 ;
wire [63:0] loc2 ;
wire [63:0] loc3 ;
wire [63:0] loc4 ;
wire [63:0] loc5 ;
wire [63:0] loc6 ;
wire [63:0] loc7 ;

assign loc0 = 64'hFF806C5D4F4C473C ;

assign loc1 = 64'h80805D554C473C37 ;
assign loc2 = 64'h6C5D4F4C473C3C36 ;
assign loc3 = 64'h5D5D4F4C473C3733 ;
assign loc4 = 64'h5D4F4C47403B332B ;
assign loc5 = 64'h4F4C47403B332B23 ;
assign loc6 = 64'h4F4C473C362D251E ;
assign loc7 = 64'h4C473B362D251E19 ;
always @ (loc0 or loc1 or loc2 or loc3 or loc4 or loc5 or loc6 or loc7)

begin // Bytes from each row is accessed in a raster scan order (MSB first, etc).
mem [0] = loc0 ;
mem [1] = loc1 ;
mem [2] = loc2 ;
mem [3] = loc3 ;
mem [4] = loc4 ;
mem [5] = loc5 ;
mem [6] = loc6 ;
mem [7] = loc7 ;
end

always @ (mem_data)
begin
byte_data [0] = mem_data [63:56] ; // MSB is assigned as
byte_data [1] = mem_data [55:48] ; // LSB.
byte_data [2] = mem_data [47:40] ;
byte_data [3] = mem_data [39:32] ;
byte_data [4] = mem_data [31:24] ;
byte_data [5] = mem_data [23:16] ;
byte_data [6] = mem_data [15:8] ;
byte_data [7] = mem_data [7:0] ; // LSB is assigned as MSB.
end
assign mem_data = mem [a[5:3]] ; // Get 64 bits data.
assign d_next = byte_data [a[2:0]] ; // Get byte data.
always @ (posedge clk)
d <= d_next ; // Register byte data.
Endmodule
 Verilog code for Ram_rc:

module ram_rc ( clk, pci_clk, rnw,be, ra, wa, di, din_valid, do ) ;

input clk ; // Declare I/Os.

input pci_clk ;
input rnw ;
input din_valid ;
input [7:0] be ;
input [2:0] ra ;
input [2:0] wa ;
input [63:0] di ;

output [63:0] do ;

reg [63:0] do ; // Declare registered outputs.

wire [63:0] mem_data ; // Declare all wire signals.

wire [63:0] do_next ;
wire [2:0] addr ;
wire 63:0] loc0 ;
wire [63:0] loc1 ;
wire [63:0] loc2 ;
wire [63:0] loc3 ;
wire [63:0] loc4 ;
wire [63:0] loc5 ;
wire [63:0] loc6 ;
wire [63:0] loc7 ;
wire be0 ;
wire be1 ;
wire be2 ;
wire be3 ;
wire be4 ;
wire be5 ;
wire be6 ;
wire be7 ;

reg [63:0] column ;

reg [63:0] mem [7:0] ; // Declare register array, 8×64 bits.

assign addr = (rnw) ? wa : ra ; // Get write address (rnw = 1) or read address.

assign mem_data = mem [addr] ; // Fetch the memory content.
assign loc0 = mem [0] ; // Intermediate store for memory.
assign loc1 = mem [1] ;
assign loc2 = mem [2] ;
assign loc3 = mem [3] ;
assign loc4 = mem [4] ;
assign loc5 = mem [5] ;
assign loc6 = mem [6] ;
assign loc7 = mem [7] ;

always @ (addr or loc0 or loc1 or loc2 or loc3 or loc4 or loc5 or loc6 or loc7)
begin
case (addr) // Read the RAM column-wise.
3'b000:
column = {loc0[63:56], loc1[63:56], loc2[63:56], loc3[63:56], loc4[63:56],loc5[63:56],
loc6[63:56],
loc7[63:56]} ;
3'b001:
column = {loc0[55:48], loc1[55:48], loc2[55:48], loc3[55:48], loc4[55:48], loc5[55:48],
loc6[55:48],
loc7[55:48]} ;
3'b010:
column = {loc0[47:40], loc1[47:40], loc2[47:40], loc3[47:40], loc4[47:40], loc5[47:40],
loc6[47:40],
loc7[47:40]} ;
3'b011:
column = {loc0[39:32], loc1[39:32], loc2[39:32], loc3[39:32], loc4[39:32], loc5[39:32],
loc6[39:32],
loc7[39:32]} ;
3'b100:
column = {loc0[31:24], loc1[31:24], loc2[31:24], loc3[31:24], loc4[31:24], loc5[31:24],
loc6[31:24],
loc7[31:24]} ;
3'b101:
column = {loc0[23:16], loc1[23:16], loc2[23:16], loc3[23:16], loc4[23:16], loc5[23:16],
loc6[23:16],
loc7[23:16]} ;
3'b110:
column = {loc0[15:8], loc1[15:8], loc2[15:8], loc3[15:8], loc4[15:8], loc5[15:8], loc6[15:8],
loc7[15:8]} ;
3'b111:
column = {loc0[7:0], loc1[7:0], loc2[7:0], loc3[7:0], loc4[7:0], loc5[7:0], loc6[7:0], loc7[7:0]} ;
default :
column = {loc0[7:0], loc1[7:0], loc2[7:0], loc3[7:0], loc4[7:0], loc5[7:0], loc6[7:0], loc7[7:0]} ;
endcase
end
assign be7 = (!be[7]) & rnw & din_valid ; // Enable write only if be7 = 1, and so on.
assign be6 = (!be[6]) & rnw & din_valid ;
assign be5 = (!be[5]) & rnw & din_valid ;
assign be4 = (!be[4]) & rnw & din_valid ;
assign be3 = (!be[3]) & rnw & din_valid ;
assign be2 = (!be[2]) & rnw & din_valid ;
assign be1 = (!be[1]) & rnw & din_valid ;
assign be0 = (!be[0]) & rnw & din_valid ;
always @ (posedge pci_clk)
begin // Write into RAM only if be7 = 1, and so on.
// Otherwise, don’t disturb the RAM contents.
mem [addr] <= { ( (be7) ? di[63:56] : mem_data[63:56] ),
( (be6) ? di[55:48] : mem_data[55:48] ),
( (be5) ? di[47:40] : mem_data[47:40] ),
( (be4) ? di[39:32] : mem_data[39:32] ),
( (be3) ? di[31:24] : mem_data[31:24] ),
( (be2) ? di[23:16] : mem_data[23:16] ),
( (be1) ? di[15:8] : mem_data[15:8] ),
( (be0) ? di[7:0] : mem_data[7:0] ) } ;
end
assign do_next = (rnw) ? do : column ;
// Read column-wise from RAM only if rnw = 0.
// Otherwise, don’t disturb.
always @ (posedge clk)
do <= do_next ; // Register the output.
Endmodule

verilog code for dual ram:

`include “ram_rc.v” // This is the individual RAM // code file.

module dualram ( clk, pci_clk, rnw, be, ra, wa, di, din_valid, do ) ;

input clk ; // System clock.

input pci_clk ;
input rnw ;
input din_valid ;
input [7:0] be ;
input [2:0] ra, wa ;
input [63:0] di ; // Data input and

output [63:0] do ; // Data output of dual RAM.

wire switch_bank; // Declare net outputs.

wire [63:0] do1 ;
wire [63:0] do2 ;
wire [63:0] do_next ;
reg [63:0] do; // Declare registered outputs.
reg rnw_delay ;

assign switch_bank = ~rnw; // Configure ram1/ram2 for read and write

// mode respectively to start with.

ram_rc ram1 ( clk, pci_clk, rnw, be, ra, wa, di, din_valid, do1) ;

ram_rc ram2( clk, pci_clk, switch_bank, be, ra, wa, di, din_valid, do2) ;

assign do_next = (rnw_delay) ? do2 : do1 ; // Read ram2 or ram1.

always @ (posedge clk)

begin
rnw_delay <= rnw ; // Delay the rnw signal by one clock.
do <= do_next ; // Register the selected RAM output.
end
endmodule

Ram_rc writing data into the memory

Ram _rc reading Data from memory

Dual ram writing data into the memory

Dual ram reading data from the memory

*********************************************************************

module adder12s ( clk,n0,n1,n2,n3,n4,n5,n6,n7,sum) ;

input clk ;
input [11:0] n0 ;
input [11:0] n1 ;
input [11:0] n2 ;
input [11:0] n3 ;
input [11:0] n4 ;
input [11:0] n5 ;
input [11:0] n6 ;
input [11:0] n7 ;

output [14:0] sum ;

wire [7:0] s00_lsb ;

wire [7:0] s01_lsb ;
wire [7:0] s02_lsb ;
wire [7:0] s03_lsb ;

wire [5:0] s00_msb ;

wire [5:0] s01_msb ;
wire [5:0] s02_msb ;
wire [5:0] s03_msb ;

wire [7:0] s10_lsb ;

wire [7:0] s11_lsb ;

wire [6:0] s10_msb ;

wire [6:0] s11_msb ;

wire [7:0] s20_lsb ;

reg [11:7] n0_reg1 ;

reg [11:7] n1_reg1 ;
reg [11:7] n2_reg1 ;
reg [11:7] n3_reg1 ;
reg [11:7] n4_reg1 ;
reg [11:7] n5_reg1 ;
reg [11:7] n6_reg1 ;
reg [11:7] n7_reg1 ;

reg [7:0] s00_lsbreg1 ;

reg [7:0] s01_lsbreg1 ;
reg [7:0] s02_lsbreg1 ;
reg [7:0] s03_lsbreg1 ;
reg [5:0] s00_msbreg2 ;
reg [5:0] s01_msbreg2 ;
reg [5:0] s02_msbreg2 ;
reg [5:0] s03_msbreg2 ;

reg [6:0] s00_lsbreg2 ;

reg [6:0] s01_lsbreg2 ;
reg [6:0] s02_lsbreg2 ;
reg [6:0] s03_lsbreg2 ;

reg [7:0] s10_lsbreg3 ;

reg [7:0] s11_lsbreg3 ;

reg [5:0] s00_msbreg3 ;

reg [5:0] s01_msbreg3 ;
reg [5:0] s02_msbreg3 ;
reg [5:0] s03_msbreg3 ;

reg [6:0] s10_lsbreg4 ;

reg [6:0] s11_lsbreg4 ;
reg [6:0] s10_msbreg4 ;
reg [6:0] s11_msbreg4 ;

reg [6:0] s10_msbreg5 ;

reg [6:0] s11_msbreg5 ;

reg s20_lsbreg5cy ;

reg [6:0] s20_lsbreg5 ;

// First Stage Addition

assign s00_lsb[7:0] = n0[6:0]+n1[6:0] ;
// Add lsb first - s00_lsb[7] is the carry
assign s01_lsb[7:0] = n2[6:0]+n3[6:0] ;
// n0-n7 lsb need not be registered since addition is already carried out here.
assign s02_lsb[7:0] = n4[6:0]+n5[6:0] ;
assign s03_lsb[7:0] = n6[6:0]+n7[6:0] ;
always @ (posedge clk)
// Pipeline 1: clk (1). Register msb to continue
// addition of msb.
begin
n0_reg1[11:7] <= n0[11:7] ;
// Preserve all inputs for msb addition during the clk(2).
n1_reg1[11:7] <= n1[11:7] ;
n2_reg1[11:7] <= n2[11:7] ;
n3_reg1[11:7] <= n3[11:7] ;
n4_reg1[11:7] <= n4[11:7] ;
n5_reg1[11:7] <= n5[11:7] ;
n6_reg1[11:7] <= n6[11:7] ;
 n7_reg1[11:7] <= n7[11:7] ;
s00_lsbreg1[7:0] <= s00_lsb[7:0] ;
// Preserve all lsb sum. s00_lsbreg1[7] is the registered carry from lsb addition.
s01_lsbreg1[7:0] <= s01_lsb[7:0] ;
s02_lsbreg1[7:0] <= s02_lsb[7:0] ;
s03_lsbreg1[7:0] <= s03_lsb[7:0] ;
end
// Sign extended & msb added with carry.
assign s00_msb[5:0] = {n0_reg1[11], n0_reg1[11:7]}+{n1_reg1[11],
n1_reg1[11:7]}+s00_lsbreg1[7];//s00_msb[6] is ignored.
assign s01_msb[5:0] = {n2_reg1[11], n2_reg1[11:7]}+{n3_reg1[11],
n3_reg1[11:7]}+s01_lsbreg1[7];
assign s02_msb[5:0] = {n4_reg1[11], n4_reg1[11:7]}+{n5_reg1[11],
n5_reg1[11:7]}+s02_lsbreg1[7];
assign s03_msb[5:0] = {n6_reg1[11], n6_reg1[11:7]}+{n7_reg1[11],
n7_reg1[11:7]}+s03_lsbreg1[7];
always @ (posedge clk)
// Pipeline 2: clk (2). Register msb to continue addition of msb.
begin
s00_msbreg2[5:0] <= s00_msb[5:0] ; // Preserve all msb sum.
s01_msbreg2[5:0] <= s01_msb[5:0] ;
s02_msbreg2[5:0] <= s02_msb[5:0] ;
s03_msbreg2[5:0] <= s03_msb[5:0] ;
s00_lsbreg2[6:0] <= s00_lsbreg1[6:0] ; // Preserve all lsb sum.
s01_lsbreg2[6:0] <= s01_lsbreg1[6:0] ;
s02_lsbreg2[6:0] <= s02_lsbreg1[6:0] ;
s03_lsbreg2[6:0] <= s03_lsbreg1[6:0] ;
end

// Second Stage Addition

assign s10_lsb[7:0] =
s00_lsbreg2[6:0]+s01_lsbreg2[6:0] ;
//Add lsb first : s10_lsb[7] is the carry.
assign s11_lsb[7:0] = s02_lsbreg2[6:0]
+s03_lsbreg2[6:0] ;
//s00, s01 lsbs need not be registered
//since addition is already carried out here.
always @ (posedge clk)
// Pipeline 3: clk (3). Register msb to continue addition
of msb.
begin
s10_lsbreg3[7:0] <= s10_lsb[7:0] ; // Preserve
all lsb sum.
s11_lsbreg3[7:0] <= s11_lsb[7:0] ;
s00_msbreg3[5:0] <= s00_msbreg2[5:0];
// Preserve all msb sum.
s01_msbreg3[5:0] <= s01_msbreg2[5:0] ;
s02_msbreg3[5:0] <= s02_msbreg2[5:0] ;
s03_msbreg3[5:0] <= s03_msbreg2[5:0] ;
end
 assign s10_msb[6:0] =
{s00_msbreg3[5],s00_msbreg3[5:0]}+{s01_msbreg3[5],s01_msbreg3[5:0]}+s10_lsbreg3[7] ;
// Add MSB of second stage with sign extension and
carry in from LSB.
// s10_msb[7] is ignored.
assign s11_msb[6:0] = {s02_msbreg3[5],
s02_msbreg3[5:0]}+{s03_msbreg3[5], s03_msbreg3[5:0]}+s11_lsbreg3[7] ;
always @ (posedge clk)
// Pipeline 4: clk (4). Register msb to continue addition
of msb.
begin
s10_lsbreg4[6:0] <= s10_lsbreg3[6:0] ; // Preserve all lsb
sum.
s11_lsbreg4[6:0] <= s11_lsbreg3[6:0] ;
s10_msbreg4[6:0] <= s10_msb[6:0] ; // Preserve all msb
sum.
s11_msbreg4[6:0] <= s11_msb[6:0] ;
end

// Third Stage Addition

assign s20_lsb[7:0] =
s10_lsbreg4[6:0]+ s11_lsbreg4[6:0] ;
//Add lsb first :
s20_lsb[7] is the carry.
always @ (posedge clk)
// Pipeline 5:
clk (5). Register msb to continue addition of msb.
begin

s10_msbreg5[6:0] <= s10_msbreg4[6:0]; //Preserve all msb sum.

s11_msbreg5[6:0] <= s11_msbreg4[6:0] ;

s20_lsbreg5cy <= s20_lsb[7]; // Preserve all lsb sum.

s20_lsbreg5[6:0] <= s20_lsb[6:0];

end
// Add third
stage MSB results and concatenate
// with LSB
result to get the final result.
assign sum[14:0] =
{({s10_msbreg5[6], s10_msbreg5[6:0]}+{s11_msbreg5[6], s11_msbreg5[6:0]}+s20_lsbreg5cy),
s20_lsbreg5[6:0]};
endmodule

******************************************************************

module adder14s ( clk,n0,n1,n2,n3,n4,n5,n6,n7,sum) ;

input clk ;
input [13:0] n0 ;
input [13:0] n1 ;
input [13:0] n2 ;
input [13:0] n3 ;
input [13:0] n4 ;
input [13:0] n5 ;
input [13:0] n6 ;
input [13:0] n7 ;

output [19:0] sum ;

wire [8:0] s00_lsb ;

wire [8:0] s01_lsb ;
wire [8:0] s02_lsb ;
wire [8:0] s03_lsb ;

wire [7:0] s00_msb ;

wire [7:0] s01_msb ;
wire [7:0] s02_msb ;
wire [7:0] s03_msb ;

wire [9:0] s10_lsb ;

wire [9:0] s11_lsb ;

wire [8:0] s10_msb ;

wire [8:0] s11_msb ;

wire [10:0] s20_lsb ;

reg [13:8] n0_reg1 ;

reg [13:8] n1_reg1 ;
reg [13:8] n2_reg1 ;
reg [13:8] n3_reg1 ;
reg [13:8] n4_reg1 ;
reg [13:8] n5_reg1 ;
reg [13:8] n6_reg1 ;
reg [13:8] n7_reg1 ;

reg [8:0] s00_lsbreg1 ;

reg [8:0] s01_lsbreg1 ;
reg [8:0] s02_lsbreg1 ;
reg [8:0] s03_lsbreg1 ;

reg [7:0] s00_msbreg2 ;

reg [7:0] s01_msbreg2 ;
reg [7:0] s02_msbreg2 ;
reg [7:0] s03_msbreg2 ;

reg [8:0] s00_lsbreg2 ;

reg [8:0] s01_lsbreg2 ;
reg [8:0] s02_lsbreg2 ;
reg [8:0] s03_lsbreg2 ;

reg [9:0] s10_lsbreg3 ;

reg [9:0] s11_lsbreg3 ;

reg [7:0] s00_msbreg3 ;

reg [7:0] s01_msbreg3 ;
reg [7:0] s02_msbreg3 ;
reg [7:0] s03_msbreg3 ;

reg [9:0] s10_lsbreg4 ;

reg [9:0] s11_lsbreg4 ;

reg [8:0] s10_msbreg4 ;

reg [8:0] s11_msbreg4 ;

reg [8:0] s10_msbreg5 ;

reg [8:0] s11_msbreg5 ;

reg s20_lsbreg5cy ;
reg [9:0] s20_lsbreg5 ;

// First Stage Addition

assign s00_lsb[8:0] = n0[7:0]+n1[7:0] ;
// Add lsb first - s00_lsb[7] is the carry
assign s01_lsb[8:0] = n2[7:0]+n3[7:0] ;
// n0-n7 lsb need not be registered since addition is already carried out here.
assign s02_lsb[8:0] = n4[7:0]+n5[7:0] ;
assign s03_lsb[8:0] = n6[7:0]+n7[7:0] ;
always @ (posedge clk)
// Pipeline 1: clk (1). Register msb to continue
// addition of msb.
begin
n0_reg1[13:8] <= n0[13:8] ;
// Preserve all inputs for msb addition during the clk(2).
n1_reg1[13:8] <= n1[13:8] ;
n2_reg1[13:8] <= n2[13:8] ;
n3_reg1[13:8] <= n3[13:8] ;
n4_reg1[13:8] <= n4[13:8] ;
n5_reg1[13:8] <= n5[13:8] ;
n6_reg1[13:8] <= n6[13:8] ;
n7_reg1[13:8] <= n7[13:8] ;
s00_lsbreg1[8:0] <= s00_lsb[8:0] ;
// Preserve all lsb sum. s00_lsbreg1[7] is the registered carry from lsb addition.
s01_lsbreg1[8:0] <= s01_lsb[8:0] ;
s02_lsbreg1[8:0] <= s02_lsb[8:0] ;
s03_lsbreg1[8:0] <= s03_lsb[8:0] ;
 end
// Sign extended & msb added with carry.
assign s00_msb[7:0] = {n0_reg1[13], n0_reg1[13:8]}+{n1_reg1[13],
n1_reg1[13:8]}+s00_lsbreg1[8];//s00_msb[6] is ignored.
assign s01_msb[7:0] = {n2_reg1[13], n2_reg1[13:8]}+{n3_reg1[13],
n3_reg1[13:8]}+s01_lsbreg1[8];
assign s02_msb[7:0] = {n4_reg1[13], n4_reg1[13:8]}+{n5_reg1[13],
n5_reg1[13:8]}+s02_lsbreg1[8];
assign s03_msb[7:0] = {n6_reg1[13], n6_reg1[13:8]}+{n7_reg1[13],
n7_reg1[13:8]}+s03_lsbreg1[8];
always @ (posedge clk)
// Pipeline 2: clk (2). Register msb to continue addition of msb.
begin
s00_msbreg2[7:0] <= s00_msb[7:0] ; // Preserve all msb sum.
s01_msbreg2[7:0] <= s01_msb[7:0] ;
s02_msbreg2[7:0] <= s02_msb[7:0] ;
s03_msbreg2[7:0] <= s03_msb[7:0] ;

s00_lsbreg2[8:0] <= s00_lsbreg1[8:0] ; // Preserve all lsb sum.

s01_lsbreg2[8:0] <= s01_lsbreg1[8:0] ;
s02_lsbreg2[8:0] <= s02_lsbreg1[8:0] ;
s03_lsbreg2[8:0] <= s03_lsbreg1[8:0] ;
end

// Second Stage Addition

assign s10_lsb[9:0] = s00_lsbreg2[8:0]+s01_lsbreg2[8:0] ;
//Add lsb first : s10_lsb[7] is the carry.
assign s11_lsb[9:0] = s02_lsbreg2[8:0] +s03_lsbreg2[8:0] ;
//s00, s01 lsbs need not be registered
//since addition is already carried out here.
always @ (posedge clk)
// Pipeline 3: clk (3). Register msb to continue addition of msb.
begin
s10_lsbreg3[9:0] <= s10_lsb[9:0] ; // Preserve all lsb
sum.
s11_lsbreg3[9:0] <= s11_lsb[9:0] ;

s00_msbreg3[7:0] <= s00_msbreg2[7:0]; //

Preserve all msb sum.
s01_msbreg3[7:0] <= s01_msbreg2[7:0] ;
s02_msbreg3[7:0] <= s02_msbreg2[7:0] ;
s03_msbreg3[7:0] <= s03_msbreg2[7:0] ;
end

assign s10_msb[8:0] = {s00_msbreg3[7],s00_msbreg3[7:0]}+

{s01_msbreg3[7],s01_msbreg3[7:0]}+s10_lsbreg3[9] ;
// Add MSB of second stage with sign extension and carry in
from LSB.
// s10_msb[7] is ignored.
assign s11_msb[8:0] = {s02_msbreg3[7], s02_msbreg3[7:0]}+
{s03_msbreg3[7], s03_msbreg3[7:0]}+s11_lsbreg3[9] ;
 always @ (posedge clk)
// Pipeline 4: clk (4). Register msb to continue addition of msb.
begin
s10_lsbreg4[9:0] <= s10_lsbreg3[9:0] ; // Preserve all lsb
sum.
s11_lsbreg4[9:0] <= s11_lsbreg3[9:0] ;

s10_msbreg4[8:0] <= s10_msb[8:0] ; // Preserve all msb

sum.
s11_msbreg4[8:0] <= s11_msb[8:0] ;
end

// Third Stage Addition

assign s20_lsb[10:0] =
s10_lsbreg4[9:0]+ s11_lsbreg4[9:0] ;
//Add lsb first : s20_lsb[7] is the carry.
always @ (posedge clk)
// Pipeline 5: clk (5). Register msb to
continue addition of msb.
begin
s10_msbreg5[8:0] <=
s10_msbreg4[8:0]; //Preserve all msb sum.
s11_msbreg5[8:0] <=
s11_msbreg4[8:0] ;
s20_lsbreg5cy <=
s20_lsb[10]; // Preserve all lsb sum.
s20_lsbreg5[9:0] <=
s20_lsb[9:0];
end
// Add third stage MSB results and
concatenate
// with LSB result to get the final result.
assign sum[19:0] = {({s10_msbreg5[8],
s10_msbreg5[8:0]}+{s11_msbreg5[8], s11_msbreg5[8:0]}+s20_lsbreg5cy), s20_lsbreg5[9:0]};
endmodule

*******************************************************************
module dctreg28(din, cnt, qr0, qr1, qr2, qr3, qr4, qr5, qr6, qr7,en,clk);
input [10:0] din;
input [2:0] cnt;
input en;
input clk;
output [10:0] qr0;
output [10:0] qr1;
output [10:0] qr2;
output [10:0] qr3;
output [10:0] qr4;
output [10:0] qr5;
output [10:0] qr6;
 output [10:0] qr7;
reg [10:0] qr0;
reg [10:0] qr1;
reg [10:0] qr2;
reg [10:0] qr3;
reg [10:0] qr4;
reg [10:0] qr5;
reg [10:0] qr6;
reg [10:0] qr7;

reg [10:0] q0;

reg [10:0] q1;
reg [10:0] q2;
reg [10:0] q3;
reg [10:0] q4;
reg [10:0] q5;
reg [10:0] q6;
reg [10:0] q7;
always@(posedge clk)
begin
if(en==1'b1)
begin
case(cnt)

3'b000: q0=din;
3'b001: q1=din;
3'b010: q2=din;
3'b011: q3=din;
3'b100: q4=din;
3'b101: q5=din;
3'b110: q6=din;
3'b111:
begin
q7=din;
qr0=q0;
qr1=q1;
qr2=q2;
qr3=q3;
qr4=q4;
qr5=q5;
qr6=q6;
qr7=q7;
end
endcase
end
end

endmodule

*************************************************************
module mul11x8(a, b, clk, pro,sum21temp,sum21);

input [10:0] a;
input [7:0] b;
input clk;

output [18:0]sum21temp;
output [18:0] pro;
output [18:0]sum21;

reg [10:0]p0;
reg [10:0]p1;
reg [10:0]p2;
reg [10:0]p3;
reg [10:0]p4;
reg [10:0]p5;
reg [10:0]p6;
reg [10:0]p7;

reg [12:0]sum1;
reg [12:0]sum2;
reg [12:0]sum3;
reg [12:0]sum4;

wire [11:0] p1shift;

wire [11:0] p3shift;

reg [15:0]sum11;
reg [15:0]sum12;

reg [18:0]sum21;

reg [18:0]sum21temp;

reg [11:0]a_mag;
reg [7:0]b_mag;

assign p1shift[11:0]=p1<<1;
assign p3shift[11:0]=p3<<1;

always @(a)
begin
if(a[10] == 1'b0)
a_mag = a[10:0] ;
else
a_mag = ~a[10:0] + 1 ;
end
always@(b)
begin
if(b[7]==1'b0)
 b_mag=b[7:0];
else
b_mag=~b[7:0]+1;
end

always@(posedge clk)
begin

p0[10:0]= a_mag[10:0] &{11{b_mag[0]}};

p1[10:0]= a_mag[10:0] &{11{b_mag[1]}};
p2[10:0]= a_mag[10:0] &{11{b_mag[2]}};
p3[10:0]= a_mag[10:0] &{11{b_mag[3]}};
p4[10:0]= a_mag[10:0] &{11{b_mag[4]}};
p5[10:0]= a_mag[10:0] &{11{b_mag[5]}};
p6[10:0]= a_mag[10:0] &{11{b_mag[6]}};
p7[10:0]= a_mag[10:0] &{11{b_mag[7]}};
end

always@(posedge clk)
begin

//sum1[14:0]={0,p0[10:0]}+{p1[10:0],0};
//sum2[14:0]={0,p2[10:0]}+{p3[10:0],0};
sum1[12:0]=p0[10:0]+p1shift[11:0];
sum2[12:0]=p2[10:0]+p3shift[11:0];
sum3[12:0]=p4[10:0]+{p5[10:0],1'b0};
sum4[12:0]=p6[10:0]+{p7[10:0],1'b0};

end

always@(posedge clk)
begin

sum11[15:0]=sum1[12:0]+{sum2[12:0],1'b0,1'b0};
sum12[15:0]=sum3[12:0]+{sum4[12:0],1'b0,1'b0};

end

always@(posedge clk)
begin
sum21[18:0]=sum11[15:0]+
{sum12[15:0],1'b0,1'b0,1'b0,1'b0};
end

always@(posedge clk)
begin
 if(a[10]==1'b1 && b[7]==1'b0)
begin

sum21temp=~sum21[18:0]+1'b1;
end
else if(a[10]==1'b0 && b[7]==1'b1)
begin

sum21temp=~sum21[18:0]+1'b1;
end
else sum21temp=sum21;
end

assign pro=sum21temp;

endmodule
********************************************************************

module mul12x8(a, b, clk, pro);

input [11:0] a;
input [7:0] b;
input clk;

output [19:0] pro;

reg [11:0]p0;
reg [11:0]p1;
reg [11:0]p2;
reg [11:0]p3;
reg [11:0]p4;
reg [11:0]p5;
reg [11:0]p6;
reg [11:0]p7;

reg [13:0]sum1;
reg [13:0]sum2;
reg [13:0]sum3;
reg [13:0]sum4;

wire [12:0] p1shift;

wire [12:0] p3shift;

reg [16:0]sum11;
reg [16:0]sum12;
reg [19:0]sum21;

reg [19:0]sum21temp;

reg [12:0]a_mag;
reg [7:0]b_mag;

assign p1shift[12:0]=p1<<1;
assign p3shift[12:0]=p3<<1;

always @(a)
begin
if(a[11] == 1'b0)
a_mag = a[11:0] ;
else
a_mag = ~a[11:0] + 1 ;
end

always@(posedge clk)
begin

p0[11:0]= a_mag[11:0] &{12{b[0]}};

p1[11:0]= a_mag[11:0] &{12{b[1]}};
p2[11:0]= a_mag[11:0] &{12{b[2]}};
p3[11:0]= a_mag[11:0] &{12{b[3]}};
p4[11:0]= a_mag[11:0] &{12{b[4]}};
p5[11:0]= a_mag[11:0] &{12{b[5]}};
p6[11:0]= a_mag[11:0] &{12{b[6]}};
p7[11:0]= a_mag[11:0] &{12{b[7]}};
end

always@(posedge clk)
begin

sum1[13:0]=p0[11:0]+{p1[11:0],1'b0};
sum2[13:0]=p2[11:0]+{p3[11:0],1'b0};
sum3[13:0]=p4[11:0]+{p5[11:0],1'b0};
sum4[13:0]=p6[11:0]+{p7[11:0],1'b0};

end

always@(posedge clk)
begin

sum11[16:0]=sum1[13:0]+{sum2[13:0],1'b0,1'b0};
sum12[16:0]=sum3[13:0]+{sum4[13:0],1'b0,1'b0};

end
 always@(posedge clk)
begin
sum21[19:0]=sum11[16:0]+
{sum12[16:0],1'b0,1'b0,1'b0,1'b0};
end

always@(posedge clk)
begin
if(a[10]==1'b1 && (b[7]==1'b0||b[7]==1'b1))
begin

sum21temp=~sum21[19:0]+1'b1;
end

else sum21temp=sum21;
end

assign pro=sum21temp;

endmodule

*********************************************************************

module mult8x8(clk,a, b, pr);

input [7:0] a;
input clk;
input [7:0] b;

output [15:0] pr;

reg[7:0] p0;
reg[7:0] p1;
reg[7:0] p2;
reg[7:0] p3;
reg[7:0] p4;
reg[7:0] p5;
reg[7:0] p6;
reg[7:0] p7;

reg [7:0] b_mag;

reg [9:0] sum01;

reg [9:0] sum02;
reg [9:0] sum03;
reg [9:0] sum04;

reg [12:0] sum11;

reg [12:0] sum12;

reg [15:0] sum21;

reg [15:0] sum21temp;

always @(b)
begin
if(b[7] == 1'b0)
b_mag = b[7:0] ;
else
b_mag = ~b[7:0] + 1 ;
end

always@(posedge clk)
begin

p0[7:0] = a[7:0] & {8{b_mag[0]}};

p1[7:0] = a[7:0] & {8{b_mag[1]}};
p2[7:0] = a[7:0] & {8{b_mag[2]}};
p3[7:0] = a[7:0] & {8{b_mag[3]}};
p4[7:0] = a[7:0] & {8{b_mag[4]}};
p5[7:0] = a[7:0] & {8{b_mag[5]}};
p6[7:0] = a[7:0] & {8{b_mag[6]}};
p7[7:0] = a[7:0] & {8{b_mag[7]}};

end

always@(posedge clk)
begin

sum01[9:0]= p0[7:0] + {p1[7:0],1'b0};

sum02[9:0]= p2[7:0] + {p3[7:0],1'b0};
sum03[9:0]= p4[7:0] + {p5[7:0],1'b0};
sum04[9:0]= p6[7:0] + {p7[7:0],1'b0};
end

always@(posedge clk)
begin

sum11[12:0]=sum01[9:0] + {sum02[9:0],2'b0};
sum12[12:0]=sum03[9:0] + {sum04[9:0],2'b0};

end

always@(posedge clk)
begin
 sum21[15:0]=sum11[12:0] + {sum12[12:0],4'b0};

end

always@(posedge clk)
begin
if ((a[7]==1'b0||a[7]==1'b1) &&( b[7]==1'b1))
begin
sum21temp=~sum21[15:0]+1'b1;
end

else
sum21temp=sum21;
end

assign pr[15:0]=sum21temp[15:0];
endmodule
************************************************************