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Intel I860 Processor Architecture Word

The Intel i860 was a RISC microprocessor introduced in 1989 that combined unique features like a very long instruction word (VLIW) architecture and powerful floating point support. It had a 32-bit ALU and 64-bit floating point unit (FPU) with separate pipelines that could process up to three operations per clock cycle. However, its performance suffered in general applications due to difficulties with compiler optimization and slow context switching times.

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2K views

Intel I860 Processor Architecture Word

The Intel i860 was a RISC microprocessor introduced in 1989 that combined unique features like a very long instruction word (VLIW) architecture and powerful floating point support. It had a 32-bit ALU and 64-bit floating point unit (FPU) with separate pipelines that could process up to three operations per clock cycle. However, its performance suffered in general applications due to difficulties with compiler optimization and slow context switching times.

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© © All Rights Reserved
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INTEL i860 PROCESSOR ARCHITECTURE

INTRODUCTION
The Intel i860 (also known as 80860) was a RISC microprocessor design introduced by Intel in
1989. It was one of Intel's first attempts at an entirely new, high-end instruction set architecture .

Intel i860

Designer

Intel

Bits

32/64-bit

Introduced

1989

Design

RISC, VLIW

Type

Register-Register

Encoding

Fixed

Branching

Compare and branch

Endianness

Bi

Page size

4 KiB

Extensions

64-bit graphics unit

Registers

General purpose

32 32-bit

Floating point

32 32-bit (16 64-bit)

Implementation
The first implementation of the i860 architecture was the i860 XR microprocessor (code
named N10), which ran at 25, 33, or 40 MHz. The second-generation i860 XP microprocessor
(code named N11) added 4 Mbyte pages, larger on-chip caches, second level cache support,
faster buses, and hardware support for bus snooping, for cache consistency
in multiprocessor systems.

Intel i860 XR microprocessor (33 MHz edition)

Produced

From 1989 to mid-1990s

Intel

Common manufacturer(s)

Max. CPU clock rate

25 MHz to 40 MHz

Instruction set

Intel i860

Cores

L1 cache

4 KB (I) + 8 KB (D)

Successor

i860 XP

i860 XP

Intel i860 microprocessor (50 MHz edition)

Produced

From 1991 to mid-1990s

Intel

Common manufacturer(s)

Max. CPU clock rate

40 MHz to 50 MHz

Instruction set

Intel i860

Cores

L1 cache

16+16 KB

Predecessor

i860 XR

Technical feature
1.) The i860 combined a number of features that were unique at the time, most notably
its very long instruction word (VLIW) architecture and powerful support for high-speed
floating point operations.
2.)

The design mounted a 32-bit ALU "Core" along with a64-bit FPU that was itself built in three
parts: an adder, a multiplier, and a graphics processor. The system had separate pipelines for
the ALU, floating point adder and multiplier, and could hand off up to three operations per clock.

(I.e., two instructions - one integer instruction and one floating point multiply-and-accumulate
instruction per clycle.

3.)One unusual feature of the i860 was that the pipelines into the functional units were programaccessible (VLIW), requiring the compilers to order instructions carefully in the object code to
keep the pipelines filled. In traditional architectures these duties were handled at runtime by a
scheduler on the CPU itself, but the complexity of these systems limited their application in early
RISC designs. The i860 was an attempt to avoid this entirely by moving this duty off-chip into
the compiler. This allowed the i860 to devote more room to functional units, improving
performance. As a result of its architecture, the i860 could run certain graphics and floating point
algorithms with exceptionally high speed, but its performance in general-purpose applications
suffered and it was difficult to program efficiently.

Performance
Some performance of intel i860 processor architecture are as follow;

Some problem related to performance of intel i860 processor


architecture are-

1.) One problem, perhaps unrecognized at the time, was that runtime code paths are difficult
to predict, meaning that it becomes exceedingly difficult to order instructions properly
at compile time. For instance, an instruction to add two numbers will take considerably
longer if the data are not in the cache, yet there is no way for the programmer to know if
they are or not. If an incorrect guess is made, the entire pipeline will stall, waiting for the
data. The entire i860 design was based on the compiler efficiently handling this task, which
proved almost impossible in practice. While theoretically capable of peaking at about 60-80
MFLOPS for both single precision and double precision for the XP versions,[5] handcoded assemblers managed to get only about up to 40 MFLOPS, and most compilers had
difficulty getting even 10 MFLOPs. The later Itanium architecture, also a VLIW design,
suffered again from the problem of compilers incapable of delivering optimized (enough)
code.
2.) Another serious problem was the lack of any solution to handle context switching quickly.
The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill
them and require them all to be re-loaded. This took 62 cycles in the best case, and
almost 2000 cycles in the worst. The latter is 1/20000th of a second at 40 MHz (50
microseconds), an eternity for a CPU. This largely eliminated the i860 as a general
purpose CPU.

APPLICATION

INTERNAL ARCHITECTURE

PAGING UNIT

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