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B.E./B.Tech. Degree Examination, Novembewdecember 2007

This document provides information about a digital electronics exam for third semester electronics and communication engineering students. It contains two parts - Part A with 10 multiple choice questions worth 2 marks each, and Part B with 2 questions worth 16 marks each. Part A questions cover topics like binary, octal, hexadecimal conversions, logic expressions, logic diagrams, flip flops, and programmable logic devices. Part B questions involve implementing logic functions using gates, designing counters and sequential circuits, hazards, and memories. Students have to answer all questions in three hours for a total of 100 marks.

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33 views

B.E./B.Tech. Degree Examination, Novembewdecember 2007

This document provides information about a digital electronics exam for third semester electronics and communication engineering students. It contains two parts - Part A with 10 multiple choice questions worth 2 marks each, and Part B with 2 questions worth 16 marks each. Part A questions cover topics like binary, octal, hexadecimal conversions, logic expressions, logic diagrams, flip flops, and programmable logic devices. Part B questions involve implementing logic functions using gates, designing counters and sequential circuits, hazards, and memories. Students have to answer all questions in three hours for a total of 100 marks.

Uploaded by

vsalaiselvam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Reg. No.

H-3282
B.E./B.Tech.
DEGREEEXAMINATION,NOVEMBEWDECEMBER
2007.
Third Semester
(Regulation 2004)
Electronics and Communication Engineering
EC 1201- DIGITAL ELECTRONICS

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(Common to B.E. Part Time SecondSemester Regulation 2005)


Time : Three hours

Maximum : 100 marks

N.

Answer ALL questions.

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va

PARTA-(fOx2=20marks)

Convert (O.SfS)roto octal.

2.

ExpressF = A + B'C as sum of minterms.

3.

Draw the logic diagram for X = AB + B'C.

4.

Implement F = (AB' + A'B) (C + D') with only NOR gates.

5.

What is a Moore machine?

6.

Give the characteristic expressionof a JK Flip Flop.

7.

What is a flow table?

8..

What is Race?

9.

Draw the logic diagram of a memory cell.

10.

What is a combinational PLD?

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w.

1.

PARTB-(5x16=80marks)
11. (a)

(i)

Convert the binary number 0.1100 to its equivalent decimal


(4)
number.

(ii)

convert the number 326, to its equivalent decimal number.

(iii)

Convert the foliowing binary number to its hexadecimal equivalent


(4)
1111110000.

(iv)

Convert 2497.50rcto its octal equivalent.

@)

(4)

Or
(b)

(i)

Simplify the following using Kmap.


(4)

(ii)

Convert SOP to equivalentPOS-

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X = A'B + A'B'C + ABC' + AB'C'

(4)

A'B'C + A'B'C + A'BC + AB'C + ABC'

Apply Demorgan's theorem to the following expression.

N.

(iii)

(4)

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((A+B+C)D)'

(iv) using BooleanLaws and rules simplify the logic expression.

(i)

Impiement Full adder using two half adders.

(8)

(ii)

Draw and explain the BCD adder circuit.

(8)

(a)

ft)

Or

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w.

12.

@)

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Z = (A'+ B) (A + B).

(i)

(ii)

Implement the Booiean expression using gates

X=(AB+C)'D+E.

@)

Draw the logic syrnbol of a XNOR gate and give its truth table.

G)

(iii) Sketh a NAND-NAND logic circuit for the Boolean expression.


(8)
Y = AB'+ AC + BD.
18.

(a)

Design a 3 bit binary counter using T flip flop that has a repeated
sequenceof six states.000 - 001 - 010 - 100 - 101 - 110.Give the state
(16)
table, state diagram and logic diagram.
Or
2

R 3282

(b)

Design the sequential circuit whose state table is given as

(16)

Presentstate lnput Next state Output


xArA2

00

000

00

101

01

001

01

100

Az

Ar

010

101

011

100

what areHazards? Explain in detail with a suitable example.

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14. (a)

Or

Implication table.

Write short notes on :


RAM.

(ii)

Types of ROM's.

(i)

w.

(a)

ft)

(16)

(8)
(8)

Or

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15.

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N.

The circuit has two inputs T (toggle) and C (Clock) and one output Q. The
output state is complemented if T = 1 and clock c changes from 1 to 0
(negative edge triggering) otherwise, under any other input condition, the
output Q remains unchanged. Derive the Primitive flow table and

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na

(b)

(16)

Implement the following two Boolean functions with a PI"A.


F r ( A , B , C ) = > , ( 0 ,1 , 2 , 4 )
F z( A , B , C ) = L ( 0 , 5 , 6 , 7 )

(16)

R 3282

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