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16-Bit ALU Using FPGA: Advanced Logic Circuits and Switching Theory

1) The document proposes building a 16-bit arithmetic logic unit (ALU) using an FPGA that can perform arithmetic operations like addition and subtraction, as well as logic operations like AND, OR, and XOR. 2) The ALU will be split into three modules - arithmetic, logic, and carry - that can be combined to build a 32-bit ALU using selection lines. 3) The project aims to code the ALU design in Verilog and synthesize it on an FPGA board to demonstrate its functionality through the FPGA's input/output components.

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55 views3 pages

16-Bit ALU Using FPGA: Advanced Logic Circuits and Switching Theory

1) The document proposes building a 16-bit arithmetic logic unit (ALU) using an FPGA that can perform arithmetic operations like addition and subtraction, as well as logic operations like AND, OR, and XOR. 2) The ALU will be split into three modules - arithmetic, logic, and carry - that can be combined to build a 32-bit ALU using selection lines. 3) The project aims to code the ALU design in Verilog and synthesize it on an FPGA board to demonstrate its functionality through the FPGA's input/output components.

Uploaded by

mary_nailyn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ADVANCED LOGIC CIRCUITS AND SWITCHING THEORY

16-bit ALU using FPGA


Proposal

Name: Tan, Hannah Kay R.


Course/Section: COE118L/B1
Group No:
Date of Submission: June 1, 2015
Engr. Jose B. Lazaro
Professor

BACKGROUND OF THE PROTOTYPE:


An arithmetic logic unit (ALU) is a digital electronic circuit that
performs arithmetic and bitwise logical operations on integer binary
numbers. It is a fundamental building block of the central processing
unit (CPU) found in many computers.
The ALU takes as input the data to be operated on (called
operands) and a code from the control unit indicating which operation
to perform. The output is the result of the computation.
The ALU implemented will perform the following operations:
Arithmetic operations:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Addition with carry
6. Subtraction with borrow
Logic operations
1. AND
2. NOT
3. OR
4. NAND
5. NOR
6. EX-OR
7. EX-NOR
The ALU will be split into three modules, one Arithmetic, one Logic
and one Carry module. These three modules can be combined to build
a 32-bit ALU with the use of selection line.
The table for the required specifications of ALU is as following:
S3
0
0
0
0
0
0

S2
S0
0
0
0
0
1
1

S1
0
0
1
1
0
0

0
1
0
1
0
1

OPERATIONS

FUNCTION

A+B
A+B+1
A+1
A-1
B+1
B-1

ADDITION
SUBTRACTION
INCREMENT A
DECREMENT A
INCREMENT B
DECREMENT B

A+B+1

A+B

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

NOT A
NOT B
A AND B
A OR B
A NAND B
A NOR B
A XOR B
NOT(A XOR B)

ADDITION WITH
CARRY
SUBTRACTION
WITH BOOROW
NOT A
NOT B
A AND B
A OR B
A NAND B
A NOR B
A EX-OR B
A EX-NOR B

The prototype would make use of logic gates, registers, and states.
The code will be coded using Verilog and synthesized in the FPGA
board and the project shall run on the FPGAs I/O components.

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