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VHDL 1-bit and 2-bit Comparators

The document describes VHDL code for 1-bit and 2-bit comparators. The 1-bit comparator entity named COMP1 compares two 1-bit inputs A and B and outputs whether A is greater than, equal to, or less than B. The 2-bit comparator entity named COMP2 compares two 2-bit inputs A and B and outputs the same comparisons. Both comparators use if/else statements in a process to evaluate the inputs and assign the appropriate output signals.

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José Torres
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51 views1 page

VHDL 1-bit and 2-bit Comparators

The document describes VHDL code for 1-bit and 2-bit comparators. The 1-bit comparator entity named COMP1 compares two 1-bit inputs A and B and outputs whether A is greater than, equal to, or less than B. The 2-bit comparator entity named COMP2 compares two 2-bit inputs A and B and outputs the same comparisons. Both comparators use if/else statements in a process to evaluate the inputs and assign the appropriate output signals.

Uploaded by

José Torres
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL

Comparadores:
Comparador 1 bit:
library IEEE;
use IEEE.std_logic_1164.all;
entity COMP1 is
port(
A: in std_logic;
B: in std_logic;
A_mayor_B : out std_logic;
A_igual_B : out std_logic;
A_menor_B : out std_logic);
end COMP1;

Comparador 2 bits
library IEEE;
use IEEE.std_logic_1164.all;
entity COMP2 is
port(
A: in std_logic_vector(1 downto 0);
B: in std_logic_vector(1 downto 0);
A_igual_B: out
std_logic;
A_mayor_B: out
std_logic;
A_menor_B: out
std_logic);
end COMP2;

architecture arch1 of COMP1 is


begin
process (A,B)
begin
if A=B then
A_igual_B <= '1';
A_mayor_B <='0';
A_menor_B <='0';
elsif (A='1') and (B='0') then
A_igual_B <= '0';
A_mayor_B <='1';
A_menor_B <='0';
elsif (A='0') and (B='1') then
A_igual_B <= '0';
A_mayor_B <='0';
A_menor_B <='1';
end if;
end process;
end arch1;

architecture arch1 of COMP2 is


begin
process (A,B) begin
if (A(1)=B(1)) and (A(0)=B(0)) then
A_igual_B <='1';
A_mayor_B <='0';
A_menor_B <='0';
elsif (A(1)='1') and (B(1)='0') then
A_mayor_B <='1';
A_igual_B <='0';
A_menor_B <='0';
elsif (A(1)='0') and (B(1)='1') then
A_menor_B <='1';
A_mayor_B <='0';
A_igual_B <='0';
elsif (A(0)='1') and (B(0)='0') then
A_mayor_B <='1';
A_igual_B <='0';
A_menor_B <='0';
elsif (A(0)='0') and (B(0)='1') then
A_menor_B <='1';
A_mayor_B <='0';
A_igual_B <='0';
end if;
end process;
end arch1;

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