Course objectives

To understand the basic building blocks of a computer

system and the role of the central processing unit.

To analyze the various ways by which a CPU does its
functions.
To learn how to access the services performed by the
8086 CPU, with the use of assembly language
programming.
To learn how a CPU can be used along with external
devices.
To learn how to design appliances for human interface
and usage.

 Grading policy : Relative grading

Cut off marks for S grade 85

minimum Cut off marks for R grade = 30
Evaluation

T1 = 15 %

T2 = 15 %

End exam = 50%

Assignment, class performance = 20%

(At least 10 % for programming test)

 Note :
1.

Except for genuine cases, make up exams and late

submission of assignments are not allowed.

2. Any mistake in the marks or result should be

informed with in 3 days after the results are

published.
3. Minimum 80% attendance is required.

Syllabus
Module 1 (5 hours)

Introduction: History of microprocessors Basics of

computer architecture- Computer languages CISC and
RISC-Review of binary arithmetic.
Module 2 (15 hours)
Intel 8086 processor: The architecture of 8086 use of
MASM Programming concepts- Programming using
instructions for data transfer ,arithmetic, logical and
shift and rotate operations, String manipulations
Procedures-Macros-ASCII operations-high level
language constructs I/O instructionsModular
programming

Syllabus
Module 3 (12 hours)

Hardware and Interfacing: The pin configuration, clock

and power on reset of 8086- minimum and maximum
modes. Interfacing chips- PPI 8255 -Timer8253/54
Keyboard Display Interface 8279-DMA Controller 8237Programmable Interrupt Controller 8259
Module 4 (10 hours)
Intel 8051 microcontroller: architecture ports, timers,
interrupts, serial data transmission instruction set programming
6

1. MICROPROCESSOR
A processor on a single microchip.
A 16-bit microprocessor can process data and

memory addresses that are represented by 16 bits at a

time.
A 16-bit bus transmits 16 bits in parallel.

 Intel 4004 4 bit processor, clock speed of 108 KHz &

2,300 transistors with ports for ROM,RAM & I/O.

8008 8 bit version of the 4004.
8080 8 bit processor, 16 bit address bus.
8085 8 bit processor, 16 bit address bus.
Microprocessor manufacturing companies
Intel, AMD, zilog, motorola( now freescale)etc.
8

YEAR OF RELEASE OF x86

PROCESSORS Table 0.1
x86 processor

Year of release

8086
(16 bit)
8088
(16 bit, 8 bit external data bus)
80186
80286
80386
(32 bit)
80486
Pentium (64 bit)
Pentium Pro
Pentium -2
Pentium-3
Pentium-4
Pentium-D
Core-2

1978
1979
1982
1982
1985
1989
1993
1995
1997
1999
2004
2005
2006

Core-2 Quad

2007
9

PERSONAL COMPUTERS
IBM produced the first PC in August 1981 using the

8088.
It had 64 KB of RAM (expandable to 256 KB), a floppy
disk drive
In March 1983 ,the IBM PC XT was released-it had a
hard disk
In August 1984 ,the PC-AT using the 80286 was
released .

10

2.COMPUTER ARCHITECTURE BASICS

A computer has
a CPU
Memory
I/O
all are interconnected through a system bus

11

The block diagram of a computer-Fig 0.3

12

13

 The CPU is usually a microprocessor.

CPU processes data according to the programs meant

to operate on specific data.

Program set of instructions.
CPU decodes this instructions, which generates
control signals necessary to activate the ALU.
All these activities are timed and synchronized by a
pulse train of fixed frequency clock signal.
Clock signal synchronizing the activity of the CPU
with the activity on the bus.

14

SYSTEM BUS
Bus collection of signal wires which connect between

the components of the computer system.

CPU is connected to the memory as well as I/O
through the system bus , but only one at a time.
There is only one system bus.
The system bus comprises of

Data bus
Address bus
Control bus

15

SYSTEM BUS COMPONENTS

-Fig 0.4

16

DATA BUS
Used to transfer data.
bi-directional
Data has to be sent from the CPU to memory and I/O.
Data has to be received by the CPU.

Width of data bus determines,

Data transfer rate.
Size of internal registers of CPU.
Processing capability of CPU.
8086 can process data of 16 bits at a time (data bus width of
8086 is 16 bits).
17

ADDRESS BUS
Address bus width determines
Maximum size of physical memory that the CPU can

access.

When a memory location is to be accessed, the

corresponding address is placed on the address bus by

the CPU.
I/O devices also have addresses.
In both cases, CPU supplies the address .
Unidirectional
8086 address bus width is 20 bits
It can address 2 20 different locations.
It can use memory size of 2 20 bytes = 1 MB
18

CONTROL BUS
Set of control signals for activities like writing /
reading to/ from memory / I/O devices or special
activities of the CPU like interrupts and DMA.
Signals travelling in either directions and some signals
may be bi-directional.
Memory read signal will be asserted for reading from
memory. It is sent to memory from the processor.
Interrupt is received by the processor from an I/O
devices.

19

PROCESSOR
Component responsible for controlling all the

activities of the system.

It performs 3 actions continuously & infinitely,
Fetch an instruction from memory.
Decode the instruction.
Execution cycle
Execute the instruction.

20

PROCESSOR ACTIVITY Fig 0.5

21

SYSTEM CLOCK
All the activities of the processor and buses are

synchronized by a clock square wave with particular

frequency.
Clock period T = 1/f , f clock frequency.
Execution cycle may require many clock periods,
depends on
Architectural features of processor.
Complexity of the instructions to be executed.

Time for execution depends on the clock speed.

Clock speed of 3 GHz implies faster processing than

a clock of 1 GHz.

22

SYSTEM CLOCK Fig 0.6

23

Memory
Primary or main memory
RAM ( random access memory)
ROM ( read only memory )
Secondary memory
Hard disk
Optical disk
Memory organized as bytes.
Memory capacity number of bytes it can store.
Eg: 1 KB, 1 MB
24

Memory
Two basic operations associated with memory
Read

Data stored in a memory location to be transferred to the CPU

without erasing the content in memory.

Write

New data to be placed in a memory location. ( it over writes

the previous value)

Access time
Time required for these operations
25

Memory and associated control

signals -Fig 0.7

26

MEMORY READ CYCLE-STEPS

Place on the address bus, the address of the memory

location whose content is to be read .This action is

performed by the processor.
Assert the memory read signal which is part of the control
bus.
Wait until the content of the addressed location appears on
the data bus.
Transfer the data on the data bus to the processor.
De-activate the memory read signal .The memory read
operation is over and the address on the address bus is not
relevant anymore
27

MEMORY WRITE CYCLE-STEPS

Place on the address bus ,the address of the location to

which data is to be written.

On the data bus, place the data to be written.
Assert the memory write signal which is part of the
control bus.
Wait until the data is stored in the addressed location.
De-activate the memory write signal .This ends the
memory write operation.

28

The I/O system

Computer needs peripherals to communicate with the

outside world.
It is difficult for a processor to deal directly with I/O
devices.
Processor does not have the necessary control signals
to deal with different peripherals.
Each peripheral have controller which acts as an
interface between the peripheral and the processor.
Eg: keyboard display interfacing chip, parallel port

interfacing chip & serial communication chip.

29

Figure 0.8 The I/O system

30

3. COMPUTER LANGUAGES
High Level Language
Eg: c, c++, java

compiler
Assembly Language

assembler

Machine Language
31

High Level Language

Vocabulary and grammar similar to the language

spoken by us.
Easy to understand and write.
Not processor specific.

32

Assembly Language
Uses mnemonics for specifying the operation the

computer is to perform.
Mnemonics are direct translation of the machine code
to a symbol.
Eg: for addition
: ADD
for multiplication : MUL
Mnemonics depends on processor type , but related to
the operation.
Assembler converts assembly language to machine
language.
33

Machine Language
Consists of binary ones and zeros.
One binary code for addition , another one for

subtraction.
These operation codes are called opcodes.
Each processor has its own machine language and
assembly language.
Assembly language to machine language translation
and vice versa is a one to one process.

34

4.RISC and CISC

CISC ( Complex Instruction Set Computer )
Complex instructions implemented fully using hardware.
Eg : multiply instruction needs a dedicated hardware.
Hardware is fast, execution is fast.
Hardware budget is high.
Examples For CISC : x86.

35

 RISC (Reduced Instruction Set Computer)

Realize a complex instruction using a set of simple

instructions.
Hardware budget is less.
Software is to written to realize complex instructions.
Only simple instructions implemented in a single clock.
Examples for RISC : ARM ,Suns Sparc processors
36

5.NUMBER SYSTEMS
Decimal
Binary
Hexa decimal
Binary Coded Decimal (BCD)-packed and unpacked
Conversions between them is possible

Arithmetic operations using all these number systems

is possible.

37

Number system conversion

a) Find decimal equivalent?

1) 1001.011B = 9.375
2) 240FCH = 147708
3) 25.6H = ?
4) 31.3 H = ?
5) 1100.101B = ?
6) A32.3 H = ?
7) 100101B = ?

38

b) Decimal to binary
- Divide decimal number by 2 repeatedly and save
reminders.
- Write remainders from bottom to top.
- 13 = 1101
- 213 = ?
c) Decimal to hexadecimal
- Divide decimal number by 16 repeatedly and save
reminders.
- Write remainders from bottom to top.
- 225 = ?
39

d) Binary to hexadecimal
- Group binary number into groups of 4 bits.
- 0100 1100 = 4C
- 0101 0111 1111 = ?
e) Hexadecimal to binary
- Take each hexadecimal digit and write its equivalent
four bit binary number.
- 3AF24H = ?

40

f ) BCD numbers
- Binary coded decimal
- Unpacked BCD
- One decimal digit as a byte.
- 9 = 00001001
- 98 = 00001001

00001000
8

- Packed BCD
- One decimal digit is packed into 4 binary bits.
- 98 = 1001 1000
9
8
41

 No BCD nibble( four bits) can have a code greater than

1001.
BCD in hex form
- 1)write the binary equivalent of each decimal number
as a nibble.
- 2) write the hex equivalent of each nibble.
- BCD of decimal number 675 is
-

0110
6

0111

0101

- 675 H represents packed BCD in hex form.

42

 Find the binary, hex and packed BCD representation

of the decimal numbers 126 and 245. Also write the

packed BCD in the hex format?
Number
Binary
Hex
BCD
BCD in hex form

126

245

43

6. ASCII CODE
( American Standard Code for Information Interchange )
It is a 7 bit code, written as a byte.
Used when entering data through the keyboard &

displaying text on the video display.

A = 41h,

0= 30H

Z=54H,
9= 39H

a= 61H

z= 7AH

44

 It has representations for numbers ,lower case and

upper case English alphabets ,special characters like

#,^.& and control characters .
There are ASCII codes for new line, tab & space bar.
When we type a character on the keyboard, it is the

ASCII value of the key that is read in.

Computer converts this form to binary form for

processing.
45

REPRESENTATION OF NEGATIVE NUMBERS

Computers use 2s compliment.

All arithmetic operations can be done in this form.

Unique representation for 0.
MSB for +ve numbers is 0 and for ve number is 1.
Range of numbers represented by n bits is
(-2n-1) to (+2n-1 -1).
46

 Negative numbers

-8
-7
-6
-5
-4
-3
-2
-1
-0
+0
+1

binary
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
0001

hex
8
9
A
B
C
D
E
F
0
0
1
47

7.NUMBERS OF DIFFERENT LENGTHS

When hexadecimal numbers of different lengths are

added ,their length should be made the same ,by sign

extending the number of smaller length
A byte should be extended to a word ,to add the byte to
a word
A word should be extended to a double word ,in order
to add it to a double word

48

8. UNITS OF MEMORY CAPACITY

28 =256 bytes
210=1024 bytes =1KiloByte or 1KB
26 x 210 = 216 =64 KB =65,536 bytes

49

UNITS OF MEMORY CAPACITY

210 x 210 = 220 = one Mega Byte (1MB) =1024 x1024

=1,048,576 bytes

210 x220 = 230 = one Giga Byte (1 GB) = 1024 x1024 x 1024

= 1,073,741,824 bytes

210 x 230 = 240 =one Terra Byte(TB) =1024 x 1024 x1024 x

1024 =1,099,511,627,776
50

UNITS OF MEMORY CAPACITY

Peta Byte (PB) =250 bytes
Exa Byte (EB) =260 bytes
Zetta Byte (ZB) =270 bytes

51

9. THE 8085 MICROPROCESSOR

The 8085 was released by Intel in 1976.
It is a 40 pin DIP(dual inline package)
This chip has 8 data pins and 16 address pins
Data can be read in and out from the chip as 8 bits at a

time
It can have access to memory of 64 KB (maximum)
It has a number of control pins as well.

52

PROGRAMMING MODEL - 8085

53

 The functional block diagram shows an ALU and its

associated blocks
The whole system is controlled by the timing and control
circuit which synchronizes the activities of the processor
with a central clock
All arithmetic and logic computations take place in ALU
Instructions from memory are brought to an instruction
register and decoded by the instruction decoder

54

 Accumulator - an 8-bit register called A and it serves

to hold one of the operands

Flags- register which gives information about the
arithmetic and logic computations
All processors have registers which are used as
temporary storage for operands
General purpose registers 8 bit register s used for
data
Address registers 16 bit registers for holding memory
addresses

55

REGISTERS OF 8085 Figure 0.10

56

GENERAL PURPOSE REGISTERS

All general purpose registers are 8 bit long.
8085 is accumulator based machine.
Mandatory to have the operand/ one of the operand in
the accumulator.
Its name is not written in the instruction.
In other instructions it is notated as A.
But two each of them can be concatenated to form 16

bit registers-like BC ,DE,HL and AF

The first register holds the upper byte and second
register holds the lower byte of 16 bit register
57

PROCESSOR STATUS WORD-Fig 0.11

Processor status word (PSW) A register and flag

register together as a 16 bit register
58

FLAG REGISTER Fig 0.12

59

 Flag register 8 bit register which is a combination of

1 bit flip flops (flag bits)

Zero Flag (Z) If the result of a computation is zero,
this flag is set (z=1), otherwise it is reset
Carry Flag (C) If the operation causes a bit to
overflow from the MSB, this flag is set (c=1), otherwise
it is reset
Sign Flag (S) If the MSB of the result is 1, this flag is
set (S=1); otherwise it is reset
Parity Flag (P) When the result has even parity, this
is set (p=1); otherwise it is reset

Auxiliary Carry Flag (AC)-This flag is set (AC=1)

when there is a carry from D3 to D4 of the result

60

ADDRESS REGISTERS
They are 16 bit long
i) Program counter always points to the address of the

next location
ii) Stack pointer always point to the top of the stack

61

ASSEMBLY LANGUAGE PROGRAMMING

Programs that are written are saved in RAM from

where instruction bytes are fetched one byte at a time

for execution.
The general format for assembly code is
label:

instruction

;comment

Labels are not needed for all lines

Comments are optional
Used to enhance the understandability of the code.

62

ADDRESSING MODES
The way an operand is presented for execution by the

instruction.
Addressing modes are
Register addressing
Direct addressing
Indirect addressing
Immediate addressing

63

 Single operand instruction

Operand will be in a Register or memory.
Double operand instruction
Memory address or register &
Another register.
(at least one of them have to be in register)
General format

MOV destination, source

- Content of the source is copied to the destination.
- Code lines are not case sensitive.
64

ADDRESSING MODES
REGISTER ADDRESSING
In this mode, only registers are involved .Both the

source and destination are registers .

MOV A,B
; copy the contents of B to A
MOV C,A
; copy the contents of A to C
ADD A,H
; add the contents of H and A sum to
be in destination A

65

DIRECT ADDRESSING
In this ,one of the operands is directly addressed i.e,

the operand is in memory and its address is directly

mentioned in the instruction
LDA 0987H
; load accumulator direct-the address
is the 16 bit number 0987H
; the content of this location is copied to the
accumulator (register A)
STA 2345H
; store accumulator direct-the content
of the accumulator is stored in the address 2345H
IN 56H
; copy the data in input port with address
56 H to register A
66

INDIRECT ADDRESSING
Here ,one of the operands is indirectly specified . It is

in memory ,but instead of writing its address directly in

the instruction ,the address is loaded into a 16 bit
register and that register is specified in the instruction.
MOV C, M

;address is in the HL pair-move

content to C

STAX B

; store accumulator direct-store the

content of accumulator in the address
in the BC pair .
67

IMMEDIATE ADDRESSING
Here , the source data is written in the instruction

itself
MOV A,78H
ADD A,67

; copy the number 78H to A

; add the content of A and the number
67. The sum is to be in A
LXI H,3453H ; the immediate number 3453H is
loaded in the HL register pair

68

DATA TRANSFER INSTRUCTIONS

These instructions are responsible for transferring data

between
i) registers ii)register and memory iii) I/O and
accumulator .
These also include instructions for loading an 8 bit or
16 bit number into a register of the same size. For
certain instruction ,the accumulator ( A register) is
implied.

69

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rs

; copy data from Rs(source) to

destination register
MVI Rd, data8
; move 8 bit data to 8 bit register
OUT port address ; send data from accumulator to
output port
IN port address ; take in data from input port to
accumulator
LXI Rp, data16
; load 16 bit data to register pair
MOV R, M
; copy data to register, from
indirectly specified memory
70

DATA TRANSFER INSTRUCTIONS

MOV M,R

; copy data from register , to indirectly

specified memory
LDA address ; load data to accumulator from specified
address
STA address ; store data from accumulator to specified
address
LDAX Rp ; load to accumulator, the data from
memory address specified by the register pair (Rp)
STAX Rp
; store into the memory address specified
by the register pair Rp, the data in the accumulator
71

ARITHMETIC INSTRUCTIONS
For all arithmetic operations, A is implied to contain

one operand(if there are 2 operands)

Add, subtract, increment, decrement and decimal

adjust after addition of BCD.

No instructions for multiplication and division.
All conditional flags are affected.
72

 ADD R

; add the content of R to A sum in A

ADI data8 ; add the immediate data to A-sum in A
ADC R ; add the content of R,A and the carry bit-sum
in A
ADD M ; add the content of indirectly specified
memory to A
SUB R ; subtract from A the data in R-result in A

SUI data8 ; subtract from A the immediate data-result

in A
SBB R ; subtract from A, the content of R and carryresult in A
73

 INR R
DCR R

INR M
DCR M
INX Rp
DCX Rp
DAA

; increment the content of 8bit register R by 1

; decrement the content of 8bit register R by 1
; increment the content of indirectly
specified memory by 1.
; decrement the content of indirectly
specified memory by 1.
; increment the content of register pair by 1
; decrement the content of register pair by 1
; decimal adjust after BCD addition

74

Example 0.22
Bring data from the memory location 4567H ,add
56H to it and store the sum in location 0567H.

75

solution
LDA 4567H
ADI A,56H
STA 0567H

; copy data from 4567H to A.

; add 56H to this sum in A.
; store the content of A in 0567H

76

Example 0.23
Write a program to add an immediate data to a data in

memory address 0987H .Store the sum in the next

address in memory.

77

solution
MVI B, 3CH
LXI H, 0987H
MOV A, M
ADD A, B
INX H
MOV M,A

; load immediate data in B

; load address in the HL register pair
; copy data in address pointed by HL
; add the content of B to A- sum in A.
; increment the content of HL
; store A in address pointed by HL.

78

Example 0.24
There is a byte of data in location 6756H ,which is to

be overwritten by a number which is less than it by 5

.Write the program for it .

79

SOLUTION
LXI B,6756H
LDAX B
SUI 05
STAX B

; load the address of data in the BC pair

; load in A the content pointed by BC
; subtract 05 from A-result in A
; store A in the address pointed by BC

80

BRANCH INSTRUCTIONS
JMP address16 ; jump unconditionally to the given

address
JZ
address16 ; jump on zero- jump to the given
address if Z=1
JNZ address16 ; jump on non-zero-jump to the given
address if Z=0
JC address16 ; jump on carry-jump to the given
address if C=1
JNC address16 ; jump on carry-jump to the given
address if C=0
CALL address16 ; call a subprogram written in the
address given
81

Example 0.25
Write a program for multiplying 24 by 10. Since there

is no multiply instruction for 8085 , multiplication is

achieved by repeated addition. We do it by adding 24
to itself 10 times

82

SOLUTION
MOV A,0

; make the content of A=0

MOV B,10
; load the multiplier (10) in B
AGAIN : ADI,24
; add the multiplicand(24) to A
DCR B
; decrement B
JNZ AGAIN ; check if z(zero flag) is
zero-if so jump to AGAIN
LDA 3400H ; if z=1, store the sum in
address 3400H

83

Example 0.26
Two numbers are stored in memory .Verify if their

sum is greater than 255 .If yes, send the ASCII value of
Y to an output port with address 78H .Other wise send
N.

84

SOLUTON
LXI H, 0897H

; load HL with first address

MOV A, M
; load data from that address to A
MOV B, A
; move that data from A to B
INX H
; increment pointer register pair HL
MOV A, M ; load the second data from memory into A
ADD A, B ; add the content of A and B-sum in A
JC YES ; if C=1 , sum > 255 ;jump to YES
MOV A, N ; if C=0, it means sum < 255, so A = N
JMP XIT ; jump unconditionally to XIT
YES : MOV A, Y ; this is when sum >255. A= Y
XIT : OUT 78 H; send A to output port with address 78H
85

LOGICAL AND BIT MANIPULATION INSTRUCTIONS

ANA R ; logically AND the contents of A and R- result

in A
ANI data8 ; logically AND the contents of A and data
given-result in A
ANA M ; logically AND the contents of A and
memory-result in A
ORA R ; logically OR the contents of A and R- result
in A
ORI data8 ; logically OR the contents of A and data
given-result in A
86

LOGICAL AND BIT MANIPULATION INSTRUCTIONS ORA M ; logically OR the contents of A and

memory-result in A
XRA R ; logically XOR the contents of A and R- result
in A
XRI data8 ; logically XOR the contents of A and data
given-result in A
XRA M ; logically XOR the contents of A and
memory-result in A
CMP R ;compare the contents of A and R-only flags
affected
87

LOGICAL AND BIT MANIPULATION INSTRUCTIONS

CMP M ; compare the contents of A and memory-only

flags affected
CPI data8 ; compare the contents of A and given dataonly flags affected
RLC ; rotate the bits in A once, to the left
RAL ;rotate the bits in A and the carry bit, to the
left,once
RRC ;rotate the bits in A once, to the right
RAR ; rotate the bits in A and the carry bit, to the
right,once
88

COMPARE INSTRUCTION-Table 0.5

CMP destination, source
By subtraction operation and flags are set/reset

according to the result.

If

C flag

Z flag

destination > source

destination < source

destination =source

89

Example 0.27
Compare the number in the memory location 4566H

with the content of B. Send the bigger number to the

output port with address 67H.

90

SOLUTION
LDA 4566H

; load into A, the number in memory

CMP A, B
; compare it to the number in B
JNC YES
; if C=0 , it means that A > B, jump to
YES
MOV A, B
; C=1, means B >A, so copy bigger no to A
YES : OUT 67 H ; send the bigger number to the
output port

91

PIN DIAGRAM OF 8085-Fig 0.13

92

MULTIPLEXED ADDRESS/DATA BUS

To reduce the pin count,

lower address lines carry data also, but not at the

same time (multiplexed) ( AD0 AD7)
De-multiplexing is necessary to separate them
8 bit latch is connected externally & ALE (Address

Latch Enable) acts as clock for the latch.

ALE = 1 , ADDRESS BUS ( A 0 A7)
ALE =0, DATA BUS ( D0 D7)
93

Address and data de-multiplexing-Fig 0.14

94

Read and Write

95

Memory and I/O Read and write signals-Fig 0.15

96

Address, data and control bus-Fig 0.16

97

Power supply & clock

Crystal is connected between pins 1 & 2.
Defines clock frequency for the processor.
An 8MHz crystal is to be connected to get an internal

clock of 4MHz.
Maximum frequency of operation for 8085 is 5MHz.
(crystal of 10 MHz is to be connected)
CLK OUT : from this pin , clock of the processor can
be extracted and used for timing any unit in the s/m.
Vcc = +5v & Vss is ground reference.
98

Reset & ready pins

99

Interrupt
Processor is performing a particular task
If another more important task is to be done, current

task have to be stopped temporarily.

Once the urgent task is finished, the old one can be
resumed.
Means processor have to be interrupted
Peripheral places its interrupt request on a hardware
pin of 8085.
Software interrupt instruction is written to interrupt.
100

101

INTERRUPT PINS OF THE 8085-Table 0.6

Interrupt pins

Interrupt vector

TRAP

0024H

RST 7.5

003CH

RST 6.5

0034H

RST5 .5

002CH
102

FUNCTIONAL BLOCK DIAGRAM-Fig 0.17

103

HOLD AND HLDA

HOLD is for DMA request
HLDA is for DMA request acknowledge
Data transfer between memory and I/O devices.
Data from memory > accumulator > I/O devices
Data can be transferred directly between a memory

and peripheral DMA.

DMA request is placed on the HOLD pin
Processor send acknowledge signal HLDA
Data transfer is over, HOLD request is removed by
peripheral.

104

SID and SOD

SID the pin for inputting data serially
SOD the pin for serial data output

105

end

106

 numbers

-8
-7
-6
-5
-4
-3
-2
-1
-0
+0
+1

binary
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
0001

hex
8
9
A
B
C
D
E
F
0
0
1
107

2s complement
Find 8 bit 2s complement number corresponding to

6?
6 in 8 bit representation : 0000 0 1 1 0
Complement each bit
Add 1 to it

108

 1111 1001 +

1
1111 1010
F
A

; complement
; add 1
; in hex

-6 is FAH (8 bit form)

AH (4 bit )
FFFAH ( 16 bit)

109

Conversion from 2s
complement form
Find the decimal number whose 2s compliment

representation is FAH?
Complement each bit

Add 1

( i.e., find 2s complement )

Find its -ve

110

A
1 1 1 1 1 0 1 0 ; (number)
0000 0 1 0 1 ; complement
0000 0 1 1 0 ; 2s complement
=6

take ve value = -6
FA is the 2s complement representation of -6

111

 Find the decimal number from 2s complement

representation?
1) FFF2H
2) F9H
Answer :
1) -14
2) -7

112

COMPUTER ARITHMETIC -

Addition

1)Addition of Unsigned numbers

Case 1
Binary
Decimal
0101 1001 +
89 +
0110 1001
105
1100 0010
194

Hexadecimal
59H
69H
C2H

Here the sum lies within a value of 255

8bit numbers : 0 to 255
113

Case 2
0111 1000 +
1001 1001
1 0001 0001

120 +
153
273

78H +
99 H
111 H

Here the sum is >the number of bits allotted

The extra bit is called carry.

Carry indicates the insufficiency of the space allotted

for the result

114

2)Addition of Packed BCD Numbers

Case 1
Packed BCD
0100 0101 +
0010 0010
0110 0111

Packed BCD in hex form

45H +
22H
67H

Decimal
45 +
22
67

Upper nibble and lower nibble within 0 to 9

Just like normal decimal addition

115

Case 2
Packed BCD
Packed BCD in hex
0100 0101 +
45H +
0010 0111
27H
0110 1100
6CH
The lower nibble of sum is greater than 9
No BCD digit can have a value > 9
correction
add 6 (0110) to the lower nibble alone
0110 1100 +
6CH +
0000 0 1 1 0
0 6H
0111 0010
72H

Decimal
45 +
27
72

116

 Case 3

Packed BCD
Packed BCD in hex
0111 0110 +
76H +
0110 0010
62H
1101 1000
D8H
Upper nibble of sum > 9
Correction
Add 6 to upper nibble alone
1101 1000 +
D8H +
0110 0000
60H
1 0011 1000
138H
117

Case 4
upper and lower nibbles of sum > 9
add 6 to both nibbles
Packed BCD
1000 1001 +
0111 0010
1111 1011
0110 0110
1 0110 0001

Packed BCD in hex

89H +
72H
FBH
66H
161H

Sum needs more than one byte space

118

3)Addition of Negative Numbers

Add -43 and -56
Take twos complement of both
-43 +
1101 0101 +
-56
1100 1000
-99
1 1001 1101
Ignore the carry
Consider 8 bits of the sum : 1001 1101
The MSB is 1 , so negative number.
Take twos complement of sum ,
answer is 0110 0011 , ie 99
Take ve : decimal number is -99

119

Examples
1) Add +90 and -26
2) Add -120 and +45

Answer
1) 1 0100 0000
2) 1011 0101

120

subtraction
Subtract 56 from 230 ?

decimal
230 56
174

binary
1110 0110 0011 1000
1010 1110

hex
E6H 38H
AEH

For decimal system : borrow 10

binary
: borrow 2
hexadecimal
: borrow 16
121

1) Packed BCD subtraction

subtract 18 from 53 (packed BCD )?

decimal
53 18
35

packed BCD
0101 0011
0001 1000
0011 0101

Each nibble represents decimal number (base is 10)

subtract bigger number from smaller number

borrow 10 (1010) from left.

122

 0101 0011

0001 1000
0100 1101
0001 1000

borrow 1010 from left

(because of borrowing 0101 is now 0100)
( 1010 +
0011
1101

0100 1101 -

0001 1000
0011 0101

result is 35

123

Subtract 56 from 230 ( packed BCD) ?

230-

56
= 174

DECIMAL

ANSWER:
0010 0011 0000

packed BCD

0000 0101 0110

= 0001 0111 0100
124

2) subtraction of signed numbers

change sign of 2nd number
add to the first
65 34 is 65 +(-34)
-ve number : use 2s compliment

Range of 8 bits : -128 to 127

125

Perform subtraction of the following

signed numbers?
1) +26 from +68

ANS : 42

2) +26 from -68

-94

3) -56 from +23

79

4) -56 from -23

33

126

Answer :
1) +26 from +68
68 + (-26)

Decimal
68
is
-26
is

binary
0100 0100 +
1110 0110 ( 2s compliment)
1 0010 1010
Ignore the extra bit
MSB is 0 , the result is +ve [0010 1010 =42]
If MSB is 1 , the result is ve ( take the ve of its 2s
compliment)
127

Overflow into the sign bit

Range of 8 bit numbers : -128 to 127
If we add -100 and -55, result is -155
Both operands are within the allowed range.
Sum is not within the range

1001 1100 +
(-100)
1100 1001
(-55)
1 0110 0101
( ignore extra bit )
MSB is 0 : indicating +ve number
There was an overflow into sign bit
128

Addition of numbers of different

lengths
Data can have different sizes depending on the

processor.
To add / subtract data of different widths.
Processor do not allow addition / subtraction of data

of different widths.

129

 To equalize the size of data involved

Depends on data is signed or unsigned
Unsigned byte is appended with zeros in upper byte.
35H > 0035H
FFH > 00FFH
Signed byte should be sign extended to make it 16

bit.
35H > 0035H
FFH > FFFFH

130

Add unsigned numbers 35H and 7890H?

35H is appended with zeros to make it 0035H

0035H +
7890H
= 78C5H

131

Add the following signed numbers?

1)45H & A87CH
2) A8H & 1045H
3) F5H & B45CH

Solution :
1) A8C1H
2) 1 0FEDH (ignore extra bit)
3) 1 B451H (ignore extra bit)

132

8086 PROCESSOR
The 8086 Processor is a 16 bit processor internally as

well as externally
Its ALU, internal registers and most of its instructions
are designed to work with 16 bit binary words
It has 16 bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a
time
8086 has 20 bit address bus . So 1MB memory
locations

133

 All actions in the processor are synchronized by a

system clock, which provides the basic timing

There is a control unit which provides the control
signals for the overall functioning of the processor
8086 CPU is divided into two independent functional
parts
Bus Interface Unit (BIU)
Execution Unit (EU)
These two interact with each other through the
internal bus
EU Contains ALU, Control unit and registers
BIU is for address calculations, pre fetching
instructions for the queue and sequencing instructions
134

8086-INTERNAL BLOCK DIAGRAM

Simplified Block diagram

EXECUTION UNIT
It contains the arithmetic and logic unit, control unit,

an internal bus, and a few registers

Internal register is actually an on-chip RAM
Some are program visible , while others are not
directly visible to programmers
Internal registers are used as temporary storage for
operands
If the operand is already in a register it takes less time
for the execution of associated instruction
General purpose or scratchpad registers

137

The scratch pad registers

AX (16 bits) -AH and AL (each 8 bit)
BX (16 bits)--BH and BL (each 8 bit)
CX (16 bits) --CH and CL (each 8 bit)
DX (16 bits) --DH and DL (each 8 bit)

REGISTER SET OF 8086