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A Novel High Performance Implemance and Design of 64 Bit MAC Unit& Their Delay Comparision

This document summarizes a seminar presentation on the design and delay comparison of 64-bit MAC units. It discusses the architecture of MAC units including Wallace tree and array multipliers. It also describes Vedic multipliers and how they can reduce delay. The aim is to design a high performance MAC unit for applications like digital signal processing that require fast processing of large amounts of data. Based on delay comparisons, the Vedic multiplier design is concluded to be suitable for 64-bit processors requiring high performance operations on many bits.

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Amarender
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48 views17 pages

A Novel High Performance Implemance and Design of 64 Bit MAC Unit& Their Delay Comparision

This document summarizes a seminar presentation on the design and delay comparison of 64-bit MAC units. It discusses the architecture of MAC units including Wallace tree and array multipliers. It also describes Vedic multipliers and how they can reduce delay. The aim is to design a high performance MAC unit for applications like digital signal processing that require fast processing of large amounts of data. Based on delay comparisons, the Vedic multiplier design is concluded to be suitable for 64-bit processors requiring high performance operations on many bits.

Uploaded by

Amarender
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Seminar on

A Novel High Performance Implemance and


Design of 64 bit MAC Unit& their Delay
Comparision
1. R. AMARENDER REDDY
2. A.SHIVA PRASAD REDDY
3. B.NIRANJAN

Guide:

12621A04G2
:
12621A04C1
:
12621A04C9

Mr. G.Srujan Reddy


Associate professor-ECE

CONTENTS
Aim of the Project
Architecture of MAC
Wallace tree Multiplier
Array Multiplier
Vedic Multiplier
Applications
Advantages
Conclusion

AIM Of the Project: MAC unit is used for high performance digital signal processing systems.
The DSP applications include filtering, convolution, and inner products.
Multiplier-and-accumulator (MAC) for high speed and low-power by adopting
the new SPST implementing approach.
Therefore the functionality of the MAC unit enables high-speed filtering
and other processing typical for DSP applications.

MAC basic architecture: A MAC unit consists of a


multiplier & an accumulator
containing the sum of the
previous successive products.
The MAC inputs are obtained
from the memory location and
given to the multiplier block.

Wallace tree:A Wallace tree is an efficient multiplier implementation of a digital circuit


that multiplies two integers.
Generally in conventional Wallace multipliers many full adders and
half adders are used in their reduction phase

Vedic Multiplier: In Vedic multiplier Partial product generation and addition


are done concurrently.
The proposed Vedic Multiplier is used to reduce Delay.

Procedure of Computing Vedic Multiplication:-

CARRY SAVE ADDER:A carry-save adder is a type of digital adder, used in computer micro
architecture to compute the sum of three or more n-bit numbers in binary. It
differs from other digital adders in that it outputs two numbers of the same
dimensions as the inputs, one which is a sequence of partial sum bits and
another which is a sequence of carry bits.

Carry Save Adder:- (adding 2 numbers)

Applications:1) Digital signal processing (DSP) applications


a. Signal filtering
b. convolution.
c. Decreasing number of inner products.
2) Optical communications.
3) Multimedia image processing.
4) real-time signal processing like audio signal processing, video/image
processing, or large-capacity data processing

Advantages:
The application like optical communication systems which is based on
DSP , require extremely fast processing of huge amount of digital data.

Conclusion:
Since the delay of 64 bit is less, this design can be used in the

system which requires high performance in processors involving large


number of bits of the operation. The MAC unit is designed using
Verilog-HDL.

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