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Timing Ppts

The document provides propagation delays for various components including inverters and flip-flops. It asks to calculate the maximum clock frequency for a given circuit using these delays, and how the frequency would change if ideal clocks were used instead of synchronized clocks.

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Mahesh
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131 views6 pages

Timing Ppts

The document provides propagation delays for various components including inverters and flip-flops. It asks to calculate the maximum clock frequency for a given circuit using these delays, and how the frequency would change if ideal clocks were used instead of synchronized clocks.

Uploaded by

Mahesh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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D1 D2

C1 C2 C3

Delay due to Delay due to Setup Hold


0 – 1 transition 1 – 0 transition Time Time

C1 4.85 4.50
C2 3.35 3.10
C3 2.85 2.65

INV 0.25 0.20

D1 1.65 1.65 0.75 0.40


D2 1.40 1.40 0.65 0.30

For the design shown below, given that the inputs and outputs are synchronized with clock ( - ideal clock i.e.),
and the delays of the various components being provided in the table, find out the maximum applicable clock frequency.
How would the maximum clock frequency vary if ports were associated with ideal clock?
What is the maximum frequency that the following circuit will operate, given the parameters below,
and assuming no wire delay?

D Q D Q

Clock

Parameters:

inverter propagation delays:


LH = 150 picoseconds
HL = 200 picoseconds
flip-flop clock-to-out
LH = 130 picoseconds
HL = 170 picoseconds
flip-flop setup time
LH = 90 picoseconds
HL = 110 picoseconds
flip-flop hold time
LH = -20 picoseconds
HL = -30 picoseconds
clock jitter, cycle-to-cycle = 200 picoseconds
clock jitter, long-term = 250 picoseconds
Consider the above sequential circuit. Assume that
the setup time for the edge-triggered register is
4ns, hold time is 3ns, the contamination delay is
1ns and propagation delay is 4ns. Identify the key
problem with this circuit and propose a solution to
fix it without modifying the clock. Assume that In
is properly setup and held around the clock edge
Will this design work satisfactorily?
Assumptions: thold = tsetup = tclock_out =
tclock_skew = 1ns.
After reset A = 0, B = 1

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