A B C D E

COMPAL CONFIDENTIAL
1
MODEL NAME : Abacus-MT 1

COMPAL P/N :
PCB NO : LA-1682
Revision : 0.2

2 2

Abacus-MT Schematics Document

uFCBGA/uFCPGA NorthWood MT

2003-02-25
3 3

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 1 of 44
A B C D E
 A B C D E

Compal confidential Block Diagram

Model : Abacus-MT

NorthWood-MT
Prescott-MT CPU ITP Port Thermal Sensor
1 Fan Control 1 CPU Bypass uFCPGA CPU ADM1032 Clock Generator 1
+12V page 7 +1.2VP and VID ICS950810
page 7 +CPU_CORE 478pin page 5,6 page 8 +5VS page 6 +3VS page 16

HA#(3..31) HD#(0..63)
Fan Control 2 System Bus
+5VS page 7
400/533 MHz

Mainstream PIRQE# INTEL Memory DDR-DIMM X2

BANK 0, 1, 2, 3
LVDS Connector
on VGA Board Montara-GT BUS(DDR) +2.5V 200/266/333MHz

AGP Conn AGP4X(1.5V) +1.5VS

732 BGA +2.5V
page 17 +2.5V +1.25VS page 13,14,15
TV OUT page 19
+1.25VS
CRT Signal +CPU_CORE page 9,10,11,12
Internal LVDS
CRT Connector Value
page 19
2 2

LVDS Connector HUB LINK 1.5

on M/B Board page 18
+1.5VS
66MHz

+3VS
+3VS 33MHz PCI BUS INTEL 48MHz USB 2.0/1.1 2X USB Ports
+3VALW +3VALW
+5VALW page 34
IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 +1.5VS
(PIRQC,D#,GNT#1,REQ#1) (PIRQB#,GNT#0,REQ#0) (PIRQA#,GNT#2,REQ#2) ICH4-M
+1.5VALW 24.576MHz AC-LINK
+CPU_CORE 421 BGA
Debug Minipci CONN LAN CardBus VCC5REF
ATA100

WIRELESS BCM-4401L & 1394 VCC5REFSUS page 20,21,22

+5VS +3V PCI4510 M DC
+3VS page 28
page 35 +5VS +3V page 24 +3V page 25,26,27 +3VALW
+3V page 31
+3VS
LPC BUS 33MHz Cable
Card Bus IDE HDD IDE AC97 Codec
3
RJ45 1394 CD-ROM
3

page 24 SLOT CONN +5VS +5VS STAC9750 RJ11

page 26 page 25
NS PC87591L +5VDDA
page 23 page 23 page 29 Cable
Embedded
Controller SIDE IRQ15 PIDE IRQ14
+3VS page 32
+3VALW

Power On/Off DC/DC Interface AMP & INT. HeadPhone &

Ext. IO Speaker MIC Jack
Reset & RTC Suspend Touch Pad page 33
+5VALW page 30 +5VDDA page 30
page 34 page 35 LID Switch
Int.KBD
+5VS page 31 page 33
Power Circuit
4 DC/DC LED Indicator BIOS 4

page Connector EC DEBUG +3VALW page 33

36,37,38,39,40,41 +3VALW page 32
page 34
Dell-Compal Confidential
Compal Electronics, Inc.
Title
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 2 of 44
A B C D E
 5 4 3 2 1

Power Managment table

ST2, ST1, ST0 Trip (C0 bit 2:0) +3VS

MHz
+5VS
FSB MEMORY GFX-LOW GFX-HIGH Cfg# Signal +1.5VALW PCB Rev Data
+1.5VS
000 400 266 133 200 0 +3VALW
+1.2VP Bringup-Build 0.1
D 001 400 200 100 200 1 +5VALW +3V SST-Build D
+CPU_CORE
010 400 200 100 133 2 State +12VALW +2.5V
+1.25VS PT-Build
011 400 266 133 266 3 +12V_FAN
100 533 266 133 200 4
ST-Build
101 533 266 133 266 5 S0 ON ON ON
110 533 333 166 266 6
QT-Build
111 400 333 166 250 7 S1 ON ON ON

S3 ON ON OFF

S5 S4/AC ON OFF OFF

S5 S4/AC don't exist OFF OFF OFF

SCHEMATICS VERSION LIST
Ceramic Capacitor Spec Guide:
VERSION ISSUE DATE REMARK
C C
Temperature Characteristics:
Symbol 0 1 2 3 4 5 6 7 Item Function Note
0.0A 12/30/2002 First Release
CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R
1@ Value no TV, 1394,
2@ Mainstream
@ DEPOP
8 9 A B C D E F G

NP0 C0G BJ CH CJ CK SH SJ

H I J

UJ UK SL

Tolerance:
Symbol A B C D F G H J

CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%

B B

K M N P Q V X Z

+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20%

SMBUS Control Table

THERMAL THERMAL VGA Thermal

SOURCE INVERTER BATT SERIAL SENSOR SENSOR SODIMM CLK CHIP MINI PCI LCD
EEPROM (CPU) (LM75) ADM1032

SMB_EC_CK1 PC87591L
SMB_EC_DA1

SMB_EC_CK2 PC87591L
SMB_EC_DA2

SMB_CLK
ICH4-M
SMB_CDATA
A A

LCD_DDCCLK
M-GT Dell-Compal Confidential
LCD_DDCDATA
Compal Electronics, Inc.
Title
Note & Revision
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 3 of 44
5 4 3 2 1
 5 4 3 2 1

PU22
U66
FAN5234 +1.5VALW SUSP# +1.5VS page 35
page 39

+5VALW
D D
U31
+5VS
+5VALW SUSP# page 35
PU8
SHDN# Q6
MAX1632 SIDEPWR +5VSHDD
page 23
page 38
U26
SUSP# +5VDDA
page 29

U70
+3VALW SYSON +3V
page 35

VR_ON
C
+12VALW U20 C

page 36 PU21 SUSP# +3VS

page 35 PU27
AC
LM3485 +12VFANP CM2843 +1.2VP
B+ page 38 page 41

ENLL PU23
Mobile
Battery JP8
page 36
ISL6247 +CPU_CORE
+5VS
page 41

B
+3VS B

SUSP#
PU20 +1.5VS VGA Conn.
ISL6225 +1.25VS 180 pin
+2.5V
page 40 +2.5V +3V
SYSON
+5VALW
+12VALW
B+ page 17

A A

Dell-Compal Confidential
Compal Electronics, Inc.
Title
POWER DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
Date: Tuesday, February 25, 2003 Sheet 4 of 44
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE

D D

AC10
AC12
AC14
AC16
AC18

AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18

AB11
AB13
AB15
AB17
AB19

AE10
AE12
AE14
AE16
AE18
AE20

AF11
AF13
AF15
AF17
AF19

AF21
AC8

AD7
AD9
AA8

AB7
AB9

AE6
AE8

C10
C12
C14
C16
C18
C20

D11
D13
D15
D17
D19
AF2

AF5
AF7
AF9
A10
A12
A14
A16
A18
A20

B11
B13
B15
B17
B19

E10
C8

D7
D9
A8

B7
B9
JCPU1A

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
HA#[3..31] HD#[0..63]
<9> HA#[3..31] HD#[0..63] <9>
HA#3 K2 B21 HD#0
HA#4 A#3 D#0 HD#1
K4 A#4 D#1 B22
HA#5 L6 A23 HD#2
HA#6 A#5 D#2 HD#3
K1 A25
HA#7 L3
A#6
A#7
POWER D#3
D#4 C21 HD#4
HA#8 M6 D22 HD#5
HA#9 A#8 D#5 HD#6
L2 A#9 D#6 B24
HA#10 M3 C23 HD#7
HA#11 A#10 D#7 HD#8
M4 A#11 D#8 C24
HA#12 N1 B25 HD#9
HA#13 A#12 D#9 HD#10
M1 A#13 D#10 G22
HA#14 N2 H21 HD#11
HA#15 A#14 D#11 HD#12
N4 A#15 D#12 C26
HA#16 N5 D23 HD#13
HA#17 A#16 D#13 HD#14
T1 A#17 D#14 J21
HA#18 R2 D25 HD#15
HA#19 A#18 D#15 HD#16
P3 A#19 D#16 H22
HA#20 P4 E24 HD#17
HA#21 R3
A#20
A#21
HOST D#17
D#18 G23 HD#18
HA#22 T2 F23 HD#19

C
HA#23
HA#24
U1
A#22
A#23
ADDR D#19
D#20 F24 HD#20
HD#21 C
P6 A#24 D#21 E25
HA#25 U3 F26 HD#22
HA#26 A#25 D#22 HD#23
T4 A#26 D#23 D26
HA#27 V2 L21 HD#24
HA#28 A#27 D#24 HD#25
R6 A#28 D#25 G26
HA#29 W1 H24 HD#26
HA#30 A#29 D#26 HD#27
T5 A#30 D#27 M21
HA#31 U4 L22 HD#28
V3
W2
Y1
A#31
A#32
A#33
Northwood-MT HOST
D#28
D#29
D#30
J24
K23
H25
HD#29
HD#30
HD#31
A#34 D#31 HD#32
<9> H_REQ#[0..4]
H_REQ#[0..4]

H_REQ#0
AB1 A#35
Prescott-MT ADDR D#32
D#33
D#34
M23
N22
P21
HD#33
HD#34
HD#35
J1 REQ#0 D#35 M24
H_REQ#1 K5 N23 HD#36
H_REQ#2 REQ#1 D#36 HD#37
J4 REQ#2 D#37 M26
H_REQ#3 J3 N26 HD#38
H_REQ#4 REQ#3 D#38 HD#39
H3 REQ#4 D#39 N25
H_ADS# G1 R21 HD#40
<9> H_ADS# ADS# D#40
P24 HD#41
D#41 HD#42
D#42 R25
+CPU_CORE AC1 R24 HD#43
V5
AP#0
AP#1
CONTROL D#43
D#44 T26 HD#44
AA3 T25 HD#45
R284 1 BINIT# D#45
2 56 _0402_1% AC3 IERR# D#46 T22 HD#46
T23 HD#47
R301 1 D#47
2 220_0402_5% D#48 U26 HD#48
H6 U24 HD#49
B <9> H_BREQ0# BR0# D#49 B
D2 U23 HD#50
<9> H_BPRI# BPRI# D#50
G2 V25 HD#51
<9> H_BNR# BNR# D#51
G4 U21 HD#52
<9> H_LOCK# LOCK# D#52
V22 HD#53
D#53 HD#54
V24
<16> CLK_CPU_BCLK
CLK_CPU_BCLK AF22
BCLK0
CLK D#54
D#55 W26 HD#55
CLK_CPU_BCLK# AF23 Y26 HD#56
<16> CLK_CPU_BCLK# BCLK1 D#56
W25 HD#57
D#57 HD#58
CON D#58
D#59
Y23
Y24 HD#59
F3 Y21 HD#60
<9> H_HIT#
E3 TROL
HIT# GND POWER D#60
AA25 HD#61

BOOTSELECT
<9> H_HITM# HITM# D#61
E2 AA22 HD#62
<9> H_DEFER# DEFER# D#62
AA24 HD#63
D#63

VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8

AD1

F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12
FOX_PZ47803-274A-42_Prescott +CPU_CORE

A BOOTSELECT <41> A

NWD: L PSD: H Dell-Compal Confidential

PSD Pull-up internal
Title
Compal Electronics, Inc.
Prescott / P4 uFCPGA (1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Abacus-MT LA-1682
Date: Tuesday, February 25, 2003 Sheet 5 of 44
5 4 3 2 1
 5 4 3 2 1

GND H_SKTOCC# R269 and R317 depop for desktop CPU

1
R267 R269

AE11
AE13
AE15
AE17
AE19
AE22
AE24

AF10
AF12
AF14
AF16
AF18
AF20

AF26
@33_0402_5% H_DPSLPR# 1 0_0402_5%
2

AE7
AE9

C11
C13
C15
C17
C19

C22
C25

D10
D12
D14
D16
D18
D20
D21
D24
AF1

AF6
AF8
H_DPSLP# <10,20>

B10
B12
B14
B16
B18
B20
B23
B26

E11
E13
E15
E17
E19
E23
E26

F10
F12
F14
F16
F18

F22
F25
C2

C5
C7
C9

D3
D6
D8
B4
B8

E1

E4
E7
E9

F2

F5
JCPU1B H_GHI# 1 2 PM_CPUPERF# <21>

2
R317

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128

SKTOCC#
+CPU_CORE 0_0402_5%
H_RS#[0..2]
<9> H_RS#[0..2]
H_RS#0 F1 J26
RS#0 DP#0
1 2H_RESET# H_RS#1 G5 RS#1 DP#1 K25 +H_GTLREF
R279 51_0402_5% H_RS#2 F4 K26
D
1 2ITP_BPM#0 AB2
RS#2
RSP#
GROUND DP#2
DP#3 L25 1
D

R262 51_0402_5% H_TRDY# J6

1 2ITP_BPM#1
<9> H_TRDY# TRDY# CON GTLREF0 AA21 C318
220P_0603_50V8J
R272 51_0402_5% AA6
1
R268
2ITP_BPM#2
51_0402_5% H_A20M#
TROL GTLREF1
GTLREF2 F20
2
C6 F6
1 2ITP_BPM#3
<20>
<20>
H_A20M#
H_FERR#
H_FERR# B6
A20M#
FERR#
REF GTLREF3
R296 51_0402_5% H_IGNNE# B2 AE26
<20> H_IGNNE# IGNNE# OPTIMIZED/COMPAT# +CPU_CORE
1 2ITP_BPM#4 <20> H_SMI#
H_SMI# B5 SMI#
R278 51_0402_5% H_PW RGD AB23
<20> H_PWRGD PWRGOOD
1 2ITP_BPM#5 <20> H_STPCLK#
H_STPCLK# Y4 STPCLK# TESTHI0 AD24 1 R285 2
R291 51_0402_5% AA2 56_0402_5%
H_INTR TESTHI1
D1 AC21 1 R275 2
1 2 H_PW RGD
<20>
<20>
H_INTR
H_NMI
H_NMI E5
LINT0
LINT1
LEGACY TESTHI2
TESTHI3 AC20 56_0402_5%
R288 300_0402_5% H_INIT# W5 AC24
<20> H_INIT# INIT# TESTHI4
H_RESET# AB25 AC23
<8,9> H_RESET# RESET# TESTHI5
AA20 1 2 R293 56_0402_5%
TESTHI6 R276 56_0402_5%
AB22 1 2
<9> H_DBSY#
H_DBSY# H5 DBSY#
ITP TESTHI7
TESTHI8 U6 1 2 R294 56_0402_5%
H_DRD Y# H2 W4 1 2 R464 56_0402_5%
<9> H_DRDY#
<16> H_BSEL0
H_BSEL0 AD6
DRDY#
BSEL0
MISC TESTHI9
TESTHI10 Y3 1 2 R465 56_0402_5%
AD5 A6 H_GHI# 1 2 R466 300_0402_5%
BSEL1 TESTHI11
TESTHI12 AD25 H_DPSLPR# 1 2 R318 @56_0402_5%

H_THERMDA B3 H_DSTBN#[0..3]
+CPU_CORE H_THERMDC C4
THERMDA
THERMDC
THER Northwood-MT H_DSTBN#[0..3] <9>
E22 H_DSTBN#0

C R315
1 2 H_THERMTRIP#
56 _0402_1%
A2 THERMTRIP#
MAL DSTBN#0
DSTBN#1 K22 H_DSTBN#1
H_DSTBN#2 C

<8> ITP_BPM#0
ITP_BPM#0
ITP_BPM#1
AC6 BPM#0
Prescott-MT DATA
DSTBN#2
DSTBN#3
R22
W22 H_DSTBN#3
H_DSTBP#[0..3]
H_DSTBP#[0..3] <9>
<8> ITP_BPM#1 AB5 BPM#1
ITP_BPM#2 AC4 F21 H_DSTBP#0
<8>
<8>
ITP_BPM#2
ITP_BPM#3
ITP_BPM#3 Y6
BPM#2
BPM#3
MISC DSTBP#0
DSTBP#1 J23 H_DSTBP#1
ITP_BPM#4 AA5 P23 H_DSTBP#2
<8> ITP_BPM#4 BPM#4 DSTBP#2
ITP_BPM#5 AB4 W23 H_DSTBP#3
<8> ITP_BPM#5 BPM#5 DSTBP#3 H_ADSTB#0 <9>
+IOPLL
+CPU_CORE
H_ADSTB#1 <9>
0_0603_5% ITP_TCK D4 L5 H_ADSTB#0
R207 1 2
+1.2VP
<8>
<8>
ITP_TCK
ITP_TDI
ITP_TDI C1
TCK
TDI ITP ADDR ADSTB#0
ADSTB#1 R5 H_ADSTB#1
H_DBI#[0..3]
ITP_TDO D5
<8> ITP_TDO TDO H_DBI#[0..3] <9>
ITP_TMS F7
<8> ITP_TMS TMS
R206 1 @0_0603_5%
2 ITP_TRST# E6 E21 H_DBI#0 R266
<8> ITP_TRST# TRST# DBI#0
L24 G25 H_DBI#1 1 @0_0402_5%
2
DBI#1 SYSRST# <21>
1 2 VCCIOPLL AD20 P26 H_DBI#2
LQG21F4R7N00_0805 VCCA AE23
VCCIOPLL
VCCA
DATA DBI#2
DBI#3 V21 H_DBI#3
1 2
LQG21F4R7N00_0805
1
+ C644 <41> VCCSENSE
VCCSENSE A5 VCCSENSE
MISC DBR# AE25 H_DBR#
H_DBR# <8>
L25 2 VSSSENSE A4
<41> VSSSENSE VSSSENSE R311
C320 +1.2VP AF3
@1U_0603_10V6K VCCVIDLB H_PROCHOT# 1 +CPU_CORE
C3 2
1
2 33U_D2_16VM VSSA AD22 VSSA
MISC PROCHOT#
MCERR# V6 100K_0402_1%
RP61 AB26 H_SLP#
@0_4P2R_0402_5% ITP SLP# H_SLP# <20>
4 1 ITP_CLK0 AC26 A22
<16> CLK_CPU_ITP
<16> CLK_CPU_ITP# 3 2 ITP_CLK1 AD26
ITP_CLK0
ITP_CLK1
CLK GROUND MISC
NC1
NC2 A7
NC3 AF25
B R302 1 61.9_0603_1% B
2 L24 COMP0 NC4 AF24
R300 1 61.9_0603_1%
2 P1 AE21

VIDPWRGD
RP62 COMP1 NC5
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181

VCCVID
3 2 Comp0/1 need keep 25
<8> CLK_ITP mils trace width
4 1

VID0
VID1
VID2
VID3
VID4
VID5
<8> CLK_ITP#

0_4P2R_0402_5% +1.2VP
F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5

AE5
AE4
AE3
AE2
AE1
AD3

AD2

AF4
R467
R5721 2 49.9_0402_1% ITP_CLK0 2.43K_0603_1%
FOX_PZ47803-274A-42_Prescott +3VS

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
2 1 +1.2VP 1
R5731 2 49.9_0402_1% ITP_CLK1 +CPU_CORE
H_VID_PWRGD <35>
C317
0.1U_0402_16V4Z

2
+5VS 2
R303
<36,38> SHDN_1632# CPU_VID[0..5] <8,41>

2
8.2K_0402_5% 1K_0402_5%
+CPU_CORE GTL Reference Voltage +5VS R307
Layout note : +CPU_CORE 470_0402_5%

1
1 <21,33> PROCHOT#
1

1. Place R_A and R_B near CPU (Within 1.5"). R334

1
1

1
R333 C174 R337

1
R265 H_THERMDA 0.1U_0402_16V4Z 2
60.4_0603_1% 8.2K_0402_5% 2 Q62 R316 Q26
+H_GTLREF 2N7002_SOT23 470_0402_5% MMBT3904_SOT23
1
2

3
@10K_0402_5%
2

C470 U57
D

S
1 3 R320

2
2200P_0603_50V7K 2 1 H_PROCHOT#
D+ VDD1 <39> H_PROCHOT#

1
2 H_THERMTRIP#
A 1 2 A
1

H_THERMDC 3 6 2 H_THERMTRIP# <21>

1
G
2

R261 D- ALERT# 470_0402_5%

1
102_0603_1% C319 8 4 Q64
<8,32> SMB_EC_CK2
3
1U_0603_6.3V6M SCLK THERM# MMBT3904_SOT23 2
2
<8,32> SMB_EC_DA2 7 5 <10,17,20,24,25,27,28,32,35> PCIRST# Dell-Compal Confidential
2

SDATA GND Q59

Compal Electronics, Inc.

3
MMBT3904_SOT23
Title
ADM1032ARM_RM8
Prescott / P4 uFCPGA & Thermal sensor (2/2)
Intel change to 0.63VCC, then 60.4/102
CPU Temperature Sensor THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Abacus-MT LA-1682
Date: Tuesday, February 25, 2003 Sheet 6 of 44
5 4 3 2 1
 A B C D E F G H I J

+CPU_CORE

Layout note :
Layout note : 1 1 1 1 1
Place close to CPU, Use 2~3 vias per PAD.
1 Place 22uF caps x31 pcs, populated 14pcs. Place close to CPU power and + C645 + C646 + C647 + C648 + C649 1
@470U_D4_2.5VM 470U_D4_2.5VM @470U_D4_2.5VM @470U_D4_2.5VM 470U_D4_2.5VM
ground pin as possible
(<1inch) 2 2 2 2 2

+CPU_CORE

For Desktop's CPU:

+CPU_CORE 470uFx15/10m ohm each 1 1 1 1 1
Place on CPU inside Total 0.67m ohm + + + + +
C650 C651 C652 C653 C654
@470U_D4_2.5VM @470U_D4_2.5VM 470U_D4_2.5VM @470U_D4_2.5VM 470U_D4_2.5VM
1 1 1 1 2 2 2 2 2
C655 C656 C657 C658
2 @22U_1210_6.3V6M 22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M 2
2 2 2 2 +CPU_CORE

+CPU_CORE
1 1 1
+ C661 + C662 + C663
1 1 1 1 1 1 470U_D4_2.5VM @470U_D4_2.5VM 470U_D4_2.5VM

C666 C667 C668 C669 C670 C671 2 2 2

@22U_1210_6.3V6M 22U_1210_6.3V6M 22U_1210_6.3V6M 22U_1210_6.3V6M 22U_1210_6.3V6M 22U_1210_6.3V6M
2 2 2 2 2 2

3 +5VS 3
+12V_FAN
Note:When use +5V Fan,
the J2 must be opened. It L53

2
prevent the +5VS short to

1
@FBM-11-201209-300AT_0805
+CPU_CORE J2
Please place these cap on the socket north side +12V_FAN JOPEN

2
+5VS +3VS
+12VALW
1 1 1 1 1
Fan1 Control circuit

1
C673 C674 C675 C676 C677

1
22U_1210_6.3V6M @22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M 22U_1210_6.3V6M 2 C678 R468
2 2 2 2 2 R469 10K_0402_5%
0.1U_0402_16V4Z 1 C672 10K_0402_5%
U76A 0.1U_0402_16V4Z

1 2
4 4

8
1
LM358 R470 FAN1_TACH <32>

2
4
+CPU_CORE
3 + S
FAN1_ON 2
1 3 G 1 2FAN1_TACH_ON 2 Q66
2 HMBT2222A_SOT23
<32> EN_FAN1 -
1 1 1 1 1 1 Q65 1

3
D 1K_0402_5%
1

4
C679 C680 C681 C682 C683 C684 SI3457DV-T1_TSOP6 C685

1
2
5
6
@22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M @22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M C686 0.47U_1206_16V4Z
2 2 2 2 2 2 1U_0603_10V4Z 2
2
1 2
C687 @2200P_0603_50V7K
R471 Molex_53398-0410
1 2 FAN1_VOUT 4 4
3 3

1
1 FAN1_TACH_FB 2
5 300K_0402_5% 2 5

1
R472 1
+ C688 1
100K_0402_5%
D47 100U_D_16VM C27 JP28
RB751V_SOD323 1 1

2
2 1000P_0402_50V7K JP34

2
C22 FAN1_VOUT
+CPU_CORE 1000P_0402_50V7K FAN1_TACH_FB 1
Please place these cap on the socket south side 2 2 2
3
Note:R471 change to @MOLEX_53398-0390_3P
1 1 1 1 1
66.5K_1%, if use +5V Fan
C689 C690 C691 C692 C693
@22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M +3VS
2 2 2 2 2
+5VS +5VS
6 6

1
+CPU_CORE
Fan2 Control circuit R473

1
10K_0402_5%
R474
1 1 1 1 1 10K_0402_5%
FAN2_TACH <32>

2
1
2
5
6
U76B
C694 C695 C696 C697 C698 D Q67
LM358 R475

1
@22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M 22U_1210_6.3V6M @22U_1210_6.3V6M 5 G
2 2 2 2 2 <32> EN_FAN2 +
7 FAN2_ON 3 1 2FAN2_TACH_ON 2 Q68
6 S SI3456DV-T1_TSOP6 HMBT2222A_SOT23
-
1 1

3
1K_0402_5%
C699 C700
1U_0603_10V4Z 0.47U_1206_16V4Z
2 2
7 C701 @2200P_0603_50V7K 7
FAN2_VFB 1 2

R476 100K_0402_5% JP29

1 2 FAN2_VOUT
FAN2_TACH_FB 1
2
1

1 3

1
R477 1 1
150K_0603_5% C702 MOLEX_53398-0390_3P
D48 10U_1206_10V4Z C28 C29
2 1000P_0402_50V7K 1000P_0402_50V7K
RB751V_SOD323
2

2 2

2
Dell-Compal Confidential
8
Title
Compal Electronics, Inc. 8
CPU Decoupling CAP. & Fan control
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Abacus-MT LA-1682
Date: Tuesday, February 25, 2003 Sheet 7 of 44
A B C D E F G H I J
 10 9 8 7 6 5 4 3 2 1

+3VS
<6,41> CPU_VID[0..5]
H H
CPU_VID0 2 1
R260 1K_0402_5%

CPU_VID1 2 1
R259 1K_0402_5%

CPU_VID2
VID [0..5] 2
R258
1
1K_0402_5%

CPU_VID3 2 1
R257 1K_0402_5%

CPU_VID4 2 1
VID 4 3 2 1 0 V
R256 1K_0402_5% 0 1 0 1 1 1.5750
G CPU_VID5 2 1 0 1 1 0 0 1.5500 G
R478 1K_0402_5%
0 1 1 0 1 1.5250
VID 5 for Prescott-MT 0 1 1 1 0 1.5000
0 1 1 1 1 1.4750
1 0 0 0 0 1.4500
1 0 0 0 1 1.4250
+3VALW 1 0 0 1 0 1.4000
+CPU_CORE
R479
1 0 0 1 1 1.3750
+CPU_CORE H_DBR# 1

29
1 2
F JP30 1 0 1 0 0 1.3500 F
C703

GND6
0.1U_0402_16V4Z 150_0402_5%
2
28 VTT1 1 0 1 0 1 1.3250
27 R480
VTT0 +CPU_CORE
26 VTAP 1 0 1 1 0 1.3000
H_DBR# 25 75_0603_1%
<6> H_DBR# DBR#
24 ITP_TDO 1 2 1 0 1 1 1 1.2750
DBA#
<6> ITP_BPM#0 23 BPM0#
22 R481 1 1 0 0 0 1.2500
GND5
<6> ITP_BPM#1 21 BPM1#
20 150_0402_5% 1 1 0 0 1 1.2250
GND4 ITP_TDI
<6> ITP_BPM#2 19 BPM2# 1 2
18 GND3 1 1 0 1 0 1.2000
<6> ITP_BPM#3 17 BPM3#
16 ITP_TMS 1 2 1 1 0 1 1 1.1750
GND2 R482
<6> ITP_BPM#4 15
E 14
BPM4# 39.2_0603_1% 1 1 1 0 0 1.1500 E
GND1
<6> ITP_BPM#5 13 BPM5#
1 2 ITP_RESET# 12 R484 1 1 1 0 1 1.1250
<6,9> H_RESET# RESET#
R483 ITP_TCK 11 ITP_TRST# 1 2
150_0402_5% FBO 680_0402_5%
10 GND0 1 1 1 1 0 1.1000
<6> CLK_ITP 9 BCLKP
<6> CLK_ITP# 8 BCLKN 1 1 1 1 1 off
ITP_TDO 7 ITP_TCK 1 R485 2
<6> ITP_TDO TDO
6 NC2
ITP_TCK 5 27.4_0603_1%
<6> ITP_TCK TCK
4 NC1
<6> ITP_TRST# ITP_TRST# 3
ITP_TMS TRST#
<6> ITP_TMS 2 TMS
GND7

ITP_TDI 1
<6> ITP_TDI TDI
1 1
D C704 C705 @MOLEX_52435-2891 D
30

@2.2P_0402_16VCJ @2.2P_0402_16VCJ
2 2

ITP DEBUG POINT

C C

+5VS

1
C482 0.1U_0402_16V4Z
0.1U_0402_16V4Z C394
2
1 2
ITP Debug Connector U25 U23
SMB_EC_DA2 1 8 SMB_EC_DA2 1 8 +5VS
<6,32> SMB_EC_DA2 SDA VCC SDA VCC
SMB_EC_CK2 2 7 SMB_EC_CK2 2 7 1 2
<6,32> SMB_EC_CK2 SCL A0 SCL A0
3 6 3 6 R308 10K_0402_5%
OS# A1 OS# A1
B 4 GND A2 5 1 2 4 GND A2 5 B
R351 1K_0402_5%
LM75CIMMX-5_MSOP8 LM75CIMMX-5_MSOP8

1
R486
1K_0402_5%

Address:1001_000X Address:1001_001X

2
Dell-Compal Confidential
A
Title
Compal Electronics, Inc. A
CPU VID & ITP PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 8 of 44
10 9 8 7 6 5 4 3 2 1
 5 4 3 2 1

HA#[3..31] 1.Place R487 and R490 within 0.5" of U77 pin K28
HA#[3..31] <5> HXSWING and HYSWING Ref. Voltage
H_REQ#[0..4] 2.Place R488 and R489 within 0.5" of U77 pin B18
H_REQ#[0..4] <5>
HD#[0..63] +CPU_CORE +CPU_CORE 3.+HYSWING, +HXSWING 10mil trace, 20mil space.
HD#[0..63] <5>

1
U77A R487 R488
301_0402_1% 301_0402_1%
D
Montara-GT D

1 2
HA#3 P23 K22 HD#0 +HYSWING +HXSWING
HA#4 HA#3 HD#0 HD#1
T25 HA#4 HD#1 H27 1 1

1
HA#5 T28 K25 HD#2 R490 R489
HA#6 HA#5 HD#2 HD#3 C706 C707
R27 HA#6 HD#3 L24
HA#7 U23 J27 HD#4 150_0402_1% 150_0402_1%
HA#8 HA7# HD#4 HD#5 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
U24 G28

2
HA#9 HA#8 HD#5 HD#6
R24 L27

2
HA#10 HA#9 HD#6 HD#7
U28 HA#10 HD#7 L23
HA#11 V28 L25 HD#8
HA#12 HA#11 HD#8 HD#9
U27 HA#12 HD#9 J24
HA#13 T27 H25 HD#10
HA#14 HA#13 HD#10 HD#11
V27 K23
HA#15 U25
HA#14
HA#15
HD#11
HD#12 G27 HD#12 Host data Ref. Voltage
HA#16 V26 K26 HD#13
HA#17 HA#16 HD#13 HD#14
Y24 HA#17 HD#14 J23
HA#18 V25 H26 HD#15 +CPU_CORE 1.Place R491 and R492 within 0.5" of U77 pin K21 J21 J17
HA#19 HA#18 HD#15 HD#16
V23 HA#19 HD#16 F25

1
HA#20 W25 F26 HD#17 2.Place C708 C709 C710 C711 in order from U77 to divider
HA#21 HA#20 HD#17 HD#18 R491
Y25 HA#21 HD#18 B27
HA#22 AA27 H23 HD#19 49.9_0603_1% 3.+HVREF 10mil trace, 20mil space.
HA#23 HA#22 HD#19 HD#20
W24 HA#23 HD#20 E27
HA#24 W23 G25 HD#21

1 2
HA#25 HA#24 HD#21 HD#22 +HVREF
W27 HA#25 HD#22 F28
HA#26 Y27 D27 HD#23 1 1 1 1
HA#27 HA#26 HD#23 HD#24 R492
AA28 HA#27 HD#24 G24
HA#28 W28 C28 HD#25 100_0603_1% C708 C709 C710 C711
HA#29 HA#28 HD#25 HD#26 1U_0402_6.3V4Z 0.1U_0402_10V6K @0.1U_0402_10V6K @0.1U_0402_10V6K
AB27 HA#29 HD#26 B26
C HA#30 HD#27 2 2 2 2 C
Y26 G22

2
HA#31 HA#30 HD#27 HD#28
AB28 HA#31 HD#28 C26
E26 HD#29
H_REQ#0 HD#29 HD#30
R28 HREQ#0 HD#30 G23
H_REQ#1 P25 B28 HD#31
H_REQ#2 HREQ#1 HD#31 HD#32
R23 HREQ#2 HD#32 B21
H_REQ#3 R25 G21 HD#33
H_REQ#4 T23
HREQ#3
HREQ#4 HOST
HD#33
HD#34 C24 HD#34 Host Address Ref. Voltage
T26 C23 HD#35
<6> H_ADSTB#0 HADSTB#0 HD#35
AA26 D22 HD#36
<6> H_ADSTB#1 HADSTB#1 HD#36 +CPU_CORE +CPU_CORE
C25 HD#37
CLK_MCH_BCLK# HD#37 HD#38
<16> CLK_MCH_BCLK# AD29 BCLK# HD#38 E24

1
CLK_MCH_BCLK AE29 D24 HD#39
<16> CLK_MCH_BCLK BCLK HD#39
+HYSWING K28 G20 HD#40 R493 R494
R495 27.4_0402_1% +HXSWING HYSWING HD#40 HD#41 49.9_0603_1% 49.9_0603_1%
B18 HXSWING HD#41 E23
1 2 +HYRCOMP H28 B22 HD#42
+HXRCOMP HYRCOMP HD#42 HD#43
1 2 B20 B23

1 2

1 2
R496 27.4_0402_1% HXRCOMP HD#43 HD#44 +HAVREF +HCCVREF
HD#44 F23
K21 F21 HD#45 1 1 1 1
HDVREF0 HD#45 HD#46 R497 R498
J21 HDVREF1 HD#46 C20
+HVREF J17 C21 HD#47 100_0603_1% 100_0603_1%
+HCCVREF HDVREF2 HD#47 HD#48 C713 C715
Y28 HCCVREF HD#48 G18
+HAVREF HD#49 2 C712 2 2 C714 2
Y22 E19

2
HAVREF HD#49 HD#50 0.1U_0402_10V6K 0.1U_0402_10V6K
HD#50 E20
H_DSTBN#0 J28 G17 HD#51
H_DSTBN#1 HDSTBN#0 HD#51 HD#52 1U_0402_6.3V4Z 1U_0402_6.3V4Z
C27 HDSTBN#1 HD#52 D20
H_DSTBN#2 E22 F19 HD#53
H_DSTBN#3 HDSTBN#2 HD#53 HD#54
D18 HDSTBN#3 HD#54 C19
H_DSTBP#0 K27 C17 HD#55
B HDSTBP#0 HD#55

HUBLink reference Voltage

H_DSTBN#[0..3] H_DSTBP#1 HD#56 B
<6> H_DSTBN#[0..3] D26 HDSTBP#1 HD#56 F17
H_DSTBP#2 E21 B19 HD#57
H_DSTBP#3 HDSTBP#2 HD#57 HD#58
E18 HDSTBP#3 HD#58 G16
H_DBI#0 J25 E16 HD#59 +1.5VS
H_DSTBP#[0..3] H_DBI#1 DINV0# HD#59 HD#60
<6> H_DSTBP#[0..3] E25 DINV1# HD#60 C16
H_DBI#2 B25 E17 HD#61
DINV2# HD#61

1
H_DBI#3 G19 D16 HD#62
DINV3# HD#62 HD#63 R499
HD#63 C18
H_DBI#[0..3] F15 80.6_0402_1%
<6> H_DBI#[0..3] <6,8> H_RESET# CPURST#
HI[0..10] H I0 U7
<20> HI[0..10]

2
H I1 HL_0
U4 HL_1
H I2 U3 L28 +HUB_PSWING
HL_2 ADS# H_ADS# <5>
H I3 V3 M25 1 1
HL_3 HTRDY# H_TRDY# <6>
H I4 W2 N24 C716 C717
HL_4 DRDY# H_DRDY# <6>

1
H I5 W6 M28 0.01U_0402_25V7Z 0.1U_0402_10V6K
HL_5 DEFER# H_DEFER# <5>
H I6 V6 N28 R500
HL_6 HITM# H_HITM# <5> 2
H I7 W7 N27 51.1_0603_1%2
H_HIT# <5>
HUB I/F

H I8 HL_7 HIT#
T3 HL_8 HLOCK# P27 H_LOCK# <5>
H I9 V5 M23 H_BREQ0# <5>

2
HI10 HL_9 BREQ0# +HUB_VREF
V4 HL_10 BNR# N25 H_BNR# <5>
W3 HLSTB BPRI# P28 H_BPRI# <5>

1
<20> HUB_PSTRB V2 HLSTB# DBSY# M26 H_DBSY# <6> 1 1
T2 N23 H_RS#0 C718 R501 C719
<20> HUB_PSTRB# HLRCOMP RS#0 0.01U_0402_25V7Z 0.1U_0402_10V6K
+1.5VS 1 2 HLRCOMP U2 P26 H_RS#1
+HUB_PSWING PSWING RS#1 H_RS#2 40.2_0603_1%
W1 HLVREF RS#2 M27
R502 +HUB_VREF 2 2

2
48.7_0603+1% H_RS#[0..2]
H_RS#[0..2] <6>
RG82G4350MA1_uFCBGA732_MONTARA-GT
A A

Dell-Compal Confidential
Compal Electronics, Inc.
Title
Montara-GT (1/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 9 of 44
5 4 3 2 1
 5 4 3 2 1

U77B

AGP_AD[0..31] AGP_AD3
Montara-GT
<17> AGP_AD[0..31] R3 DVOBD0/GAD3 BLUE C9 INTCRT_B <17>
AGP_AD2 R5 D9
AGP_AD14 AGP_AD5 DVOBD1/GAD2 BLUE#
R6 DVOBD2/GAD5 GREEN C8 INTCRT_G <17>
AGP_AD13 AGP_AD4 R4 D8
AGP_AD31 AGP_AD7 DVOBD3/GAD4 GREEN#
P6 DVOBD4/GAD7 RED A7 INTCRT_R <17>
AGP_AD6 P5 A8
DVOBD5/GAD6 RED#
1

DAC
D AGP_AD8 N5 H10 R506 D
DVOBD6/GAD8 HSYNC INT_HSYNC <17>
P2 J9 1@127_0603_1%
<17> AGP_CBE#0 DVOBD7/GCBE0# VSYNC INT_VSYNC <17>
AGP_AD10 N2 E8 1 2
AGP_AD9 DVOBD8/GAD10 REFSET
N3 DVOBD9/GAD9 DDCACLK B6 INTDDCCK <17>
R503 AGP_AD12 M1 G9 +3VS
INTDDCDA <17>
2

2 DVOBD10/GAD12 DDCADATA
R505 AGP_AD11 M5
100K_0402_5% 1@100K_0402_5% DVOBD11/GAD11

<17> AGP_ADSTB0 P3 DVOBCLK/GADSTB0

P4 G14 R507
<17> AGP_ADSTB0# DVOBCLK#/GADSTB0# IYAM0 LCD_A0- <18>
R504 AGP_AD0 T6 E15 LCD_DDCCLK 1 2
DVOBHSYNC/GAD0 IYAM1 LCD_A1- <18>
1@100K_0402_5% AGP_AD1 T5 C15
DVOBVSYNC/GAD1 IYAM2 LCD_A2- <18>
L2 C13 2.2K_0402_5%
<17> AGP_CBE#1 DVOBBLANK#/GCBE1# IYAM3
AGP_AD14 M2 F14
DVOBFLDSTL/GAD14 IYAP0 LCD_A0+ <18>
IYAP1 E14 LCD_A1+ <18>
AGP_AD30 G2 C14 R508
R509 DVOBCINTR#/GAD30 IYAP2 LCD_A2+ <18>
AGP_AD13 M3 B13 LCD_DDCDATA 1 2
AGP_AD30 DVOBCCLKINT/GAD13 IYAP3
+1.5VS_DVO 1 2 IYBM0 H12 LCD_B0- <18>
J3 E12 2.2K_0402_5%
<17> AGP_ADSTB1 DVOCCLK/GADSTB1 IYBM1 LCD_B1- <18>
1@100K_0402_5% J2 C12
<17> AGP_ADSTB1# DVOCCLK#/GADSTB1# IYBM2 LCD_B2- <18>
AGP_AD17 K6 G11

LVDS
AGP_AD16 DVOCHSYNC/GAD17 IYBM3
L5 DVOCVSYNC/GAD16 IYBP0 G12 LCD_B0+ <18>
AGP_AD18 L3 E11 +CPU_CORE
DVOCBLANK#/GAD18 IYBP1 LCD_B1+ <18> R570
AGP_AD31 H5 C11
DVOCFLDSTL/GAD31 IYBP2 LCD_B2+ <18>
G10 H_DPSLP# 2 1
IYBP3
ICLKAM D14 LCD_ACLK- <18>
<17> AGP_IRDY# K7 MI2CCLK/GIRDY# ICLKAP E13 LCD_ACLK+ <18>
N6 E10 @56 _0402_1%
<17> AGP_DEVSEL# MI2CDATA/GDEVSEL# ICLKBM LCD_BCLK- <18>
<17> AGP_TRDY# N7 MDVICLK/GTRDY# ICLKBP F10 LCD_BCLK+ <18>
<17> AGP_FRAME# M6 MDVIDATA/GFRAME#
C P7 B4 LCD_DDCCLK C
<17> AGP_STOP# MDDCCLK/GSTOP# DDCPCLK LCD_DDCCLK <18>
AGP_AD15 T7 C5 LCD_DDCDATA
MDDCDATA/GAD15 DDCPDATA LCD_DDCDATA <18>
G8 R511 1@0_0402_5%
AGP_AD19 PANELBKLTCTL PANEL_BKEN
K5 DVOCD0/GAD19 PANELBKLTEN F8 1 2 ENABKL <17,18,33>
AGP_AD20 K1 A5 ENVDD <18>

DVO
+AGPREF AGP_AD21 DVOCD1/GAD20 PANELVDDEN
K3 DVOCD2/GAD21
AGP_AD22 K2 R512 [email protected]_0603_1%
AGP_AD23 DVOCD3/GAD22
1 J6 DVOCD4/GAD23 LIBG A10 1 2
<17> AGP_CBE#3 J5 DVOCD5/GCBE3#
AGP_AD25 H2 D12
AGP_AD24 DVOCD6/GAD25 RSVD3
H1 DVOCD7/GAD24 RSVD4 F12
2 AGP_AD27 H3 DVOCD8/GAD27 RSVD5 B12
C720 AGP_AD26 H4
AGP_AD29 DVOCD9/GAD26
H6 DVOCD10/GAD29
0.1U_0402_10V6K AGP_AD28 G3 B7 CLK_MCH_DISPLAY CLK_MCH_DISPLAY <16> +3VS
DVOCD11/GAD28 DREFCLK DREFSSCLK R514
B17

CLKS
DREFSSCLK 1K_0402_5%
LCLKCTLA H9
AGP_SBA[0..7] C6 LCLKCTLB 1 2
<17> AGP_SBA[0..7] LCLKCTLB
LCLKCTLB H:1.2V
AGP_SBA0
AGP_SBA1
E5
F5
ADDID0/GSBA0 PSB Voltage Select
+1.5VS AGP_SBA2 ADDID1/GSBA1
E3 ADDID2/GSBA2 DPWR# AA22
AGP_SBA3 E2 Y23 H_DPSLP# L41
ADDID3/GSBA3 DPSLP# H_DPSLP# <6,20>
AGP_SBA4 G5 AD28 C722

MISC
ADDID4/GSBA4 RSTIN# PCIRST# <6,17,20,24,25,27,28,32,35>
1

AGP_SBA5 F4 FCM2012C-800_0805
R515 AGP_SBA6 ADDID5/GSBA5 4.7U_0805_6.3V6K
G6 ADDID6/GSBA6 PWROK J11 PM_PWROK <21,32,34> +SVDD 1 2 +3VS
AGP_SBA7 F6
1@1K_0402_5% ADDID7/GSBA7 R516 1
EXTTS0 D6 210K_0603_1% +3VS 1 1 1 C723
B C721 B
<17> AGP_PAR L7
2

AGP_PIPE# DVODETECT/GPAR 0.1U_0402_10V6K 0.1U_0402_10V6K

<17> AGP_PIPE# D5 DPMS/GPIPE#
R517 1@0_0402_5% +AGPREF F1 GVREF 2 2 2
<17,21> AGP_BUSY# 1 2 F7 AGPBUSY#
1

D
D1 DVO_GRCOMP NC0 B1
2 CLK_MCH_66M Y3 AH1
<21> RTCCLK <16> CLK_MCH_66M GCLKIN NC1
1

G A2 R519 0_0402_5%
Q69 R518 NC2
S <17> AGP_SBSTB F2 AJ2 1 2
3

1@BSS138_SOT23 GSBSTB NC3

<17> AGP_SBSTB# F3 GSBSTB# NC4 A28
40.2_0603_1% B2 AJ28
<17> AGP_GNT# GGNT# NC5
B3 A29 +SVDD
<17> AGP_REQ#
2

AGP_ST2 GREQ# NC6

NC

<17> AGP_ST2 C2 GST2 NC7 B29

AGP_ST1 C3 AH29 11/12 EMI change to W181-51
<17> AGP_ST1 GST1 NC8

6
AGP_ST0 C4 AJ29 U78
<17> AGP_ST0 GST0 NC9
D2 AA9

VDD
<17> AGP_WBF# GWBF# NC10
<17> AGP_RBF# D3 GRBF# NC11 AJ4
L4 R520 @22_0402_5%
<17> AGP_CBE#2 GCBE#2
D7 CLK_VCH 1 5 SSVCH_OUT 1 2 DREFSSCLK
RSVD1 <16> CLK_VCH X1/CLK CLKOUT
AA5 RSVD2
RG82G4350MA1_uFCBGA732_MONTARA-GT R521 1 2 @1K_0402_5% 7 2
FS1 X2 R523
CLK_MCH_DISPLAY CLK_MCH_66M DREFSSCLK
R522 1 2 @1K_0402_5% 8 4 1 2 +SVDD
FS2 SS%
1

+1.5VS

GND
1

1
R528 @1K_0402_5%
R524 R525 R526 @1K_0402_5%
FS2 FS1 R527
@33_0402_5% @33_0402_5% @33_0402_5% AGP_ST0 @W181G_SOIC8 @1K_0402_5%
1 2 0 0 28< <38

3
SS% L : -0.625%< <0.625%
2

R529
0 1 38< <48
2

2
A A
1K_0402_5%
C724
1
C725
1 1
AGP_ST1
SS% H : -1.875%< <1.875%
C726
1 2 * 1 0 46< <60
@10P_0402_25V8K @10P_0402_25V8K @10P_0402_25V8K R530
2 2 2 1K_0402_5%
1 1 58< <75
AGP_ST2
1 2 Compal Electronics, Inc.
Title
Montara-GT (2/4)
Size Document Number Rev
Abacus-MT LA-1682 0.2

Date: Tuesday, February 25, 2003 Sheet 10 of 44

5 4 3 2 1
 5 4 3 2 1

U77C

DDR_SMA[0..12] DDR_SDQ[0..63]
D
<13,14> DDR_SMA[0..12]
DDR_SMA0
Montara-GT DDR_SDQ0
DDR_SDQ[0..63] <13>
D
AC18 SMA0 SDQ0 AF2
DDR_SMA1 AD14 AE3 DDR_SDQ1
DDR_SMA2 SMA1 SDQ1 DDR_SDQ2
AD13 SMA2 SDQ2 AF4
DDR_SMA3 AD17 AH2 DDR_SDQ3
DDR_SMA4 SMA3 SDQ3 DDR_SDQ4 +2.5V
AD11 SMA4 SDQ4 AD3
DDR_SMA5 AC13 AE2 DDR_SDQ5
DDR_SMA6 SMA5 SDQ5 DDR_SDQ6
AD8 SMA6 SDQ6 AG4

1
DDR_SMA7 AD7 AH3 DDR_SDQ7
DDR_SMA8 SMA7 SDQ7 DDR_SDQ8 R531
AC6 SMA8 SDQ8 AD6
DDR_SMA9 AC5 AG5 DDR_SDQ9 604_0603_1%
DDR_SMA10 SMA9 SDQ9 DDR_SDQ10
AC19 SMA10 SDQ10 AG7
DDR_SMA11 AD5 AE8 DDR_SDQ11

2
DDR_SMA12 SMA11 SDQ11 DDR_SDQ12 +SMVSWINGL
AB5 SMA12 SDQ12 AF5
AH4 DDR_SDQ13
SDQ13

1
DDR_SDQS[0..7] AF7 DDR_SDQ14
<13> DDR_SDQS[0..7] SDQ14
AH6 DDR_SDQ15 R532
DDR_SDQS0 SDQ15 DDR_SDQ16 150_0603_1%
DDR_SDQS1
AG2
AH5
SDQS0
SDQS1
MEMORY SDQ16
SDQ17
AF8
AG8 DDR_SDQ17
DDR_SDQS2 AH8 AH9 DDR_SDQ18

2
DDR_SDQS3 SDQS2 SDQ18 DDR_SDQ19
AE12 SDQS3 SDQ19 AG10
DDR_SDQS4 AH17 AH7 DDR_SDQ20
DDR_SDQS5 SDQS4 SDQ20 DDR_SDQ21
AE21 SDQS5 SDQ21 AD9
DDR_SDQS6 AH24 AF10 DDR_SDQ22
DDR_SDQS7 SDQS6 SDQ22 DDR_SDQ23
AH27 SDQS7 SDQ23 AE11
AD15 AH10 DDR_SDQ24
SDQS8 SDQ24 DDR_SDQ25
SDQ25 AH11
AG13 DDR_SDQ26
DDR_SWE# AD25 SDQ26 DDR_SDQ27
<13,14> DDR_SWE# SWE# SDQ27 AF14
C DDR_SRAS# AC21 AG11 DDR_SDQ28 +2.5V C
<13,14> DDR_SRAS# SRAS# SDQ28
DDR_SCAS# AC24 AD12 DDR_SDQ29
<13,14> DDR_SCAS# SCAS# SDQ29
AF13 DDR_SDQ30
SDQ30

1
AH13 DDR_SDQ31
DDR_CLK0 SDQ31 DDR_SDQ32 R533
<13> DDR_CLK0 AB2 SCK0 SDQ32 AH16
DDR_CLK0# AA2 AG17 DDR_SDQ33 60.4_0603_1%
<13> DDR_CLK0# SCK0# SDQ33
DDR_CLK1 AC26 AF19 DDR_SDQ34
<13> DDR_CLK1 SCK1 SDQ34
DDR_CLK1# AB25 AE20 DDR_SDQ35
<13> DDR_CLK1#

2
DDR_CLK2 SCK1# SDQ35 DDR_SDQ36 +SMRCOMP
<13> DDR_CLK2 AC3 SCK2 SDQ36 AD18
DDR_CLK2# AD4 AE18 DDR_SDQ37
<13> DDR_CLK2# SCK2# SDQ37

1
DDR_CLK3 AC2 AH18 DDR_SDQ38 1
<14> DDR_CLK3 SCK3 SDQ38
DDR_CLK3# AD2 AG19 DDR_SDQ39 R534 C727
<14> DDR_CLK3# SCK3# SDQ39
DDR_CLK4 AB23 AH20 DDR_SDQ40 60.4_0603_1%
<14> DDR_CLK4 SCK4 SDQ40
DDR_CLK4# AB24 AG20 DDR_SDQ41 0.1U_0402_10V6K
<14> DDR_CLK4# SCK4# SDQ41 2
DDR_CLK5 AA3 AF22 DDR_SDQ42
<14> DDR_CLK5

2
DDR_CLK5# SCK5 SDQ42 DDR_SDQ43
<14> DDR_CLK5# AB4 SCK5# SDQ43 AH22
AF20 DDR_SDQ44
SDQ44 DDR_SDQ45
SDQ45 AH19
DDR_CKE0 AC7 AH21 DDR_SDQ46
<13> DDR_CKE0 SCKE0 SDQ46
DDR_CKE1 AB7 AG22 DDR_SDQ47
<13> DDR_CKE1 SCKE1 SDQ47
DDR_CKE2 AC9 AE23 DDR_SDQ48
<14> DDR_CKE2 SCKE2 SDQ48
DDR_CKE3 AC10 AH23 DDR_SDQ49
<14> DDR_CKE3 SCKE3 SDQ49
DDR_SCS#0 AD23 AE24 DDR_SDQ50
<13> DDR_SCS#0 SCS#0 SDQ50
DDR_SCS#1 AD26 AH25 DDR_SDQ51
<13> DDR_SCS#1 SCS#1 SDQ51
DDR_SCS#2 AC22 AG23 DDR_SDQ52
<14> DDR_SCS#2 SCS#2 SDQ52
DDR_SCS#3 AC25 AF23 DDR_SDQ53 +2.5V
<14> DDR_SCS#3 SCS#3 SDQ53
AF25 DDR_SDQ54
SDQ54 DDR_SDQ55
SDQ55 AG25

1
DDR_SBS0 AD22 AH26 DDR_SDQ56
B <13,14> DDR_SBS0 SBA0 SDQ56 B
DDR_SBS1 AD20 AE26 DDR_SDQ57 R535
<13,14> DDR_SBS1 SBA1 SDQ57
AG28 DDR_SDQ58 150_0603_1%
SDQ58 DDR_SDQ59
SDQ59 AF28
DDR_SDM0 AE5 AG26 DDR_SDQ60

2
DDR_SDM1 SDM0 SDQ60 DDR_SDQ61 +SMVSWINGH
AE6 SDM1 SDQ61 AF26
DDR_SDM2 AE9 AE27 DDR_SDQ62
SDM2 SDQ62

1
DDR_SDM3 AH12 AD27 DDR_SDQ63
DDR_SDM4 SDM3 SDQ63 R536
AD19 SDM4
DDR_SDM5 AD21 604_0603_1%
DDR_SDM6 SDM5
AD24 SDM6
DDR_SDM[0..7] DDR_SDM7 AH28 AG14
<13> DDR_SDM[0..7]

2
SDM7 SDQ64
AH15 SDM8 SDQ65 AE14
AE17 +2.5V
SDQ66
SDQ67 AG16
DDR_SMAB1 AD16 AH14
<14> DDR_SMAB1 SMAB1 SDQ68
DDR_SMAB2 AC12 AE15
<14> DDR_SMAB2 SMAB2 SDQ69

1
DDR_SMAB4 AF11 AF16
<14> DDR_SMAB4 SMAB4 SDQ70
DDR_SMAB5 AD10 AF17 R537
<14> DDR_SMAB5 SMAB5 SDQ71 @10K_0603_1%
AC15 RCVENOUT#
Need place Via as closed as pin. AC16
2
RCVENIN# R539
+SMRCOMP AB1 AJ24 SMVREF0 1 2 SDREF
SMRCOMP SMVREF0 1
0_0603_5%
+SMVSWINGL AJ22 1 R540
+SMVSWINGH SMVSWINGL C728 @10K_0603_1%
AJ19 SMVSWINGH
RG82G4350MA1_uFCBGA732_MONTARA-GT 0.1U_0402_10V6K
2

2
A A

TOPOLOGY 2 FOR DDR Dell-Compal Confidential

SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Compal Electronics, Inc.
Title
Montara-GT (3/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 11 of 44
5 4 3 2 1
 5 4 3 2 1

U77D
C1 VSS0 VSS91 R17
G1 VSS1 VSS92 U17 1.5V for GT
L1 AB17 +CPU_CORE
VSS2 VSS93 +1.5VS
U1 VSS3 VSS94 AC17
AA1 F18 U77E
VSS4 VSS95 C738
AE1 VSS5 VSS96 J18 CLOSE TO VCC 0.1U_0402_10V6K
D
R2
AG3
VSS6 VSS97 AA18
AG18 C732 C734 J15
Montara-GT G15 1 1 1
1
D
VSS7 VSS98 C730 1 0.1U_0402_10V6K 0.1U_0402_10V6K VCC0 VTTLF0 + C736
AJ3 VSS8 VSS99 A19 1 P13 VCC1 VTTLF1 H16
D4 D19 C807 1 1 150U_D2_6.3VM 1 1 1 1 1 T13 H18 150U_D2_4VM
VSS9 VSS100 0.1U_0402_10V6K + + VCC2 VTTLF2
G4 VSS10 VSS101 H19 N14 VCC3 VTTLF3 J19
C735 2 2 2 2
K4 VSS11 VSS102 AB19 R14 VCC4 VTTLF4 H20
N4 AE19 U14 L21 C737 C739
VSS12 VSS103 2 2 C7292 2 C731 2 2 2 2 2
0.1U_0402_10V6K VCC5 VTTLF5 0.1U_0402_10V6K 10U_1206_6.3V7K
T4 VSS13 VSS105 F20 P15 VCC6 VTTLF6 N21
W4 J20 C808 150U_D2_6.3VM 10U_1206_6.3V7K C733 T15 R21
VSS14 VSS106 0.1U_0402_10V6K 0.1U_0402_10V6K VCC7 VTTLF7
AA4 VSS15 VSS107 AA20 AA15 VCC8 VTTLF8 U21
AC4 AC20 N16 H22 0.1U_0402_10V6K
VSS16 VSS108 VCC9 VTTLF9
AE4 VSS17 VSS109 A21 R16 VCC10 VTTLF10 M22 1 1
B5 D21 +1.5VS 1.5V for GT U16 P22 C809 C810
VSS18 VSS110 L42 VCC11 VTTLF11
U5 VSS19 VSS111 H21 P17 VCC12 VTTLF12 T22
Y5 M21 KC FBM-L11-201209-221LMAT_0805 CLOSE TO VCCHL T17 V22
VSS20 VSS112 VCC13 VTTLF13 2 2
Y6 VSS21 VSS113 P21 1 2+VCCADPLLA 1.5V for GT AA17 VCC14 VTTLF14 Y29
AG6 T21 1 C745 AA19 K29 0.1U_0402_10V6K
VSS22 VSS114 C744 0.1U_0402_10V6K VCC15 VTTLF15
C7 VSS23 VSS115 V21 CLOSE TO PIN 1 +1.5VS W21 VCC16 VTTLF16 F29
E7 Y21 + 0.1U_0402_10V6K H14 AB29
VSS24 VSS116 C740 C741 VCC17 VTTLF17 C742 1
G7 VSS25 VSS117 AA21 1 1 1 1 VTTLF18 A26 2 0.1U_0402_16V4Z
J7 AB21 220U_D2_4VM 0.1U_0402_10V6K A20
VSS26 VSS118 2 2 VTTLF19 C746 1
M7 VSS27 VSS119 AG21 V1 VCCHL0 VTTLF20 A18 2 0.1U_0402_16V4Z
R7 VSS28 VSS120 B24 Y1 VCCHL1
AA7 F22 1 2 +VCCADPLLB C743 2 2 2 2
W5 A22 C747 1 2 0.1U_0402_16V4Z
VSS29 VSS121 L43 10U_1206_6.3V7K C811 VCCHL2 VTTHF0
AE7 VSS30 VSS122 J22 1 1 U6 VCCHL3 VTTHF1 A24
AJ7 L22 KC FBM-L11-201209-221LMAT_0805 0.1U_0402_10V6K U8 H29 C748 1 2 0.1U_0402_16V4Z
VSS31 VSS123 + VCCHL4 VTTHF2
H8 VSS32 VSS124 N22 W8 VCCHL5 VTTHF3 M29
K8 R22 V7 V29 C751 1 2 0.1U_0402_16V4Z
VSS33 VSS125 C7502 VCCHL6 VTTHF4
Montara-GT

P8 VSS34 VSS126 U22 V9 VCCHL7

T8 W22 C7492 0.1U_0402_10V6K +1.5VS AC1 +2.5V C757
C
VSS35 VSS127 C752 VCCSM0 C755 C
V8 VSS36 VSS128 AE22 D29 VCCAHPLL VCCSM1 AG1
Y8 A23 220U_D2_4VM 0.1U_0402_10V6K Y2 AB3 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS37 VSS129 VCCAGPLL VCCSM2
AC8 VSS38 VSS130 D23 VCCSM3 AF3
E9 AA23 +1.5VS 1 1 +VCCADPLLA A6 Y4 1 1 1 1 0.1U_0402_10V6K
1 1
VSS39 VSS131 +1.5VS C753 +VCCADPLLB VCCADPLLA VCCSM4 C812 C813
L9 VSS40 VSS132 AC23 B16 VCCADPLLB VCCSM5 AJ5
N9 VSS41 VSS133 AJ23 VCCSM6 AA6
1

POWER
R9 F24 0.1U_0402_10V6K AB6
VSS42 VSS134 L44 2 2 VCCSM7 2 2 2 2 2 2
U9 VSS43 VSS135 H24 +1.5VS_DVO E1 VCCDVO_0 VCCSM8 AF6

2
W9 K24 FLM1608081R8K_0603 J1 Y7
VSS44 VSS136 L45 VCCDVO_1 VCCSM9 C754 C756 0.1U_0402_10V6K
AB9 VSS45 VSS137 M24 N1 VCCDVO_2 VCCSM10 AA8
AG9 P24 +1.5VS_DAC E4 AB8 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS46 VSS138 BLM21A601SPT_0805 VCCDVO_3 VCCSM11
C10 T24 J4 Y9
2

VSS47 VSS139 VCCDVO_4 VCCSM12

J10 VSS48 VSS140 V24 M4 VCCDVO_5 VCCSM13 AF9
AA10 AA24 1 C760 1 E6 AJ9 C766 C768

1
VSS49 VSS141 C758 0.01U_0402_25V7Z C763 VCCDVO_6 VCCSM14 0.1U_0402_10V6K 0.1U_0402_10V6K
AE10 VSS50 VSS142 AG24 1 1 H7 VCCDVO_7 VCCSM15 AB10
D11 A25 + + J8 AA11 0.1U_0402_10V6K
VSS51 VSS143 1 1 1 1 VCCDVO_8 VCCSM16 1 1 1 1 1 1
F11 D25 C761 0.1U_0402_10V6K L8 AB12 C815 C816
VSS52 VSS144 @220U_D2_4VM C814 150U_D2_6.3VM VCCDVO_9 VCCSM17
H11 VSS53 VSS145 AA25 M8 VCCDVO_10 VCCSM18 AF12
2 2 2 0.1U_0402_10V6K 2
AB11 VSS54 VSS146 AE25 N8 VCCDVO_11 VCCSM19 AA13
C759 2 C762 2 2 C764 2 2 2 2 2 2 2
AC11 VSS55 VSS147 G26 R8 VCCDVO_12 VCCSM20 AJ13
AJ11 J26 0.1U_0402_10V6K 10U_1206_6.3V7K 0.1U_0402_10V6K K9 AB14 C765 C767
VSS56 VSS148 VCCDVO_13 VCCSM21 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
J12 VSS57 VSS149 L26 M9 VCCDVO_14 VCCSM22 AF15
AA12 N26 +1.5VS_DLVDS 1 1 1 P9 AB16
VSS58 VSS150 VCCDVO_15 VCCSM23
AG12 VSS59 VSS151 R26 VCCSM24 AJ17
A13 U26 C817 AB18 C771 & C772 change to 100u
VSS60 VSS152 0.1U_0402_10V6K C818 C819 VCCSM25 next Reversion
D13 VSS61 VSS153 W26 1 1 +1.5VS_DAC A9 VCCADAC0 VCCSM26 AF18
C769 2 2 2
F13 VSS62 VSS154 AB26 B9 VCCADAC1 VCCSM27 AB20
H13 A27 C770 0.1U_0402_10V6K 0.1U_0402_10V6K B8 AF21 1 1 1 1 0.1U_0402_10V6K
1 1
VSS63 VSS155 1@47U_1210_6.3V4Z 1@22U_1210_6.3V6M VSSADAC VCCSM28 C771 C772 C773 C774 C820 C821
N13 VSS64 VSS156 F27 VCCSM29 AJ21
B 2 2 + + B
R13 VSS65 VSS157 AC27 +1.5VS_ALVDS VCCSM30 AB22
U13 AG27 A11 AF24 0.1U_0402_10V6K
VSS66 VSS158 +1.5VS +1.5VS_ALVDS +1.5VS +1.5VS_DLVDS VCCALVDS VCCSM31 150U_D2_4VM 2 2 2 2
AB13 VSS67 VSS159 AJ27 B11 VSSALVDS VCCSM32 AJ25
2 2
AE13 VSS68 VSS160 AC28 L46 L47 VCCSM33 AF27
J14 AE28 AC29 150U_D2_4VM 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS69 VSS161 VCCSM34
P14 VSS70 VSS162 C29 1 2 1 2 +1.5VS_DLVDS G13 VCCDLVDS0 VCCSM35 AF29
T14 E29 FLM1608081R8K_0603 1 1 FLM1608081R8K_0603 1 B14 AG29
VSS71 VSS163 C776 VCCDLVDS1 VCCSM36
AA14 VSS72 VSS164 G29 J13 VCCDLVDS2
AC14 J29 C775 C777 B15 +2.5V_QSM +2.5V
VSS73 VSS165 0.1U_0402_10V6K 0.01U_0402_25V7Z 0.1U_0402_10V6K VCCDLVDS3 C778 R16
D15 VSS74 VSS166 L29 L48
2 2 2 0.1U_0402_10V6K 0_0805_5%
H15 VSS75 VSS167 N29
N15 VSS76 VSS168 U29 +2.5V_TXLVDS F9 VCCTXLVDS0 1 2 1 2
R15 VSS77 VSS169 W29 B10 VCCTXLVDS1 VCCQSM0 AJ6 1 1
U15 AA29 D10 AJ8 KC FBM-L11-201209-221LMAT_0805
VSS78 VSS170 VCCTXLVDS2 VCCQSM1 C779
AB15 VSS79 VSS171 AJ10 A12 VCCTXLVDS3
AG15 AJ12 R541 +VCC_GPIO VCC_ASM 4.7U_1206_10V7K
VSS80 VSS172 C783 C785 0_0603_5% 2 2 +1.5VS
F16 VSS81 VSS173 AJ18 L49 VCCASM0 AD1
J16 AJ20 1@22U_1206_16V4Z_V1 0.1U_0402_10V6K 1 2 A3 AF1 L50
VSS82 VSS174 +3VS VCCGPIO_0 VCCASM1
P16 VSS83 VSS176 C22 +2.5V 1 2 +2.5V_TXLVDS A4 VCCGPIO_1
T16 D28 FLM1608081R8K_0603 1 1 1 2
VSS84 VSS177 C780 KC FBM-L11-201209-221LMAT_0805
AA16 VSS85 VSS178 E28 1 1 1 1 1 1 1
AE16 L6 @10U_1206_6.3V7K C781 RG82G4350MA1_uFCBGA732_MONTARA-GT
VSS86 VSS179 C782 0.1U_0402_10V6K C787 + C788
A17 VSS87 VSS180 T9
1@47U_1210_6.3V4Z 2 2 100U_D_16VM
D17 VSS88 VSS181 AJ26
2 2 2 2 2 0.1U_0402_10V6K 2
H17 VSS89 VSS182 AJ1
C784 C786 2
N17 VSS90 0.1U_0402_10V6K 0.1U_0402_10V6K

A A
RG82G4350MA1_uFCBGA732_MONTARA-GT

Dell-Compal Confidential
Compal Electronics, Inc.
Title
Montara-GT(4/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
Abacus-MT LA-1682
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 12 of 44
5 4 3 2 1
 A B C D E F G H

+2.5V
SDREF_DIMM
RP32 10_4P2R_0402_5% RP46 10_4P2R_0402_5% +2.5V
DDR_SDQ1 1 4 DDR_DQ1 DDR_SDQ26 1 4 DDR_DQ26 JP22 R322
DDR_SDQ4 2 3 DDR_DQ4 DDR_SDQ31 2 3 DDR_DQ31 1 2 2 1
VREF VREF SDREF
3 VSS VSS 4 1
DDR_DQ5 5 6 DDR_DQ4 0_0402_5%
RP42 10_4P2R_0402_5% RP37 10_4P2R_0402_5% DDR_DQ2 DQ0 DQ4 DDR_DQ1 C413 DDR_DQ[0..63]
7 DQ1 DQ5 8 DDR_DQ[0..63] <14>
DDR_SDQ2 1 4 DDR_DQ2 DDR_SDQ27 1 4 DDR_DQ27 9 10 0.1U_0402_16V4Z
DDR_SDQ5 DDR_DQ5 DDR_SDQ30 DDR_DQ30 DDR_DQS0 VDD VDD DDR_DM0 2 DDR_DQS[0..7]
2 3 2 3 11 DQS0 DM0 12 DDR_DQS[0..7] <14>
DDR_DQ0 13 14 DDR_DQ3
DQ2 DQ6 DDR_DM[0..7]
15 VSS VSS 16 DDR_DM[0..7] <14>
RP33 10_4P2R_0402_5% R119 10_0402_5% DDR_DQ6 17 18 DDR_DQ7
DDR_SDQ6 DDR_DQ6 DDR_SDM0 DDR_DM0 DDR_DQ8 DQ3 DQ7 DDR_DQ13
1 4 2 1 19 DQ8 DQ12 20
DDR_SDQ0 2 3 DDR_DQ0 DDR_SDM1 2 1 DDR_DM1 21 22
1 R117 10_0402_5% DDR_DQ12 VDD VDD DDR_DQ9 1
23 DQ9 DQ13 24
DDR_DQS1 25 26 DDR_DM1
RP43 10_4P2R_0402_5% R126 10_0402_5% DQS1 DM1
27 VSS VSS 28
DDR_SDQ7 1 4 DDR_DQ7 DDR_SDM2 2 1 DDR_DM2 DDR_DQ14 29 30 DDR_DQ10 DDR_SMA0 2 1 DDR_SMAA0
DDR_SDQ3 DDR_DQ3 DDR_SDM3 DDR_DM3 DDR_DQ11 DQ10 DQ14 DDR_DQ15 R167 10_0402_5%
2 3 2 1 31 DQ11 DQ15 32
R127 10_0402_5% 33 34
VDD VDD
<11> DDR_CLK0 35 CK0 VDD 36
RP20 10_4P2R_0402_5% R114 10_0402_5% 37 38
<11> DDR_CLK0# CK0# VSS
DDR_SDQ12 1 4 DDR_DQ12 DDR_SDM4 2 1 DDR_DM4 39 40
DDR_SDQ8 DDR_DQ8 DDR_SDM5 DDR_DM5 VSS VSS DDR_SMA3 DDR_SMAA3
2 3 2 1 2 1
R113 10_0402_5% R149 10_0402_5%
DDR_DQ20 41 42 DDR_DQ16
RP31 10_4P2R_0402_5% R107 10_0402_5% DDR_DQ21 DQ16 DQ20 DDR_DQ17
43 DQ17 DQ21 44
DDR_SDQ9 1 4 DDR_DQ9 DDR_SDM6 2 1 DDR_DM6 45 46
DDR_SDQ13 DDR_DQ13 DDR_SDM7 DDR_DM7 DDR_DQS2 VDD VDD DDR_DM2
2 3 2 1 47 DQS2 DM2 48
R118 10_0402_5% DDR_DQ18 49 50 DDR_DQ22 DDR_SMA6 2 1 DDR_SMAA6
DQ18 DQ22 R152 10_0402_5%
51 VSS VSS 52
DDR_DQ23 53 54 DDR_DQ19 DDR_SMA7 2 1 DDR_SMAA7
DDR_DQ28 DQ19 DQ23 DDR_DQ24 R116 10_0402_5%
55 DQ24 DQ28 56
57 58 DDR_SMA8 2 1 DDR_SMAA8
DDR_DQ29 VDD VDD DDR_DQ25 R137 10_0402_5%
59 DQ25 DQ29 60
DDR_DQS3 61 62 DDR_DM3 DDR_SMA9 2 1 DDR_SMAA9
RP21 10_4P2R_0402_5% RP16 10_4P2R_0402_5% DQS3 DM3 R148 10_0402_5%
63 VSS VSS 64
DDR_SDQ11 1 4 DDR_DQ11 DDR_SDQ32 1 4 DDR_DQ32 DDR_DQ31 65 66 DDR_DQ30 DDR_SMA10 2 1 DDR_SMAA10
DDR_SDQ14 DDR_DQ14 DDR_SDQ33 DDR_DQ33 DDR_DQ26 DQ26 DQ30 DDR_DQ27 R146 10_0402_5%
2 3 2 3 67 DQ27 DQ31 68
69 70 DDR_SMA11 2 1 DDR_SMAA11
VDD VDD R151 10_0402_5%
71 CB0 CB4 72
RP40 10_4P2R_0402_5% RP28 10_4P2R_0402_5% 73 74 DDR_SMA12 2 1 DDR_SMAA12
DDR_SDQ15 DDR_DQ15 DDR_SDQ37 DDR_DQ37 CB1 CB5 R136 10_0402_5%
1 4 1 4 75 VSS VSS 76
DDR_SDQ10 2 3 DDR_DQ10 DDR_SDQ36 2 3 DDR_DQ36 77 78
DQS8 DM8
79 CB2 CB6 80
81 VDD VDD 82
2 RP41 10_4P2R_0402_5% RP26 10_4P2R_0402_5% 2
83 CB3 CB7 84
DDR_SDQ21 1 4 DDR_DQ21 DDR_SDQ39 1 4 DDR_DQ39 85 86
DDR_SDQ20 DDR_DQ20 DDR_SDQ34 DDR_DQ34 DU DU/RESET#
2 3 2 3 87 VSS VSS 88
<11> DDR_CLK2 89 CK2 VSS 90
<11> DDR_CLK2# 91 CK2# VDD 92
RP35 10_4P2R_0402_5% RP15 10_4P2R_0402_5% 93 94
DDR_SDQ17 DDR_DQ17 DDR_SDQ35 DDR_DQ35 DDR_CKE1 VDD VDD DDR_CKE0
1 4 1 4 <11> DDR_CKE1 95 CKE1 CKE0 96 DDR_CKE0 <11>
DDR_SDQ16 2 3 DDR_DQ16 DDR_SDQ38 2 3 DDR_DQ38 97 98
DDR_SMAA12 DU/A13 DU/BA2 DDR_SMAA11
99 A12 A11 100
DDR_SMAA9 101 102 DDR_SMAA8
RP44 10_4P2R_0402_5% RP27 10_4P2R_0402_5% A9 A8
103 VSS VSS 104 Layout note
DDR_SDQ23 1 4 DDR_DQ23 DDR_SDQ45 1 4 DDR_DQ45 DDR_SMAA7 105 106 DDR_SMAA6
DDR_SDQ18 DDR_DQ18 DDR_SDQ44 DDR_DQ44 DDR_SMA5 A7 A6 DDR_SMA4
2 3 2 3 107 A5 A4 108 Place these resistor
DDR_SMAA3 109 110 DDR_SMA2
DDR_SMA1 A3 A2 DDR_SMAA0 close by DIMM0,
111 A1 A0 112
RP34 10_4P2R_0402_5% RP17 10_4P2R_0402_5% 113 114 all trace length
DDR_SDQ19 DDR_DQ19 DDR_SDQ40 DDR_DQ40 DDR_SMAA10 VDD VDD DDR_BS1
1 4 1 4 115 A10/AP BA1 116 Max=1.4"
DDR_SDQ22 2 3 DDR_DQ22 DDR_SDQ41 2 3 DDR_DQ41 DDR_BS0 117 118 DDR_RAS#
DDR_WE# BA0 RAS# DDR_CAS#
119 WE# CAS# 120
DDR_SCS#0 121 122 DDR_SCS#1
<11> DDR_SCS#0 S0# S1# DDR_SCS#1 <11>
RP45 10_4P2R_0402_5% RP29 10_4P2R_0402_5% 123 124
DDR_SDQ29 DDR_DQ29 DDR_SDQ47 DDR_DQ47 DU DU +1.25VS
1 4 1 4 125 VSS VSS 126
DDR_SDQ28 2 3 DDR_DQ28 DDR_SDQ46 2 3 DDR_DQ46 DDR_DQ36 127 128 DDR_DQ33
DDR_DQ37 DQ32 DQ36 DDR_DQ32
129 DQ33 DQ37 130
131 VDD VDD 132
RP38 10_4P2R_0402_5% RP22 10_4P2R_0402_5% DDR_DQS4 133 134 DDR_DM4 RP47
DDR_SDQ25 DDR_DQ25 DDR_SDQ42 DDR_DQ42 DDR_DQ34 DQS4 DM4 DDR_DQ38 DDR_CKE0 1
1 4 1 4 135 DQ34 DQ38 136 4
DDR_SDQ24 2 3 DDR_DQ24 DDR_SDQ43 2 3 DDR_DQ43 137 138 DDR_CKE1 2 3
DDR_DQ39 VSS VSS DDR_DQ35
139 DQ35 DQ39 140
DDR_DQ44 141 142 DDR_DQ41 56_4P2R_0402_5%
DQ40 DQ44
143 VDD VDD 144
DDR_DQ45 145 146 DDR_DQ40
3 DDR_DQS5 DQ41 DQ45 DDR_DM5 3
147 148 RP49
DQS5 DM5 DDR_SCS#1 1
149 VSS VSS 150 4
DDR_DQ46 151 152 DDR_DQ43 DDR_SCS#0 2 3
DDR_SDQ[0..63] RP30 10_4P2R_0402_5% DDR_DQ47 DQ42 DQ46 DDR_DQ42
<11> DDR_SDQ[0..63] 153 DQ43 DQ47 154
DDR_SDQ49 1 4 DDR_DQ49 155 156 56_4P2R_0402_5%
DDR_SDQS[0..7] DDR_SDQ52 DDR_DQ52 VDD VDD
<11> DDR_SDQS[0..7] 2 3 157 VDD CK1# 158 DDR_CLK1# <11>
159 VSS CK1 160 DDR_CLK1 <11>
DDR_SMA[0..12] 161 162
<11,14> DDR_SMA[0..12] VSS VSS
RP18 10_4P2R_0402_5% DDR_DQ52 163 164 DDR_DQ53
DDR_SDM[0..7] DDR_SDQ48 DDR_DQ48 DDR_DQ49 DQ48 DQ52 DDR_DQ48
<11> DDR_SDM[0..7] 1 4 165 DQ49 DQ53 166
DDR_SDQ53 2 3 DDR_DQ53 167 168
DDR_DQS6 VDD VDD DDR_DM6
169 DQS6 DM6 170
DDR_DQ50 171 172 DDR_DQ55
RP51 10_4P2R_0402_5% RP25 10_4P2R_0402_5% DQ50 DQ54
173 VSS VSS 174
DDR_SDQ57 1 4 DDR_DQ57 DDR_SDQ51 1 4 DDR_DQ51 DDR_DQ51 175 176 DDR_DQ54
DDR_SDQ61 DDR_DQ61 DDR_SDQ50 DDR_DQ50 DDR_DQ56 DQ51 DQ55 DDR_DQ61
2 3 2 3 177 DQ56 DQ60 178
179 VDD VDD 180
DDR_DQ60 181 182 DDR_DQ57
RP50 10_4P2R_0402_5% RP23 10_4P2R_0402_5% DDR_DQS7 DQ57 DQ61 DDR_DM7
183 DQS7 DM7 184
DDR_SDQ60 1 4 DDR_DQ60 DDR_SDQ54 1 4 DDR_DQ54 185 186
DDR_SDQ56 DDR_DQ56 DDR_SDQ55 DDR_DQ55 DDR_DQ58 VSS VSS DDR_DQ59
2 3 2 3 187 DQ58 DQ62 188
DDR_DQ63 189 190 DDR_DQ62
DQ59 DQ63 DDR_BS0
191 VDD VDD 192 <11,14> DDR_SBS0 2 1
RP36 10_4P2R_0402_5% RP39 10_4P2R_0402_5% 193 194 R139 10_0402_5%
<14,16,20,28> DIMM_SMDATA SDA SA0
DDR_SDQ63 1 4 DDR_DQ63 DDR_SDQ62 1 4 DDR_DQ62 195 196 2 1 DDR_BS1
<14,16,20,28> DIMM_SMCLK SCL SA1 <11,14> DDR_SBS1
DDR_SDQ58 2 3 DDR_DQ58 DDR_SDQ59 2 3 DDR_DQ59 197 198 R133 10_0402_5%
+3VS VDD_SPD SA2 DDR_RAS#
199 VDD_ID DU 200 <11,14> DDR_SRAS# 2 1
R141 10_0402_5%
2 1 DDR_CAS#
<11,14> DDR_SCAS#
JAE MM50-200B1-1R_200P_Reverse R131 10_0402_5%
2 1 DDR_WE#
<11,14> DDR_SWE#
R138 10_0402_5%
4 DDR_SDQS0 DDR_DQS0 DDR_SDQS4 DDR_DQS4 4
2 1 2 1
R124 10_0402_5% R108 10_0402_5% Layout note
DDR_SDQS1 2 1 DDR_DQS1 DDR_SDQS5 2 1 DDR_DQS5 Place these resistors
R109 10_0402_5% R106 10_0402_5%
DDR_SDQS2 DDR_DQS2 DDR_SDQS6 DDR_DQS6 close to DIMM0,
2 1 2 1
R120 10_0402_5% R115 10_0402_5% all trace length<500 mil Dell-Compal Confidential
DDR_SDQS3 2 1 DDR_DQS3 DDR_SDQS7 2 1 DDR_DQS7
R121 10_0402_5% R129 10_0402_5% Compal Electronics, Inc.
DDR TOPOLOGY 2 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
Title
DDR-SODIMM SLOT0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 13 of 44
A B C D E F G H
 A B C D E

+2.5V +2.5V
+1.25VS +1.25VS SDREF_DIMM
JP23
1 VREF VREF 2
RP89 RP83 RP69 3 4 1
DDR_DQ4 DDR_DQ29 DDR_DQS6 DDR_DQ5 VSS VSS DDR_DQ4
1 4 4 1 4 1 5 DQ0 DQ4 6
DDR_DQ1 2 3 3 2 DDR_DQS3 3 2 DDR_DQ50 DDR_DQ2 7 8 DDR_DQ1 C488
DQ1 DQ5 0.1U_0402_16V4Z
9 VDD VDD 10
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQS0 DDR_DM0 2
11 DQS0 DM0 12
RP109 RP103 RP94 DDR_DQ0 13 14 DDR_DQ3
DDR_DQ5 DQ2 DQ6
1 4 4 1 DDR_DQ25 4 1 DDR_DQ61 15 VSS VSS 16
DDR_DQ2 2 3 3 2 DDR_DM3 3 2 DDR_DQ57 DDR_DQ6 17 18 DDR_DQ7
DDR_DQ8 DQ3 DQ7 DDR_DQ13 +1.25VS
19 DQ8 DQ12 20
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% 21 22
RP88 DDR_DQ12 VDD VDD DDR_DQ9
RP82 RP68 23 24
1 DDR_DM0 DQ9 DQ13 1
1 4 4 1 DDR_DQ31 4 1 DDR_DQ51 DDR_DQS1 25 DQS1 DM1 26 DDR_DM1
DDR_DQ3 2 3 3 2 DDR_DQ26 3 2 DDR_DQ56 27 28 1 2 DDR_SMA12
DDR_DQ14 VSS VSS DDR_DQ10 R128 56_0402_5%
29 DQ10 DQ14 30
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQ11 31 32 DDR_DQ15
DQ11 DQ15 RP48 56_4P2R_0402_5%
RP111 RP93 33 34
DDR_DQS0 1 RP108 VDD VDD
4 4 1 DDR_DQ30 4 1 DDR_DQ59 <11> DDR_CLK3 35 CK0 VDD 36 4 1 DDR_SMA11
DDR_DQ0 2 3 3 2 DDR_DQ27 3 2 DDR_DQ62 37 38 3 2 DDR_SMA9
<11> DDR_CLK3# CK0# VSS
39 VSS VSS 40
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5%
RP87 RP75 RP66 RP81 56_4P2R_0402_5%
DDR_DQ7 1 4 4 1 DDR_DQ36 4 1 DDR_DQ60 DDR_DQ20 41 42 DDR_DQ16 4 1 DDR_SMA7
DDR_DQ13 2 DQ16 DQ20
3 3 2 DDR_DQ37 3 2 DDR_DQS7 DDR_DQ21 43 DQ17 DQ21 44 DDR_DQ17 3 2 DDR_SMA8
45 VDD VDD 46
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQS2 47 48 DDR_DM2
DDR_DQ18 DQS2 DM2 DDR_DQ22 RP78 56_4P2R_0402_5%
RP107 RP100 RP53 49 50
DDR_DQ6 DQ18 DQ22
1 4 4 1 DDR_DQ33 4 1 DDR_DQ58 51 VSS VSS 52 4 1 DDR_SMA6
DDR_DQ8 2 3 3 2 DDR_DQ32 3 2 DDR_DQ63 DDR_DQ23 53 54 DDR_DQ19 3 2 DDR_SMA3
DDR_DQ28 DQ19 DQ23 DDR_DQ24
55 DQ24 DQ28 56
56_4P2R_0402_5% 56_4P2R_0402_5% 56_4P2R_0402_5% 57 58
DDR_DQ29 VDD VDD DDR_DQ25 RP77 56_4P2R_0402_5%
RP86 RP74 59 60
DDR_DQ9 DQ25 DQ29
1 4 4 1 DDR_DQS4 1 2 DDR_DM4 DDR_DQS3 61 DQS3 DM3 62 DDR_DM3 4 1 DDR_SMA10
DDR_DM1 2 3 3 2 DDR_DQ34 R179 56_0402_5% 63 64 3 2 DDR_SMA0
DDR_DM5 DDR_DQ31 VSS VSS DDR_DQ30
1 2 65 DQ26 DQ30 66
56_4P2R_0402_5% 56_4P2R_0402_5% R180 56_0402_5% DDR_DQ26 67 68 DDR_DQ27
DQ27 DQ31
RP92 RP99 69 70
DDR_DQ12 1 VDD VDD
4 4 1 DDR_DQ38 1 2 DDR_DM6 71 CB0 CB4 72
DDR_DQS1 2 3 3 2 DDR_DQ35 R177 56_0402_5% 73 74 2 1 DDR_SMA1
DDR_DM7 CB1 CB5 R323 56 _0402_1%
1 2 75 VSS VSS 76
56_4P2R_0402_5% 56_4P2R_0402_5% R181 56_0402_5% 77 78 2 1 DDR_SMA2
DQS8 DM8 R182 56 _0402_1%
RP67 RP73 79 80
DDR_DQ14 1 CB2 CB6
4 4 1 DDR_DQ39 81 VDD VDD 82
DDR_DQ11 2 3 3 2 DDR_DQ44 83 84
2 CB3 CB7 RP102 56_4P2R_0402_5% 2
85 DU DU/RESET# 86
56_4P2R_0402_5% 56_4P2R_0402_5% 87 88 4 1 DDR_SMAB1
VSS VSS
RP91 RP98 <11> DDR_CLK5 89 CK2 VSS 90 3 2 DDR_SMAB2
DDR_DQ10 1 4 4 1 DDR_DQ41 91 92
<11> DDR_CLK5# CK2# VDD
DDR_DQ15 2 3 3 2 DDR_DQ40 93 94
DDR_CKE3 VDD VDD DDR_CKE2 RP55 56_4P2R_0402_5%
<11> DDR_CKE3 95 CKE1 CKE0 96 DDR_CKE2 <11>
56_4P2R_0402_5% 56_4P2R_0402_5% 97 98 4 1 DDR_SMA4
DDR_SMA12 DU/A13 DU/BA2 DDR_SMA11
RP110 RP72 99 A12 A11 100 3 2 DDR_SMA5
DDR_DQ20 1 4 4 1 DDR_DQ45 DDR_SMA9 101 102 DDR_SMA8
DDR_DQ21 2 A9 A8
3 3 2 DDR_DQS5 103 VSS VSS 104
DDR_SMA7 105 106 DDR_SMA6 RP54 56_4P2R_0402_5%
56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQS[0..7] DDR_SMAB5 A7 A6 DDR_SMAB4
DDR_DQS[0..7] <13> 107 A5 A4 108 4 1 DDR_SMAB4
RP106 RP97 DDR_SMA3 109 110 DDR_SMAB2 3 2 DDR_SMAB5
DDR_DQ16 1 DDR_DQ[0..63] A3 A2
4 4 1 DDR_DQ43 DDR_DQ[0..63] <13>
DDR_SMAB1 111 A1 A0 112 DDR_SMA0
DDR_DQ17 2 3 3 2 DDR_DQ42 113 114
DDR_SMA[0..12] DDR_SMA10 VDD VDD DDR_SBS1 RP80 56_4P2R_0402_5%
DDR_SMA[0..12] <11,13> 115 A10/AP BA1 116 DDR_SBS1 <11,13>
56_4P2R_0402_5% 56_4P2R_0402_5% <11,13> DDR_SBS0 DDR_SBS0 117 118 DDR_SRAS# 4 1 DDR_SWE#
DDR_DM[0..7] BA0 RAS# DDR_SRAS# <11,13>
RP85 RP71 <11,13> DDR_SWE# DDR_SWE# 119 120 DDR_SCAS# 3 2 DDR_SBS0
DDR_DM[0..7] <13> WE# CAS# DDR_SCAS# <11,13>
DDR_DQS2 1 4 4 1 DDR_DQ46 DDR_SCS#2 121 122 DDR_SCS#3
<11> DDR_SCS#2 S0# S1# DDR_SCS#3 <11>
DDR_DQ18 2 3 3 2 DDR_DQ47 123 124
DU DU RP76 56_4P2R_0402_5%
125 VSS VSS 126
56_4P2R_0402_5% 56_4P2R_0402_5% DDR_DQ36 127 128 DDR_DQ33 4 1 DDR_SRAS#
DDR_DQ37 DQ32 DQ36 DDR_DQ32
RP105 RP96 129 DQ33 DQ37 130 3 2 DDR_SCAS#
DDR_DM2 1 4 4 1 DDR_DQ53 131 132
DDR_DQ22 2 VDD VDD
3 3 2 DDR_DQ48 DDR_DQS4 133 DQS4 DM4 134 DDR_DM4
DDR_DQ34 135 136 DDR_DQ38
56_4P2R_0402_5% 56_4P2R_0402_5% DQ34 DQ38
137 VSS VSS 138 1 2 DDR_SBS1
RP84 RP70 DDR_DQ39 139 140 DDR_DQ35 R358 56_0402_5%
DDR_DQ23 1 DQ35 DQ39
4 4 1 DDR_DQ52 <11> DDR_SMAB1
DDR_SMAB1 DDR_DQ44 141 DQ40 DQ44 142 DDR_DQ41
DDR_DQ28 2 3 3 2 DDR_DQ49 143 144
DDR_DQ45 VDD VDD DDR_DQ40
145 DQ41 DQ45 146
56_4P2R_0402_5% 56_4P2R_0402_5% DDR_SMAB2 DDR_DQS5 147 148 DDR_DM5
3 <11> DDR_SMAB2 DQS5 DM5 3
RP104 RP95 149 150
DDR_DQ19 1 VSS VSS
4 4 1 DDR_DQ55 DDR_DQ46 151 DQ42 DQ46 152 DDR_DQ43
DDR_DQ24 2 3 3 2 DDR_DQ54 DDR_SMAB4 DDR_DQ47 153 154 DDR_DQ42
<11> DDR_SMAB4 DQ43 DQ47
155 VDD VDD 156
56_4P2R_0402_5% 56_4P2R_0402_5% 157 158
VDD CK1# DDR_CLK4# <11>
DDR_SMAB5 159 160
<11> DDR_SMAB5 VSS CK1 DDR_CLK4 <11>
161 VSS VSS 162
Layout note DDR_DQ52 163 164 DDR_DQ53 +1.25VS
DDR_DQ49 DQ48 DQ52 DDR_DQ48
165 DQ49 DQ53 166
Place these resistor 167 VDD VDD 168
DDR_DQS6 169 170 DDR_DM6
closely DIMM1, DDR_DQ50 DQS6 DM6 DDR_DQ55 RP79
171 DQ50 DQ54 172
all trace 173 174 DDR_CKE3 1 4
DDR_DQ51 VSS VSS DDR_DQ54 DDR_CKE2 2
length<=800mil 175 DQ51 DQ55 176 3
DDR_DQ56 177 178 DDR_DQ61
DQ56 DQ60 56_4P2R_0402_5%
179 VDD VDD 180
DDR_DQ60 181 182 DDR_DQ57
DDR_DQS7 DQ57 DQ61 DDR_DM7
183 184 RP101
DQS7 DM7 DDR_SCS#2 1
185 VSS VSS 186 4
DDR_DQ58 187 188 DDR_DQ59 DDR_SCS#3 2 3
DDR_DQ63 DQ58 DQ62 DDR_DQ62
189 DQ59 DQ63 190
PAD1 PAD2 PAD3 PAD4 191 192 56_4P2R_0402_5%
VDD VDD
<13,16,20,28> DIMM_SMDATA 193 SDA SA0 194 +3VS
1 1 1 1 <13,16,20,28> DIMM_SMCLK 195 SCL SA1 196 Layout note
+3VS 197 VDD_SPD SA2 198
199 VDD_ID DU 200 Place these resistor
PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3
EMI Clip PAD for Memory Door close by DIMM1,
JAE MM50-200B1-1 200P_Normal all trace length
Max=0.8"
PAD12 PAD11 PAD14
PAD16 PAD17
4 4
1 1 1
1 1

PAD-2.5X3 PAD-2.5X3 PAD-2.5X3

PAD-2.5X3 PAD-2.5X3
DDR TOPOLOGY 2 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
Dell-Compal Confidential
PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 Compal Electronics, Inc.
1 1 1 1 1 1 Title
DDR-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 14 of 44
A B C D E
 A B C D E

Layout note : Layout note :

Distribute as close as possible Distribute as close as possible
to DDR-SODIMM0. to DDR-SODIMM1.

+2.5V +2.5V

1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
+ C170 C194 C185 C183 C189 C184 C182 C186 C190
1 + C135 C418 C419 C415 C420 C423 C422 C421 C414 150U_D2_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 1
150U_D2_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C164 C167 C166 C162 C160 C157 C158 C168 C169 C177 C172 C173 C179 C175 C176 C181 C180 C187
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 1
C789
+ + C790
150U_D2_6.3VM 150U_D2_6.3VM
2 2

Layout note :
Place one cap close to every 2 pull up resistors termination to
2 +1.25VS 2
+1.25VS

1 1 1 1 1 1 1 1 1 1
C527 C528 C529 C530 C518 C531 C532 C533 C515 C534
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1 1 1 1 1
C535 C536 C512 C537 C538 C539 C522 C511 C521 C513
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1
C520 C514 C516 C517 C503 C519
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
3 2 2 2 2 2 2 3

+1.25VS

1 1 1 1 1 1 1 1 1 1
C509 C510 C508 C507 C504 C502 C501 C497 C495 C496
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

1 1 1 1 1 1 1 1 1 1
C494 C540 C526 C525 C524 C543 C141 C188 C192 C506
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2

+1.25VS

4 4
1 1 1 1 1 1
C137 C178 C191 C139 C138 C505
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2
Dell-Compal Confidential
Compal Electronics, Inc.
Title
DDR SODIMM Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 15 of 44
A B C D E
 A B C D E F G H

+3VS L26 +3V_CLK

KC FBM-L11-201209-221LMAT_0805
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1
L21 +3V_48M
BLM21A601SPT_0805 C325 C264 C42 C43 C44 C59 C58 C61 C306
+3VS 1 2 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2
1 1 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 C243 C244 1
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2

14
19
32
37
46
50
1
8
U75
BLM21A601SPT_0805

VDD_PCI_0
VDD_PCI_1
VDD_3V66_0
VDD_3V66_1

VDD_CPU_0
VDD_CPU_1
VDD_REF

VDD_48MHZ
L23 +3VS
C310 @10P_0402_50V8K
1 2 XTALIN 2 26 +3V_VDD 1 2
+3VS XTAL_IN VDDA

1
1 1
+3VS X2 C303

1
C312
R24 14.31818MHZ_20P 0.1U_0402_16V4Z 10U_1206_10V4Z

2
1

1K_0402_5% 2 2
R19 1 2 XTALOUT 3 27
1K_0402_5% C272 @10P_0402_50V8K XTAL_OUT VSSA
2

45 CPU_BCLK 1 2
CPUCLKT2 CLK_CPU_BCLK <5>
R463 54 R225 27.4_0603_1%
2

H_SEL0 SEL0 R218 49.9_0603_1%

<6> H_BSEL0 2 1 55 SEL1
0_0402_5% 1 2 40 1 2
R213 1K_0402_5% SEL2
1 2
R219 49.9_0603_1%

CLK_PWD# 25 44 CPU_BCLK# 1 2
PWR_DWN# CPU_CLKC2 CLK_CPU_BCLK# <5>
34 R226 27.4_0603_1%
<21> PM_STPPCI# PCI_STOP#
53 49 MCH_BCLK 1 2
<21,41> PM_STPCPU# CPU_STOP# CPUCLKT1 CLK_MCH_BCLK <9>
R223 27.4_0603_1%
R242 R216 49.9_0603_1%
+3VS 1 2 1 2
10K_0402_5% 28 1 2
VTT_PWRGD# R217 49.9_0603_1%
1

C
2 Q25 R232 MCH_BCLK# 2
+CPU_CORE 1 2 2 CPUCLKC1 48 1 2 CLK_MCH_BCLK# <9>
B 2SC2411K_SOT23 1 2 43 R224 27.4_0603_1%
R238 E +3VS 10K_0402_5% MULT0 CPU_ITP
52 1 2 CLK_CPU_ITP <6>
3

220_0402_5% CPUCLKT0 R228 27.4_0603_1%

2 1
R221 @1K_0603_1% R227 49.9_0603_1%
<13,14,20,28> DIMM_SMDATA 29 SDATA 1 2
<13,14,20,28> DIMM_SMCLK 30 SCLK 1 2
R220 49.9_0603_1%

51 CPU_ITP# 1 2 CLK_CPU_ITP# <6>

CPUCLKC0 R222 27.4_0603_1%
33 3V66_0
R542 1 2 33_0402_5%CLK_VCH66 35 24
<10> CLK_VCH 3V66_1/VCH_CLK 3V66_5

23 AGP_66M R255 1 2 33_0402_5% CLK_AGP_66M <17>

R20 3V66_4 MCH_66M
1 2 475_0603_1% 42 IREF 3V66_3 22 R254 1 2 33_0402_5%
CLK_MCH_66M <10>
21 ICH_66M R253 1 2 33_0402_5%
3V66_2 CLK_ICH_66M <20>

R230 1 2 33_0402_5% ICH_48M 39 7 PCI_ICH R248 1 2 33_0402_5%

<21> CLK_ICH_48M 48MHZ_USB PCICLK_F2 CLK_PCI_ICH <20>
PCICLK_F1 6
PCICLK_F0 5

R231 1 2 33_0402_5% MCH_DISPLAY 38

<10> CLK_MCH_DISPLAY 48MHZ_DOT
PCICLK6 18
17 PCI_DEBUG R457 1 2 @33_0402_5%
PCICLK5 CLK_PCI_DEBUG <35>
16 PCI_LAN R252 1 2 33_0402_5%
PCICLK4 CLK_PCI_LAN <24>
R236 1 2 33_0402_5% ICH_14M 56 13 PCI_PCM R251 1 2 33_0402_5%
<21> CLK_ICH_14M REF PCICLK3 CLK_PCI_PCM <25,27>
12 PCI_MINI R250 1 2 33_0402_5%
PCICLK2 CLK_PCI_MINI <28>
GND_3V66_0
GND_3V66_1
GND_48MHZ

R235 1 2 33_0402_5% 11 PCI_LPC R249 1 2 33_0402_5%

GND_PCI_0
GND_PCI_1

<29> CLK_CODEC_14M PCICLK1 CLK_PCI_LPC <32>

GND_IREF
GND_CPU
GND_REF

PCICLK0 10
3 3
1 1 1 1 1
C247 C248 C313 C315
@10P_0402_50V8K @10P_0402_50V8K ICS950810CG_TSSOP56 @10P_0402_50V8K @10P_0402_50V8K
4
9
15
20
31
36
41
47

2 2 2 2 2

C314
@10P_0402_50V8K

+3V

CPU Frequency Select Table

5

1 2
SEL[2:0] CK-408 Speed 1 R355 @0_0402_5%
P

<21,32> PM_SLP_S3# IN1

4 1 2 CLK_PWD#
O R356 0_0402_5%
<21,32> PM_SLP_S1# 2 IN2
G

001 100 MHZ

SN74AHC1G08HDCK_TSSOP5
3

U79
* 011 133 MHZ

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title
Clock Generator
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 16 of 44
A B C D E F G H
 A B C D E

AGP_ST[0..2]
<10> AGP_ST[0..2] +1.5VS +12VALW +5VS +5VALW
B+ B+ +2.5V +2.5V +3VS
AGP_SBA[0..7]
<10> AGP_SBA[0..7]

1
AGP_AD[0..31]
<10> AGP_AD[0..31]
C127 C806 C241 C240 C369 C242 C372 + C355 C239
AGP_CBE#[0..3] .1U_0402_16V4Z .1U_0603_50V4Z .1U_0603_50V4Z .1U_0402_16V4Z .1U_0402_16V4Z .1U_0402_16V4Z .1U_0402_16V4Z 150U_D_6.3VM .1U_0402_16V4Z
<10> AGP_CBE#[0..3]

2
2
JP8
1
1 2 +1.5VS 1
GND GND +3VALW
+2.5V 3 3 4 4 +5VS
5 5 6 6
7 7 8 8 R229

1
9 9 10 10
11 12 EXTVGA_IN# 2 1 R240
11 12 +AGPREF AGP_NBREF 1K_0603_1%
13 13 14 14
15 16 100K_0402_5%
AGP_RST# 15 16
17 18 AGP_ADSTB0 <10>

2
AGP_CBE#0 17 18
19 19 20 20 AGP_ADSTB0# <10> 1 2
21 GND GND 22

1
AGP_AD1 23 24 AGP_AD0 +3VS R243 1@0_0603_5%
23 24

1
AGP_AD3 25 26 AGP_AD2 R239 C273
AGP_AD5 25 26 AGP_AD4 R166 POP for INT VGA 1K_0603_1% .1U_0402_16V4Z
27 27 28 28
AGP_AD7 29 30 AGP_AD6 2 1

2
29 30 DEPOP for EXT VGA
31 32

2
AGP_AD9 31 32 AGP_AD8 @0_0402_5%
33 33 34 34
AGP_AD11 35 36 AGP_AD10
35 36

5
AGP_AD13 37 38 AGP_AD12 U36
AGP_AD15 37 38 AGP_AD14
39 40 1

P
39 40 IN1 SUS_STAT# <21,32>
41 42 STP_AGP# 4
AGP_FRAME# GND GND AGP_CBE#1 O
<10> AGP_FRAME# 43 43 44 44 IN2 2 PM_C3_STAT# <21>

G
45 46 AGP_IRDY#
<10> AGP_PAR 45 46 AGP_IRDY# <10>
AGP_TRDY# 47 48 AGP_DEVSEL# 2@SN74AHC1G08HDCK_TSSOP5
<10> AGP_TRDY# AGP_DEVSEL# <10>

3
AGP_STOP# 47 48
<10> AGP_STOP# 49 49 50 50 AGP_PIPE# <10>
AGP_AD17 51 52
AGP_AD19 51 52 AGP_AD16
53 53 54 54
AGP_AD21 55 56 AGP_AD18 +3VALW
AGP_AD23 55 56 AGP_AD20
57 57 58 58 V_PRST# <25,26,27>
AGP_CBE#2 59 60 AGP_AD22
59 60

14
61 GND GND 62
AGP_ADSTB1 63 64 AGP_AD24 U33A
2 <10> AGP_ADSTB1 63 64 2
AGP_ADSTB1# 65 66 AGP_AD26 1

P
<10> AGP_ADSTB1# 65 66 <32> G_RST# A
67 68 AGP_AD28 3 1 2
AGP_AD25 67 68 AGP_AD30 O
69 69 70 70 <6,10,20,24,25,27,28,32,35> PCIRST# 2 B

G
AGP_AD27 71 72 R290 @0_0402_5%
AGP_AD29 71 72 SN74LVC32APWLE_TSSOP14
73 74 PIRQE# <20>

7
AGP_AD31 73 74
75 75 76 76
AGP_CBE#3 77 78 R282 0_0402_5%
77 78 AGP_SBSTB <10>
EXTVGA_IN# 79 80 1 2 AGP_RST#
<32> EXTVGA_IN# 79 80 AGP_SBSTB# <10>
81 GND GND 82
AGP_SBA7 83 84 AGP_SBA6
AGP_SBA5 85
83
85
84
86 86 AGP_SBA4 AGP_RST# = PCI_RST#
AGP_SBA3 87 88 AGP_SBA2
AGP_SBA1 87 88 AGP_SBA0
89 89 90 90
91 91 92 92
93 94 AGP_ST0
<10> AGP_RBF# 93 94
95 96 AGP_ST1
<10> AGP_WBF# 95 96
97 98 AGP_ST2
97 98
99 GND GND 100
<10> AGP_REQ# 101 101 102 102 BKOFF# <18,32>
<10> AGP_GNT# 103 103 104 104 ENABKL <10,18,33>
<18,21> PID3 105 105 106 106 PID0 <18,21>
STP_AGP# 107 108
107 108 PID1 <18,21>
<29,32,35,38,40> SUSP# 109 109 110 110 SMB_EC_DA1 <18,32,33,36>
111 112 +1.5VS
111 112 SMB_EC_CK1 <18,32,33,36>
<16> CLK_AGP_66M 113 113 114 114 PID2 <18,21>
115 115 116 116 AGP_NBREF

1
C/R 117 118
<19> C/R 117 118 +AGPREF
1

119 120 R543

R17 Y/G GND GND 2@1K_0402_5%
<19> Y/G 121 121 122 122
1@33_0402_5% 123 124 CRT_B
123 124 CRT_B <19>
COMP/B 125 126
<19> COMP/B

2
125 126
127 128 H: AGP L: DVO
2

3 127 128 CRT_G AGP_PAR 3

<10,21> AGP_BUSY# 129 129 130 130 CRT_G <19>
1 M_SEN# 131 132 DVO Detect
<19,33> M_SEN# 131 132
C33 133 134 AGP_PAR internal pull low
1@10P_0402_25V8K 133 134 CRT_R
135 135 136 136 CRT_R <19>
CRT_VSYNC 137 138
2 <19> CRT_VSYNC 137 138
139 140 +1.5VS
GND GND
141 141 142 142
CRT_HSYNC 143 144 +3V R544 [email protected]_0402_5%
<19> CRT_HSYNC 143 144
145 146 AGP_IRDY# 1 2
145 146 R545 [email protected]_0402_5%
147 147 148 148 +3VS
3VDDCDA 149 150 AGP_TRDY# 1 2
<19> 3VDDCDA 149 150
151 152 R546 [email protected]_0402_5%
151 152 AGP_STOP#
153 153 154 154 1 2
3VDDCCK 155 156 R547 [email protected]_0402_5%
<19> 3VDDCCK 155 156
157 158 AGP_AD15 1 2
157 158 R548 [email protected]_0402_5%
159 GND GND 160
161 162 AGP_DEVSEL# 1 2
+5VALW 161 162
163 164 B+ R549 [email protected]_0402_5%
163 164 AGP_FRAME#
165 165 166 166 1 2
167 167 168 168
+1.5VS 169 169 170 170
171 171 172 172
173 173 174 174 +12VALW
175 175 176 176
177 177 178 178
179 GND GND 180

2@FOXCONN_QT00180A-5120C

4 4

R550
1 2 CRT_VSYNC R551
<10> INT_VSYNC
1@0_0603_5% CRT_B 1 2
R552 1@0_0603_5%
INTCRT_B <10> 1: internal graphic Dell-Compal Confidential
1 2 CRT_HSYNC R553 * EXTVGA_IN#
<10> INT_HSYNC
1@0_0603_5% CRT_G 2: external AGP
R554
1 2
1@0_0603_5%
INTCRT_G <10>
Title
Compal Electronics, Inc.
1 2 3VDDCDA R555
<10> INTDDCDA
1@0_0603_5% CRT_R 1 2 INTCRT_R <10> External AGP
R556 1@0_0603_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
1 2 3VDDCCK
<10> INTDDCCK AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
1@0_0603_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 17 of 44
A B C D E
 5 4 3 2 1

D D

JP31
45 44 +12VALW +LCDVDD +3VS
MGND1 TXLOUT0- LCD_A0- <10>
46 43 Q70
MGND2 TXLOUT0+ LCD_A0+ <10> +12VALW
47 MGND3 GND1 42
+LCDVDD

D
48 MGND4 TXLOUT1- 41 LCD_A1- <10> 3 1

1
49 MGND5 TXLOUT1+ 40 LCD_A1+ <10>

1
50 39 R557 1@SI2302DS_SOT23
MGND6 GND2

1
R558 1@100K_0402_5%

G
51 38 LCD_A2- <10>

2
MGND7 TXLOUT2- R559
56 MGND8 TXLOUT2+ 37 LCD_A2+ <10> 1
57 36 1@470_0402_5% 1@100K_0402_5%

2
MGND9 GND3 C791
54 35 LCD_ACLK- <10>

2
MGND10 TXLCLKOUT- [email protected]_0402_16V4Z
55 34 LCD_ACLK+ <10>

2
MGND11 TXLCLKOUT+ 2
GND4 33

1
TXUOUT0- 32 LCD_B0- <10>

1
D D R561
TXUOUT0+ 31 LCD_B0+ <10> 1
30 2 Q72 2 Q73
GND5 G 1@2N7002_SOT23 G
TXUOUT1- 29 LCD_B1- <10>
28 S S 1@150K_0402_5%
LCD_B1+ <10>

2
TXUOUT1+ 1@2N7002_SOT23 2
GND6 27

1
TXUOUT2- 26 LCD_B2- <10>
25 Q75 C794
TXUOUT2+ LCD_B2+ <10>
GND7 24
23 [email protected]_0603_50V4Z
TXUCLKOUT- LCD_BCLK- <10> 22K
TXUCLKOUT+ 22 LCD_BCLK+ <10> <10> ENVDD 2
GND8 21 22K
C C
PANEL_I2C_DAT 20 LCD_DDCDATA <10>
19 1@DTC124EK_SOT23
PANEL_I2C_CLK LCD_DDCCLK <10>
18

3
GND9
VEDID 17 +3VS L51
GND10 16
15 +LCDVCC C796 1 2 +LCDVDD
LCDVCC1 [email protected]_0402_10V6K1 1@FBM-11-201209-300AT_0805
LCDVCC2 14 1
13 C797
PID0 PID0 <17,21>
12 [email protected]_0402_10V6K +LCDVCC
PID1 PID1 <17,21>
PID2 11 PID2 <17,21> 1
2 2
PID3 10 PID3 <17,21>
9 BACKLITE_ON C798
FPBACK [email protected]_1206_10V7K
5VSUS 8 +5VS 2
5VALW 7 +5VALW
PBAT_SMBCLK 6 SMB_EC_CK1 <17,32,33,36>
PBAT_SMBDAT 5 SMB_EC_DA1 <17,32,33,36> 1
GND12 4
3 C799
GND11 [email protected]_0402_10V6K
B+ 2
2
B+ 1 L52
INVER_B+ 1 2 INVPWR_B+
1@JAE_FI-TD44SB-L 1@FBM-11-201209-300AT_0805
1
C800
0.1U_0603_50V4Z
2 Q71
INVPWR_B+
B+ 1@FDS4435_SO8
60mil 60mil
1 8
B B
2 7
3 6
5 1

1
1
C793 R560 C792

4
1@100K_0402_5% [email protected]_0603_50V4Z
[email protected]_0603_50V4Z 2
+3VS 2

2
5

Q74
1
P

IN1 ENABKL <10,17,33> 1@2N7002_SOT23

BACKLITE_ON 4 O R562
IN2 2 BKOFF# <17,32>
G

S
1 2 1 3
1@SN74AHC1G08HDCK_TSSOP5
3

U80 +5VS 1@75K_0402_5%

G
2
1
C795
[email protected]_0402_16V4Z+5VS
2 FDS4435: P CHANNAL

A A

Dell-Compal Confidential
Compal Electronics, Inc.
Title
Internal LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 18 of 44
5 4 3 2 1
 5 4 3 2 1

C236
2@33P_0402_50V8J
1 2

C/R 1 2
<17> C/R
L18
2@FLM1608081R8K_0603 2

1
1
D R203 C221 D
2@75_0603_1% C227 2@270P_0603_50V8J
2@100P_0402_50V8J 1
2

2
C233
2@33P_0402_50V8J
1 2 JP3
3
SVIDEO_C 6
7
COMP/B 1 2 SVIDEO_CVBS 5
<17> COMP/B
L19 2
2@FLM1608081R8K_0603 4
2 1

1
1 SVIDEO_Y 8
R204 C222 9
2@75_0603_1% C225 2@270P_0603_50V8J
2@100P_0402_50V8J 1
2 2@SUYIN_35138S-07T1-01

2
D19 D4 D5
C228 @DAN217_SOT23 @DAN217_SOT23 @DAN217_SOT23

1
2@33P_0402_50V8J
1 2

Y/G 1 2
<17> Y/G

3
L20 +3VS

1
1 2@FLM1608081R8K_0603 2
R205
2@75_0603_1% C226 C220
C 2@100P_0402_50V8J 2@270P_0603_50V8J C
2 1
2

CRTVCC

CRTVCC
+3VS +3VS
1

1
2.7K_0402_5%
C14 R5 R201

1
0.1U_0402_16V4Z 2K_0402_5% 2K_0402_5%
2 R4 R202
0_0402_5% R3 2.7K_0402_5%

2
CRTVCC

2
2
G
DAN217_SOT23 DAN217_SOT23 DAN217_SOT23 1
D1 D18 D3 1 3 3VDDCDA
3VDDCDA <17>

1
M_SEN# C15

S
<17,33> M_SEN#
0.1U_0402_16V4Z

2
@3.3P_0603_50V8J 2 Q14

G
2N7002_SOT23
1 1 1 1 3 3VDDCCK
3VDDCCK <17>
Q23

S
2

3
C3 C219 C4 +3VS 2N7002_SOT23
@3.3P_0603_50V8J @3.3P_0603_50V8J JP1
2 2 2
6
B B
11
CRT_R 1 2 CRTR 1
<17> CRT_R
L2 7
FBM-10-201209-260-T_0805 12
CRT_G 1 2 CRTG 2
<17> CRT_G
L15 8
FBM-10-201209-260-T_0805 13
CRT_B 75_0603_1% 1 2 CRTB 3
+5VS <17> CRT_B
R7 L1 9
1

1K_0402_5% FBM-10-201209-260-T_0805
1 1 1 14
CRTVCC 1 2 4
R1 R195 R2 C2 C214 C1 10
75_0603_1% 75_0603_1% 3.3P_0603_50V8J 3.3P_0603_50V8J 3.3P_0603_50V8J 15
1

2 2 2
5
2

2
5

Q24
SI2303DS_SOT23 FOX_DZ11A91-L8
P

OE#

2 CRT_HSYNC 2 4 1 2 1 2
<35> SUSP <17> CRT_HSYNC A Y L16
G

R459 FBM-11-160808-121-T_0603
3

U13 33_0402_5%
3

1 2
SN74AHCT1G125GW_SOT353-5 CRTVCC L17 1 1 1 1 1 1
FBM-11-160808-121-T_0603
1 C217 C218 C8 C7 C5 C224
27P_0402_50V8J 27P_0402_50V8J 100P_0402_50V8J
C6 2 2 2 2 2 2
0.1U_0402_16V4Z
5

2
R460 100P_0402_50V8J
P

OE#

CRT_VSYNC 2 4 1 2 100P_0402_50V8J
<17> CRT_VSYNC A Y 100P_0402_50V8J
G

33_0402_5%
A U4 A
3

SN74AHCT1G125GW_SOT353-5

Dell-Compal Confidential
Compal Electronics, Inc.
Title
TV OUT & CRT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 19 of 44
5 4 3 2 1
 A B C D

+1.5VS
HUBLink reference Voltage

1
R564
U55A 80.6_0402_1%
AD[0..31]
<24,25,27,28,35> AD[0..31]
ICH4-M

2
AD0 H5 W6 SM_INTRUDER#
AD0 INTRUDER# SM_INTRUDER# <34>
AD1 J3 AC3 SMLINK0 R164 1 2 @0_0402_5% HUB_VSW ING
AD2 AD1 SMLINK0 SMLINK1 R172 1
H3 AD2 SMLINK1 AB1 2 @0_0402_5% 1 1
1 AD3 SMB_CLK C801 C802 1
K1 AD3 SM I/F SMB_CLK AC4

1
AD4 G5 AB4 SMB_DATA 0.01U_0402_25V7Z 0.1U_0402_10V6K
AD5 AD4 SMB_DATA ACIN R565
J4 AD5 SMB_ALERT#/GPI11 AA5 ACIN <32,36,38>
AD6 2 51.1_0603_1%2
H4 AD6
AD7 J5
H_FERR# AD8 AD7
1 R319 2 K2

2
+CPU_CORE 56_0402_5% AD9 AD8 GATEA20 HUB_VREF
G2 AD9 A20GATE Y22 GATEA20 <32>
AD10 L1 AB23 R104 2 1 0_0402_5%
AD10 A20M# H_A20M# <6>

1
AD11 G4 U23 1 1
AD11 DPSLP# H_DPSLP# <6,10>
AD12 L2 AA21 H_FERR# C803 R566 C804
AD12 FERR# H_FERR# <6> 0.01U_0402_25V7Z 0.1U_0402_10V6K
AD13 H2 W21 R110 2 1 0_0402_5%
AD13 IGNNE# H_IGNNE# <6>
AD14 L3 V22 40.2_0603_1%
AD14 INIT# H_INIT# <6> 2 2
AD15 R105 2 1 0_0402_5%
F5 CPU I/F AB22 H_INTR <6>

2
AD16 AD15 INTR R91 2
F4 AD16 NMI V21 1 0_0402_5% H_NMI <6>
AD17 N1 Y23 R103 2 1 0_0402_5%
AD17 CPU_PWRGOOD H_PWRGD <6>
CLK_PCI_ICH AD18 E5 U22 +3VS
AD18 RCIN# KBRST# <32>
AD19 N2 U21 R112 2 1 0_0402_5%
AD19 SLP# H_SLP# <6>
1

AD20 E3 W23 R102 2 1 0_0402_5%

AD20 SMI# H_SMI# <6>
R348 AD21 N3 V23 R101 2 1 0_0402_5% DIMM_SMCLK 1 2
AD21 STPCLK# H_STPCLK# <6>
22_0402_5% AD22 E4 R163 8.2K_0402_5%
AD23 AD22 DIMM_SMDATA
M5 AD23 1 2
AD24 E2 HI[0..10] R162 8.2K_0402_5%
HI[0..10] <9>
2

AD25 AD24 H I0
1 P1 AD25 HI0 L19
AD26 E1 L20 H I1
C480 AD27 AD26 HI1 H I2
P2 AD27 HI2 M19
10P_0402_50V8K AD28 D3 M21 H I3 +3VALW
2 AD29 AD28 HI3 H I4
R1 AD29 HI4 P19
AD30 D2 R19 H I5
AD31 AD30 HI5 H I6 SMB_CLK
P4 T20 1 2

PCI I/F
AD31 HI6 H I7 R353 8.2K_0402_5%
HI7 R20
P23 H I8 SMB_DATA 1 2
C/BE#0 HI8 H I9 R352 8.2K_0402_5%
<24,25,27,28,35> C/BE#0 J2 C/BE#0 HI9 L22
2 C/BE#1 HI10 2
CLK_ICH_66M
<24,25,27,28,35> C/BE#1
C/BE#2
K4
M4
C/BE#1 HUB I/F HI10 N22
K21 1 2
<24,25,27,28,35> C/BE#2 C/BE#2 HI11
C/BE#3 N4 R99 56_0402_5% +3VS
<24,25,27,28,35> C/BE#3 C/BE#3
1

T21 CLK_ICH_66M
CLK66 CLK_ICH_66M <16>
R321 REQ#0 B1
<24> REQ#0 REQ#0
22_0402_5% REQ#1 A2 P21
<28> REQ#1 REQ#1 HI_STB HUB_PSTRB <9>
REQ#2 B3 N20 IRQ14 1 2
<25,27> REQ#2 REQ#2 HI_STB# HUB_PSTRB# <9>
REQ#3 C7 R143 8.2K_0402_5%
2

REQ#4 REQ#3 HUB_RCOMP_ICH 1 IRQ15

1 B6 REQ#4 HICOMP R23 2 +1.5VS 1 2
M23 HUB_VREF R87 48.7_0402_1% R123 8.2K_0402_5%
C395 HUB_VREF HUB_VSW ING
<24> GNT#0 C1 GNT#0 HUB_VSWING R22
15P_0402_50V8J E6 GATEA20 1 2
2 <28> GNT#1 GNT#1
A7 R95 10K_0402_5%
<25,27> GNT#2 GNT#2
B7 J19 APICCLK KBRST# 1 2
GNT#3 APICCLK APICD0 R94 10K_0402_5%
D6 GNT#4 APICD0 H19
K20 APICD1
APICD1

Interrupt I/F
CLK_PCI_ICH P5 D5 PIRQA#
<16> CLK_PCI_ICH PCICLK PIRQA# PIRQA# <25,27>
C2 PIRQB#
PIRQB# PIRQB# <24>
F1 B4 PIRQC#
<24,25,27,28,35> PCI_FRAME# FRAME# PIRQC# PIRQC# <28>
M3 A3 PIRQD#
<24,25,27,28> PCI_DEVSEL# DEVSEL# PIRQD# PIRQD# <28>
L5 C8 PIRQE# RP4
<24,25,27,28> PCI_IRDY# IRDY# PIRQE#/GPI2 PIRQE# <17>
G1 D7 GPI3 GPI4 1 8
<24,25,27,28> PCI_PAR PAR PIRQF#/GPI3
L4 C3 GPI4 GPI3 2 7
<24,25,27,28> PCI_PERR# PERR# PIRQG#/GPI4
RP5 PCI_PLOCK# M2 C4 GPI5 PIRQE# 3 6
PCI_PERR# LOCK# PIRQH#/GPI5 IRQ14 GPI5
1 10 +3VS <32> EC_WAKEUP# W2 PME# IRQ14 AC13 IRQ14 <23> 4 5
REQA# 2 9 PIRQA# ICH_PCIRST# U5 AA19 IRQ15
PCIRST# IRQ15 IRQ15 <23>
PCI_STOP# 3 8 PIRQB# K5 J22 SIRQ 8.2K_8P4R_1206_5%
<24,25,27,28> PCI_SERR# SERR# SERIRQ SIRQ <25,27,32>
PCI_SERR# 4 7 REQ#4 F3
<24,25,27,28> PCI_STOP# STOP#
+3VS 5 6 <24,25,27,28,35> PCI_TRDY# F2 TRDY#
EE_CS D10
8.2K_10P8R_1206_5% REQA# B5 EEPROM I/F D11 R156
REQB# REQA#/GPI0 EE_IN
A6 REQB#/GPI1/REQ5# EE_OUT A8 1 2
3 PIDERST# +3VALW 3
<23> PIDERST# E8 GNTA#/GPO16 EE_SHCLK C12
SIDERST# C5 @1K_0402_5%
<23> SIDERST# GNTB#/GPO17/GNT5#
RP3 SMLINK0 1 2
PCI _IRDY# 1 10 A10 R165
+3VS LAN_RXD0
PCI_TRDY# 2 9 PIRQC# A9 8.2K_0402_5%
PCI_DEVSEL# PIRQD# LAN_RXD1 SMLINK1
3 8 LAN_RXD2 A11 1 2
PCI_FRAME# 4 7 SIRQ B10 R169
PCI_PLOCK# LAN_TXD0 8.2K_0402_5%
+3VS 5 6 C10
LAN I/F LAN_TXD1
LAN_TXD2 A12
8.2K_10P8R_1206_5% C11
LAN_CLK R159
LAN_RSTSYNC B11
LAN_RST# Y5 1 2
+3VS
RP2 10K_0402_5%
1 8 REQ#0 APICCLK
2 7 REQ#1 FW82801DBM_BGA421 APICD0
3 6 REQ#2 APICD1
REQ#3
4 5 ICH4-M

2
8.2K_8P4R_1206_5% R89 R88
1 2 REQB# 10K_0402_5% 0_0402_5%
R158 8.2K_0402_5%
+3VS

1
1 2 ICH_PCIRST#
R571 8.2K_0402_5% R97
10K_0402_5%
2
G

DIMM_SMCLK 3 1 SMB_CLK
<13,14,16,28> DIMM_SMCLK
2
S

+3V
4 Q28 SMB_DATA 1 DIMM_SMDATA 4
3 DIMM_SMDATA <13,14,16,28>
2N7002_SOT23
D

S
5

Q27
1 2N7002_SOT23
Dell-Compal Confidential
P

ICH_PCIRST# IN1
O 4 PCIRST# <6,10,17,24,25,27,28,32,35>
2 IN2
G

U9
Compal Electronics, Inc.
3

SN74AHC1G08HDCK_TSSOP5 Title
INTEL ICH4 (1/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 20 of 44
A B C D
 A B C D

+3VALW
+3VS
IAC_BITCLK

1
R79 R569
10K_0402_5% 10K_0402_5% R336
@10_0402_5%
+3VS
U55B

2
1 1

1 2 ICH_SPKR
<10,17> AGP_BUSY#
AGP_BUSY# R2 AGPBUSY#
ICH4-M GPI7 R3
1
C460
R98 @1K_0402_5% SYSRST# Y3 V4 EC_SMI# @10P_0402_50V8K
<6> SYSRST# SYSRST# GPI8 EC_SMI# <32> 2
VLBA# AB2 V5 SCI#
<32> VLBA# BATLOW# GPI12 SCI# <32>
1 2 ICH_AC_SDOUT T3 W3 LID_OUT#
<17> PM_C3_STAT# C3_STAT# GPI13 LID_OUT# <32>
R150 @8.2K_0402_5% ICLKRUN# AC2
V20
CLKRUN# GPIO GPIO25 V2
W1
EC_FLASH# <32>
<41> PM_DPRSLPVR DPRSLPVR GPIO27
1 2 PM_STPCPU# AA1 W4
<32> PWRBTN# PWRBTN# GPIO28
R90 @1K_0402_5% AB6
<10,32,34> PM_PWROK PWROK
EC_SWI# Y1
<32> EC_SWI# RI#
PM_STPPCI#
1
R78
2
@1K_0402_5%
<32,34> RSMRST# AA6
W18
RSMRST# PM AA13 PDA0 CLK_ICH_14M
<16,32> PM_SLP_S1# SLP_S1# PDA0 PDA0 <23>
Y4 AB13 PDA1
<16,32> PM_SLP_S3# SLP_S3# PDA1 PDA1 <23>

1
R842 and R81 depop for ICH4 Y2 W13 PDA2
<32> PM_SLP_S4# SLP_S4# PDA2 PDA2 <23>
AA2 Y13 PDCS1# R93
<32> PM_SLP_S5# SLP_S5# PDCS1# PDCS1# <23>
2 1 W19 AB14 PDCS3# @10_0402_5%
<16,41> PM_STPCPU# STP_CPU# PDCS3# PDCS3# <23>
R84 2 1 0_0402_5% Y21
<16> PM_STPPCI# STP_PCI#
RTCCLK R81 1 2 0_0402_5% AA4 AA11 PDDREQ
<10> RTCCLK PDDREQ <23>

2
R18 22_0402_5% SUS_CLK PDDREQ PDDACK#
<17,32> SUS_STAT# AB3 SUS_STAT#/LPCPD# PDDACK# Y12 PDDACK# <23> 1
1 ICH_THRM# V1 AC12 PDIOR#
THRM# PDIOR# PDIOR# <23>
W12 PDIOW# C124
PDIOW# PDIOW# <23> @10P_0402_50V8K
C62 AB12 PDIORDY
@100P_0402_25V8K PIORDY PDIORDY <23> 2
2 PDD0
J21 SSMUXSEL PDD0 AB11
PM_CPUPERF# PDD1
<6> PM_CPUPERF#
2 1 V_GATE
Y20
V19
CPUPERF# IST PDD1 AC11
Y10 PDD2
<32,41> VGATE VGATE/VRMPWRGD PDD2
R96 33_0402_5% AA10 PDD3
PDD3 PDD4
R391 IAC_BITCLK 2 1 B8
AC97 I/F PDD4 AA7
AB8 PDD5
@0_0402_5% <29,31> IAC_BITCLK R160 33_0402_5% C13 AC_BITCLK PDD5 PDD6
<29,31> IAC_RST# AC_RST# PDD6 Y8
IAC_SDATA_IN0 PDD7 CLK_ICH_48M
2 <6,33> PROCHOT# 2 1 <29> IAC_SDATA_IN0
IAC_SDATA_IN1
D13
A13
AC_SDATAIN0 IDE I/F PDD7 AA8
AB9 PDD8 2
<31> IAC_SDATA_IN1 AC_SDATAIN1 PDD8

1
B13 Y9 PDD9
R392 ICH_AC_SDOUT AC_SDATAIN2 PDD9 PDD10 R92
D9 AC_SDATAOUT PDD10 AC9
2 1 ICH_THRM# IC H_AC_SYNC C9 W9 PDD11 @10_0402_5%
<32> EC_THRM# AC_SYNC PDD11
AB10 PDD12
0_0402_5% PDD12 PDD13
W10

2
LAD0 PDD13 PDD14
<32> LAD0 T2 LPC_AD0 PDD14 W11 1
LAD1 R4 Y11 PDD15
<32> LAD1 LPC_AD1 PDD15
LAD2 T4 C123
<32> LAD2 LAD3 LPC_AD2 SDA0 @10P_0402_50V8K
1 2 RTCCLK
<32> LAD3 U2
U3
LPC_AD3 LPC I/F SDA0 AA20
AC20 SDA1
SDA0 <23> 2
LPC_DRQ#0 SDA1 SDA1 <23> PDD[0..15]
R347 @100K_0402_5% U4 AC21 SDA2
LPC_DRQ#1 SDA2 SDA2 <23> PDD[0..15] <23>
LFRAME# T5 AB21 SDCS1#
<32> LFRAME# LPC_FRAME# SDCS1# SDCS1# <23>
AC22 SDCS3#
SDCS3# SDCS3# <23> SDD[0..15]
SDD[0..15] <23>
AB18 SDDREQ
SDDREQ SDDREQ <23>
C20 AB19 SDDACK#
<34> USBP0+ USBP0+ SDDACK# SDDACK# <23>
D20 Y18 SDIOR#
<34> USBP0- USBP0- SDIOR# SDIOR# <23>
A21 AA18 SDIOW#
USBP1+ SDIOW# SDIOW# <23>
B21 AC19 SDIORDY
USBP1- SIORDY SDIORDY <23>
<34> USBP2+ C18 USBP2+
D18 W17 SDD0
<34> USBP2- USBP2- SDD0
A19 AB17 SDD1
USBP3+ SDD1 SDD2
B19 USBP3- SDD2 W16
C16 AC16 SDD3
USBP4+ SDD3 SDD4
D16 USBP4- SDD4 W15
A17 AB15 SDD5
+3VS USBP5+ SDD5 SDD6
B17 USBP5- USB I/F SDD6 W14
AA14 SDD7
SDD7 SDD8
SDD8 Y14
R82 1 2 100K_0402_5% PID0 <34> OVCUR#0
OVCUR#0 B15 OC#0 SDD9 AC15 SDD9
OVCUR#1 C14 AA15 SDD10
3 R83 OC#1 SDD10 3
1 2 100K_0402_5% PID1 <34> OVCUR#2
OVCUR#2 A15 OC#2 SDD11 Y15 SDD11
OVCUR#3 B14 AB16 SDD12
R80 OC#3 SDD12
1 2 100K_0402_5% PID2 OVCUR#4 A14 OC#4 SDD13 Y16 SDD13 +RTCVCC
OVCUR#5 D14 AA17 SDD14
R77 OC#5 SDD14
1 2 100K_0402_5% PID3 SDD15 Y17 SDD15 R145
USB_RBIAS A23 180K_0402_5%
USB_RBIAS
B23 USB_RBIAS# 2 1
1
2

J23 C156
CLK14 CLK_ICH_14M <16>
R86 F19 2 1 2 1 0.1U_0402_10V6K
+3VALW CLK48 CLK_ICH_48M <16>
22.6_0603_1% J20 GPIO32 RTC_RST# J1 R326 2
G22 GPIO33 RTCRST# W7
F20 JOPEN 1K_0402_5%
1

R144 1 OVCUR#1 GPIO34 VBIAS R_VBIAS1

2 8.2K_0402_5% G20 GPIO35 CLOCK VBIAS Y6 1 2 2
F21 GPIO36
R142 1 2 8.2K_0402_5% OVCUR#3 H20 AC7 RTCX1 C163 R154
GPIO37 RTCX1 R329 0.047U_0402_16V4Z 1K_0402_5%
<23> SIDEPWR F23 GPIO38
R130 1 2 8.2K_0402_5% OVCUR#4 RTCX2
H22
G23
GPIO39 GPIO RTCX2 AC6 2 1
10M_0603_5%
<17,18> PID0 GPIO40
R147 1 2 8.2K_0402_5% OVCUR#5 H21 X3
<17,18> PID1 GPIO41
F22 H23 32.768KHZ_12.5P
<17,18> PID2 GPIO42 SPKR ICH_SPKR <30>
<17,18> PID3 E23 GPIO43 1 2 2 1
MISC THRMTRIP# W20 H_THERMTRIP# H_THERMTRIP# <6>
R331 R324 @22M_0603_5%

2
1 1 10M_0603_5%
R330
R346 C450 C448 @2.4M_0603_1%
10K_0402_5% 12P_0402_50V8J 12P_0402_50V8J
FW82801DBM_BGA421 2 2
+3VS 1 2

1
D46
RB751V_SOD323
ICH4-M
CLKRUN# 2 1 ICLKRUN#
<24,27,28,32> CLKRUN#
4 4

1 2 IC H_AC_SYNC
<29,31> IAC_SYNC
R335 33_0402_5%
1 2 ICH_AC_SDOUT
<29,31> IAC_SDATAO
1 1 R325 33_0402_5% Dell-Compal Confidential
C457 C452 Compal Electronics, Inc.
@22P_0402_50V8J @22P_0402_50V8J
2 2 Title
INTEL ICH4 (2/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 21 of 44
A B C D
 A B C D E F G H

U55C

D22 VSS0
ICH4-M VCC3.3_0 A5 +3VS
+3VS

E10 VSS1 VCC3.3_1 AC17

E14 VSS2 VCC3.3_2 AC8 1 1 1 1 1 1 1 1
E16 VSS3 VCC3.3_3 B2
E17 H18 C146 C140 C428 C441 C9 C416 C466 C424
VSS4 VCC3.3_4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
E18 VSS5 VCC3.3_5 H6
2 2 2 2 2 2 2 2
E19 VSS6 VCC3.3_6 J1
E21 J18 4.7U_0805_10V4Z
VSS7 VCC3.3_7
E22 VSS8 VCC3.3_8 K6
F8 VSS9 VCC3.3_9 M10
1 1
G19 VSS10 VCC3.3_10 P12
G21 VSS11 VCC3.3_11 P6 1 1 1 1 1 1 1 1
G3 VSS12 VCC3.3_12 U1
G6 V10 C463 C449 C430 C397 C469 C473 C472 C443
VSS13 VCC3.3_13 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
H1 VSS14 VCC3.3_14 V16
2 2 2 2 2 2 2 2
J6 VSS15 VCC3.3_15 V18
K11 VSS16
K13 VSS17
K19 VSS18 VCCSUS3.3_0 E11 +3VALW
K23 VSS19 VCCSUS3.3_1 F10
K3 F15 +3VALW
VSS20 VCCSUS3.3_2
L10 VSS21 VCCSUS3.3_3 F16
L11 VSS22 VCCSUS3.3_4 F17
L12 VSS23 VCCSUS3.3_5 F18 1 1 1 1 1 1 1
L13 VSS24 VCCSUS3.3_6 K14
L14 V7 C433 C434 C431 C451 C464 C454 C442
VSS25 VCCSUS3.3_7 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L21 VSS26 VCCSUS3.3_8 V8
2 2 2 2 2 2 2
M1 VSS27 VCCSUS3.3_9 V9
M11 VSS28
M12 VSS29
M13
M20
VSS30 GND POWER K10
VSS31 VCC1.5_0 +1.5VS
M22 VSS32 VCC1.5_1 K12 1 1 1 1
N10 VSS33 VCC1.5_2 K18
N11 K22 C447 C436 C396 C426
VSS34 VCC1.5_3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
N12 VSS35 VCC1.5_4 P10
2 2 2 2
N13 VSS36 VCC1.5_5 T18
N14 VSS37 VCC1.5_6 U19
N19 VSS38 VCC1.5_7 V14
N21 VSS39
N23 VSS40
N5 VSS41 VCCSUS1.5_0 E12 +1.5VALW
2 +1.5VS 2
P11 VSS42 VCCSUS1.5_1 E13
P13 VSS43 VCCSUS1.5_2 E20
P20 VSS44 VCCSUS1.5_3 F14
P22 VSS45 VCCSUS1.5_4 G18 1 1 1 1 1 1 1 1 1
P3 VSS46 VCCSUS1.5_5 R6
R18 T6 C425 C427 C437 C467 C465 C446 C440 C445 C398
VSS47 VCCSUS1.5_6 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R21 VSS48 VCCSUS1.5_7 U6
2 2 2 2 2 2 2 2 2
R5 VSS49
T1 VSS50
T19 E7 VCC5REF
VSS51 VCC5REF1
T23 VSS52 VCC5REF2 V6 VCC DECOUPLING
U20 VSS53
V15 E15 VCC5REFSUS
VSS54 VCC5REFSUS1
V17 VSS55
V3 VSS56
W22 VSS57 VCCHI_0 L23 +1.5VS
W5 M14 +1.5VS +1.5VALW
VSS58 VCCHI_1
W8 VSS59 VCCHI_2 P18
Y19 VSS60 VCCHI_3 T22
Y7 VSS61 1 1 1 1 1 1 1
A16 VSS62
A18 AA23 C417 C453 C459 C444 C429 C435 C439
VSS63 VCC_CPU_IO_0 +CPU_CORE 4.7U_0805_10V4Z
A20 P14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS64 VCC_CPU_IO_1 2 2 2 2 2 2 2
A22 VSS65 VCC_CPU_IO_2 U18
A4 +1.5VS_PLL
VSS66
AA12 VSS67
AA16 VSS68 VCCPLL C22 1 2 +1.5VS VCCHI DECOUPLING
AA22 R85 0_0805_5%
VSS69
AA3 VSS70
AA9 VSS71 VCCRTC AB5 +RTCVCC
AB20 VSS72
AB7 +3VS_ICHLAN
3 VSS73 +CPU_CORE +1.5VS_ICHLAN +3VS_ICHLAN 3
AC1 VSS74
AC10 VSS75 VCCLAN3.3_0 E9 1 2 +3VS
AC14 F9 R338 0_0805_5%
VSS76 VCCLAN3.3_1 +1.5VS_ICHLAN
AC18 VSS77 1 1 1 1 1 1 1 1
AC23 VSS78
AC5 F6 1 2 C130 C438 C432 C468 C462 C455 C456 C461
VSS79 VCCLAN1.5_0 +1.5VS 1U_0603_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
B12 F7 R332 0_0805_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS80 VCCLAN1.5_1 2 2 2 2 2 2 2 2
B16 VSS81
B18 VSS82
B20 VSS83
B22 VSS84
B9 VSS85
C15 VSS86
C17 VSS87
C19 +3VALW +5VALW +3VS +5VS
VSS88
C21 VSS89
C23 VSS90

1
C6 VSS91
D1 +RTCVCC +1.5VS_PLL D23 R111 D13 R349
VSS92 1SS355_SOD323 1K_0603_1% 1SS355_SOD323 1K_0603_1%
D12 VSS93
D15 VSS94
D17 2 1 1

2
VSS95 VCC5REFSUS VCC5REF
D19 VSS96
D21 C153 C129 C128
VSS97 0.1U_0402_10V6K 0.1U_0402_16V4Z 0.01U_0402_25V7Z
D23 VSS98 1 1 1 1
1 2 2 C143
D4 VSS99
D8 C136 0.1U_0402_16V4Z C475 C474
VSS100 1U_0603_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z
A1 VSS101 2 2 2 2

4
FW82801DBM_BGA421 4
ICH4-M

Dell-Compal Confidential
Compal Electronics, Inc.
Title
INTEL ICH4 (3/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 22 of 44
A B C D E F G H
 A B C D E

HDD Connector SI2301DS: P CHANNEL

VGS: -4.5V, RDS: 130 mOHM
+5VSHDD
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
SDD[0..15] 0.1U_0402_16V4Z 1U_0603_10V4Z
<21> SDD[0..15] VGS(MAX): +-8V
1 1 1 1 1 1
C386 C389 C387 C375 C377 1 D
1 C643 1
JP6 1000P_0402_50V7K @22U_1206_10V4Z
2 2 2 2 2 2
<20> SIDERST# 1 2
SDD7 SDD8
SDD6 3 4 SDD9 22U_1206_10V4Z 0.1U_0402_16V4Z
SDD5 5 6 SDD10
SDD4 7 8 SDD11 G S
SDD3 9 10 SDD12 2 3
SDD2 11 12 SDD13
SDD1 13 14 SDD14
SDD0 15 16 SDD15 +5VS +5VSHDD
17 18 +12VALW
SDDREQ 19 20
<21> SDDREQ 21 22 R274 3 1
<21> SDIOW# 23 24

1
470_0402_5% 1 2 SDIORDY
<21> SDIOR# 25 26 +3VS
SDIORDY SEC_CSEL1 2 R280 4.7K_0402_5% R55 Q6
<21> SDIORDY 27 28
RSDDACK# 100K_0402_5% SI2301DS_SOT23

2
IRQ15 29 30
<20> IRQ15 31 32

2
<21> SDA1 33 34
<21> SDA0 35 36 SDA2 <21>
1 2 RSDDACK#
<21> SDCS1# 37 38 SDCS3# <21> <21> SDDACK#
SHDD_LED# R289 22_0402_5%
39 40
+5VSHDD 41 42 +5VSHDD
43 44

1
1

1
D R54
FOX_HH99227-S1-TR 2 150K_0603_5% C86
<21> SIDEPWR 0.1U_0402_16V4Z
G
SDDREQ Q18 2
1 2 S

2
2N7002_SOT23
C323
33P_0402_50V8J
2 2

CD-ROM Connector PDIORDY

+3VS 1 2
R370 4.7K_0402_5%

<21> PDD[0..15] PDD[0..15] 1 2 RPDDACK#

<21> PDDACK#
R371 22_0402_5%

1 2
C197 47P_0402_50V8J

1 2 C195
47P_0402_50V8J CD_AGND <29>
C196 1 2 PDDREQ 1 2
JP14
<29> INT_CD_L 47P_0402_50V8J C559 +5VS
1 2 INT_CD_R <29>
33P_0402_50V8J
3 3 4 PDD8 3
<20> PIDERST# 5 6
PDD7 PDD9 +5VS
7 8

2
PDD6 PDD10 C105
PDD5 9 10 PDD11 R67 R74
PDD4 11 12 PDD12 100K_0402_5%
13 14 1 2
PDD3 PDD13 100K_0402_5%
PDD2 15 16 PDD14

1
PDD1 17 18 PDD15 0.1U_0402_16V4Z
19 20

5
PDD0 PDDREQ
21 22 PDDREQ <21>
+5VS PHDD_LED# 1

P
23 24 PDIOR# <21> IN1
4 ACT_LED#
<21> PDIOW# 25 26 O ACT_LED# <31>
PDIORDY RPDDACK# R374 SHDD_LED# 2
<21> PDIORDY 27 28 IN2

G
IRQ14 100K_0402_5%
<20> IRQ14 29 30 PDIAG# 1 2 1 1 1 1 U18
<21> PDA1

3
31 32 +5VS C567 C565 C204 C202 SN74AHC1G08HDCK_TSSOP5
<21> PDA0 33 34 PDA2 <21>
<21> PDCS1# 35 36 PDCS3# <21>
PHDD_LED# 1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_1206_10V4Z
37 38 2 2 2 2
39 40
+5VS 41 42 +5VS
43 44 1 2

PRI_CSEL 45 46 C563 +5VS

47 48 0.1U_0402_16V4Z
49 50
2

R185 1 1 1 1
470_0402_5% SUYIN_800185MB050S106ZU C206 C561 C205 C203
1

1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_1206_10V4Z

2 2 2 2

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title
IDE/FDD/CD-ROM Module
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 23 of 44
A B C D E
 5 4 3 2 1

+1.8VLAN
+3VWOL WLAN LOM LED (JP28)
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1
1 1 1 1 1 1 1 1 WLAN_LINK_80211A LINK_LED100# ORANGE (100M)
C96 C41 C72 C95 C82 C70
C97 C94 C77 C74 C88 C87 C80 4.7U_0805_10V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2 2 2 2 2
2 2 2 2 2 2 2 2
WLAN_LINK_10_LDE LINK_LED10# GREEN (10M)
0.1U_0402_16V4Z

10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z WLAN_ACT_LED ACTLED# YELLOW

L7 WLAN_LINK_80211A
@BLM11A121SPT_0603 NC ORANGE/GREEN
D D
+3VALW 2 1 +3VAUXLAN +3VAUXLAN
WLAN_LINK_10_LDE
R461 0_0603_5%
1 2 +1.8VLAN +3VAUXLAN
+3VAUXLAN +3VWOL +3VWOL
+3V 2 1
L39 1 1 1 1 1 1
1 2 +3VAUXLAN +3VWOL BLM11A121SPT_0603
+3VS
C46 C55 C48 C45 C47 C38
R462 @0_0603_5% 1 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.8VLAN 2 2 2 2 2 2
C67 +3VAUXLAN
1000P_0402_50V7K 1000P_0402_50V7K
AD[0..31] 2
<20,25,27,28,35> AD[0..31] +3VAUXLAN

1
LINK_LED10# 1 2

3
R33 R31 D8

112

115
125

106

114
10K_0402_5% 10K_0402_5% RB751V_SOD323

17
44

19
30
40
52

79
94

96
97

91
92

25
56

65
68
U11

1
D E
47K
2 Q16 B

XTAL_AVSS
VDDIO1
VDDIO2

XTAL_AVDD
VDDCORE1
VDDCORE2
VDDCORE3

VDDBUS1
VDDBUS2
VDDBUS3
VDDBUS4
VDDBUS5
VDDBUS6
VDDBUS7

NC10

REG_AVDD1
REG_AVDD2

REG_VOUT1
REG_VOUT2

VESD1
VESD2
VESD3
<28> WLAN_LINK_10_LED

2
R32 G 2N7002_SOT23 2
10K_0402_5% D9 S 10K

3
1 2 C Q4
AD31 122 75 LINK_LED10# RB751V_SOD323 +3VAUXLAN DTA114YKA_SOT23
AD30 PCI_AD31 LED0_L LINK_LED100#
123 76

1
AD29 PCI_AD30 LED1_L ACTLED# LINK_LED100# R14
124 PCI_AD29 LED2_L 77 1 2

3
AD28 126 78 2 1
AD27 PCI_AD28 LED3_L D2 200_0603_5%
127 PCI_AD27

1
AD26 RB751V_SOD323 D E
128 PCI_AD26 47K
AD25 1 58 2 Q15 B
PCI_AD25 EPHY_AGND <28> WLAN_LINK_80211A
AD24 3 57 RB751V_SOD323G 2N7002_SOT23 2
PCI_AD24 EPHY_AVDD +1.8VLAN
AD23 6 D7 S 10K Q3

3
AD22 PCI_AD23 C DTA114YKA_SOT23
8 PCI_AD22 EPHY_BIAS_AVDD 69 +3VAUXLAN 1 2
C AD21 9 70 +3VAUXLAN C
AD20 PCI_AD21 EPHY_BIAS_AVSS L8
10

1
AD19 PCI_AD20 EPHY_PLLVDD ACTLED# R13
11 PCI_AD19 EPHY_PLLVDD 64 1 2 +1.8VLAN 1 2

3
AD18 14 63 LCN0603T-R22J-S_5%_0603 2 1
AD17 PCI_AD18 EPHY_PLLGND D10 200_0603_5%
15 PCI_AD17

1
AD16 R34 1 D E
16 71 2 @10K_0402_5% RB751V_SOD323
AD15
AD14
AD13
33
34
36
PCI_AD16
PCI_AD15
PCI_AD14
Broadcom EPHY_VREF
EPHY_RDAC
EPHY_TESTMODE
72
88
R28 1 2 1.27K_0603_1% <28> WLAN_ACT_LED 2
G
S Q17
2
B
47K

Q5
10K

3
AD12 PCI_AD13 LAN_TX+ 2N7002_SOT23 C DTA114YKA_SOT23
37 62
AD11
AD10
38
39
PCI_AD12
PCI_AD11
BCM 4401L EPHY_TDP
EPHY_TDN 61
59
LAN_TX-
LAN_RX+

1
AD9 PCI_AD10 EPHY_RDP LAN_RX- +3VAUXLAN
41 PCI_AD9 EPHY_RDN 60
AD8 42
AD7 PCI_AD8 +3VAUXLAN
45 PCI_AD7 NC0 104 +3VAUXLAN
AD6 48 105
AD5 PCI_AD6 NC1
49 PCI_AD5 NC2 103

1
AD4 50 108
AD3 PCI_AD4 NC3 R35 R30 R25
51 PCI_AD3 NC4 102

1
AD2 53 109 1K_0402_5% @10K_0402_5% @10K_0402_5% 1
AD1 PCI_AD2 NC5
54 PCI_AD1 NC6 110
AD0 55 107 U8 C20

2
PCI_AD0 NC7 0.1U_0402_16V4Z
1 CS VCC 8
R452 2
<20,25,27,28,35> C/BE#3 4 87 2 7

2
PCI_CBE3_L VAUX_AVAIL SK NC @100K_0402_5% R15
<20,25,27,28,35> C/BE#2 18 PCI_CBE2_L NC8 86 3 DI ORG 6
<20,25,27,28,35> C/BE#1 32 PCI_CBE1_L NC9 85 4 DO GND 5 1 2
<20,25,27,28,35> C/BE#0 43 PCI_CBE0_L
20 90 AT93C46_SO8 200_0603_5%
<20,25,27,28,35> PCI_FRAME# PCI_FRAME_L BOOTROM_SCL
<20,25,27,28> PCI_IRDY# 21 PCI_IRDY_L BOOTROM_SDA 93
<20,25,27,28,35> PCI_TRDY# 23 PCI_TRDY_L
26 98 SPROM_CS
<20,25,27,28> PCI_DEVSEL# PCI_DEVSEL_L SPROM_CS
27 95 SPROM_CLK
B <20,25,27,28> PCI_STOP# PCI_STOP_L SPROM_CLK B
SPROM_DOUT

10

11

12

13
<20,25,27,28> PCI_PERR# 28 PCI_PERR_L SPROM_DOUT 101

9
29 99 SPROM_DI +3VAUXLAN JP7
<20,25,27,28> PCI_SERR# PCI_SERR_L SPROM_DIN
31 LAN_RJ45T+ 1

LDE_ORANGE+

LDE_GREEN+

LED_YELLOW+

LED_YELLOW-
G_O_LED-
<20,25,27,28> PCI_PAR PCI_PAR PR1+
116 U2
<20> PIRQB# PCI_INT_L
89 LAN_RJ45T- 2
EXT_POR_L LAN_DISABLE# <32> PR1-
PCIRST# 117 LAN_TX+ 1 12
0,17,20,25,27,28,32,35> PCIRST# PCI_RST_L TD+ TX+
118 83 LAN_TX- 2 11 LAN_RJ45R+ 3
<16> CLK_PCI_LAN PCI_CLK JTAG_TDO TD- TX- PR2+
<20> GNT#0 119 PCI_GNT_L JTAG_TCK 80 SPROM_DOUT SPROM_CLK
<20> REQ#0 121 PCI_REQ_L JTAG_TDI 82 3 TDC TCT 10 4 PR3+
<33> LAN_PME# 113 PCI_PME_L JTAG_TRST_L 73 4 RDC RCT 9
LAN_AD17 5 81 1Kb None None 5
PCI_IDSEL JTAG_TMS LAN_RX+ PR3-
5 RD+ RX+ 8
22 LAN_RX- 6 7 LAN_RJ45R- 6
<21,27,28,32> CLKRUN# PCI_CLKRUN_L RD- RX- PR2-
4Kb 10K Pullup None
67 1 1 7

SHLD1

SHLD2
XTAL_IN Pulse_H1112 PR4+
66 XTAL_OUT
16Kb None 10K Pullup C213 8 PR4-
1

0.01U_0402_25V7Z
VSS10
VSS11

1
2 2 FOX_JM66113-L1B1-TR
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

14

15
1

1
Y1 R29 R193 R190
25MHZ_20P 200_0603_5% EPHY_PLLVDD 75_0603_1% R192 R191
BCM4401_LQFP128 C215 75_0603_1%
2

12
46
111
100
84
2
24
74
13
47
120
35

XI 1 2 XO 0.01U_0402_25V7Z 75_0603_1%

2
1 2 Close to RJ45 under inch

2
1 1
C54 C52 2 75_0603_1% 2
C40 4.7U_0805_10V4Z 1000P_0402_50V7K
C39 27P_0402_50V8J 2 1 C211 C212
2 27P_0402_50V8J 2
Place closely pin 118
1000P_1808_3KV7K 1000P_1808_3KV7K
1 1
CLK_PCI_LAN
1

A +3VAUXLAN A
R52
33_0402_5% LAN_RX+ R53 2 1 49.9_0805_1% Chassis GND & Digital GND Short Together
LAN_RX- R51 2 1 49.9_0805_1% 1 1
LAN_TX+ R42 2 1 49.9_0805_1%
Dell-Compal Confidential
2

1 LAN_TX- R46 2 1 49.9_0805_1% C56 C84

AD17 1 2 LAN_AD17 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C79 2 2
R64 100_0402_5%
22P_0402_50V8J
Compal Electronics, Inc.
2 Place close to U11 Title
BROADCOM 4401L LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 24 of 44
5 4 3 2 1
 A B C D E

2 1 +3V_CBSA <20,24,27,28,35> AD[0..31] CBS_CAD[0..31] <26,27>

R73 U35A
@402K_0603_1% +3V_CBSD AD31 J5 E8 CBS_CAD31
+3V_CBSD AD30 AD31 CAD31/D10 CBS_CAD30
J6 AD30 CAD30/D9 C8
R70 AD29 K2 B8 CBS_CAD29
2@1K_0402_5% U35B AD28 AD29 CAD29/D1 CBS_CAD28
K3 AD28 CAD28/D8 E9
G1 +3V_CBSA AD27 K5 F9 CBS_CAD27
PHY_CPS VCC_G01 AD26 AD27 CAD27/D0 CBS_CAD26
2 1 P10 CPS VCC_M01 M1 K6 AD26 CAD26/A0 F11
2

2
R59 R1 L11 AD25 L2 E11 CBS_CAD25
1 R69 @0_0402_5% VCC_R01 VDPLL AD24 AD25 CAD25/A1 CBS_CAD24 1
VCC_W08 W8 1 2 L3 AD24 CAD24/A2 C11
@0_0402_5% 1 2 PH Y_CNA P17 L19 2@BLM21A05 _0805 AD23 M2 A12 CBS_CAD23
CNA VCC_L19 AD22 AD23 CAD23/A3 CBS_CAD22
VCC_H19 H19 1 1 M3 AD22 CAD22/A4 C12
R68 R50 E19 AD21 M6 E12 CBS_CAD21
1

1 VCC_E19 AD21 CAD21/A5

@0_0402_5% 2@43K_0402_5% A13 C115 C103 AD20 M5 C13 CBS_CAD20
CBS_PC0
CBS_PC1
V10
W10
PC0
VCC_A13
VCC_A08 A8
A5
2@10U_1206_10V4Z
2 2
[email protected]_0402_25V7Z AD19
AD18
N2
N3
AD20
AD19 PCI4510 CAD20/A6
CAD19/A25 A14
E13
CBS_CAD19
CBS_CAD18
CBS_PC2 PC1 VCC_A05 AD17 AD18 CAD18/A7 CBS_CAD17
P9 N6 B14

PCI4510_R0 W13
PC2
PCI4510 G14
CBS_VCC AD16
AD15
P1
R6
AD17
AD16
CAD17/A24
CAD16/A17 F18
G17
CBS_CAD16
CBS_CAD15
R0 VCCCB_G14 AD15 CAD15/IOWR#
2

R63 A11 AD14 P7 F19 CBS_CAD14

R72 R58 PCI4510_R1 VCCCB_A11 +3V_CBSD AD13 AD14 CAD14/A9 CBS_CAD13
1 2 V13 R1 V5 AD13 CAD13/IORD# G18
2@0_0402_5% R71 2@0_0402_5% L1 AD12 U6 H15 CBS_CAD12
[email protected]_0603_1% VCCP_L01 AD11 AD12 CAD12/A11 CBS_CAD11
VCCP_W05 W5 V6 AD11 CAD11/OE# H14
AD10 R7 H17 CBS_CAD10
1

C53 1 AD9 AD10 CAD10/CE2# CBS_CAD9

1.8V_G02 G2 2 [email protected]_0402_16V4Z P8 AD9 CAD9/A10 H18
IEEE1394_TPA0+ V12 L18 Place close to pin H1 AD8 U7 J14 CBS_CAD8
2@0_0402_5% TPA0+ 1.8V_L18 AD7 AD8 CAD8/D15 CBS_CAD7
1 2 W7 AD7 CAD7/D7 J17
IEEE1394_TPA0- W12 C73 [email protected]_0402_16V4Z AD6 R8 K14 CBS_CAD6
TPA0- CLK_PCI_PCM AD5 AD6 CAD6/D13 CBS_CAD5
VCCD0# E6 VCCD0# <26,27> U8 AD5 CAD5/D6 J19
B5 AD4 V8 K17 CBS_CAD4
R574 R575 VCCD1# VCCD1# <26,27> AD4 CAD4/D12

1
V15 AD3 W9 K15 CBS_CAD3
TPA1+ R47 AD2 AD3 CAD3/D5 CBS_CAD2
2 1 2 1 V9 AD2 CAD2/D11 L14
W15 A4 @33_0402_5% AD1 U9 K18 CBS_CAD1
TPA1- VPPD0# VPPD0 <26,27> AD1 CAD1/D4
[email protected]_0402_1% [email protected]_0402_1% C5 AD0 R9 L15 CBS_CAD0
VPPD1# VPPD1 <26,27> AD0 CAD0/D3
C822 R576

2
IEEE1394_TPB0+ V11 1
TPB0+
2 1 2 1
IEEE1394_TPB0- W11 E1 C75 B11 CBS_CC/BE3#
TPB0- GND_E01 @22P_0402_50V8J CC/BE3#/REG# CBS_CC/BE3# <26,27>
2@270P_0402_50V8J [email protected]_0402_1% K1 L6 C14 CBS_CC/BE2#
GND_K01 2 <20,24,27,28,35> C/BE#3 C/BE3# CC/BE2#/A12 CBS_CC/BE2# <26,27>
2 1 2 1 IEEE1394_TPB1+ V14 N1 P2 G15 CBS_CC/BE1#
[email protected]_0402_16V4Z TPB1+ GND_N01 <20,24,27,28,35> C/BE#2 C/BE2# CC/BE1#/A8 CBS_CC/BE1# <26,27>
R65 2@1K_0402_5% C89 W6 U5 J15 CBS_CC/BE0#
2 GND_W06 <20,24,27,28,35> C/BE#1 C/BE1# CC/BE0#/CE1# CBS_CC/BE0# <26,27> 2
2 1 IEEE1394_TPB1- W14 P19 V7
TPB1- GND_P19 <20,24,27,28,35> C/BE#0 C/BE0#
R56 2@1K_0402_5% K19 B13 CBS_CRST#
GND_K19 CRESET CBS_CRST# <26,27>
IEEE1394_TPBIAS0 U12 G19 B15 CBS_CFRAME#
TPBIAS0 GND_G19 CFRAME#/A23 CBS_CFRAME# <26,27>
A15 F13 C BS_CIRDY#
GND_A15 CIRDY#/A15 CBS_CIRDY# <26,27>
IEEE1394_TPBIAS0 2 1 IEEE1394_TPBIAS1 U15 A10 E14 CBS_CTRDY#
2@1U_0603_10V4Z TPBIAS1 GND_A10 CTRDY#/A22 CBS_CTRDY# <26,27>
R577 C98 A7 W4 A16 CBS_CDEVSEL#
GND_A7 <20,24,27,28> PCI_PAR PCI_PAR CDEVSEL#/A21 CBS_CDEVSEL# <26,27>
1 E17 CBS_CSTOP#
CSTOP#/A20 CBS_CSTOP# <26,27>
2 1 IEEE1394_TPA0+ R22 F15 CBS_CPERR#
CPERR#/A14 CBS_CPERR# <26,27>
H5 1V8_VR_EN# 2 1 E10 CBS_CSERR#
VR_EN# CSERR#/WAIT# CBS_CSERR# <26,27>
[email protected]_0402_1% 2@0_0402_5% F14 CBS_CPAR
2 CPAR/A13 CBS_CPAR <26,27>
R11 R2 B12 CBS_CREQ#
+3V_CBSA AVD2 <20,24,27,28> PCI_DEVSEL# DEVSEL# CREQ#/INPACK# CBS_CREQ# <26,27>
R578 U13 G3 N5 D19 CBS_CGNT#
AVD3 SUSPEND# PCM_SUSP# <26,27,32> <20,24,27,28,35> PCI_FRAME# FRAME# CGNT#/WE# CBS_CGNT# <26,27>
2 1 IEEE1394_TPA0- U14 J1 C15 CBS_CCLK_INTERNAL
AVD4 <20,27> GNT#2 GNT# CCLK/A16 CBS_CCLK_INTERNAL <26,27>
C823
2@1U_0603_10V4Z [email protected]_0402_1% U11 R57 P3 A9 CBS_CSTSCHNG
AGND2 <20,24,27,28> PCI_IRDY# IRDY# CSTSCHG/BVD1 CBS_CSTSCHNG <26,27>
R12 J3 2 1 PCM_PME# <27,33> R3 B9 CBS_CCLKRUN#
AGND3 RI_OUT#/PME# <20,24,27,28> PCI_PERR# PERR# CCLKRUN#/WP CBS_CCLKRUN# <26,27>
R13 2@0_0402_5% J2
AGND4 <20,27> REQ#2 REQ#
E2 PCM_SPK# T1 E18 CBS_CBLOCK#
SPKROUT PCM_SPK# <27,30> <20,24,27,28> PCI_SERR# SERR# CBLOCK#/A19 CBS_CBLOCK# <26,27>
VDPLL P15 P5 C10 CBS_CINT#
VDPLL <20,24,27,28> PCI_STOP# STOP# CINT#/READY CBS_CINT# <26,27>
F5 PIRQA# PIRQA# <20,27> P6
INTA#/MFUNC0 <20,24,27,28,35> PCI_TRDY# TRDY#
G6 CBS_MFUNC1 H3 F10 CBS_CAUDIO
INTB#/MFUNC1 <6,10,17,20,24,27,28,32,35> PCIRST# PCI_RESET# CAUDIO/BVD2 CBS_CAUDIO <26,27>
F3 CBS_MFUNC2 C9 CBS_CCD2#
MFUNC2 CCD2/CD2# CBS_CCD2# <26,27>
F2 SIRQ <20,27,32> H2 L17 CBS_CCD1#
MFUNC3 <17,26,27> V_PRST# G_RST# CCD1/CD1# CBS_CCD1# <26,27>
N14 G5 CBS_MFUNC4
VSPLL MFUNC4 CBS_MFUNC5 CBS_CVS2
LEDSKT/MFUNC5 F1 CVS2/VS2# F12 CBS_CVS2 <26,27>
FILTER0 T19 H6 CBS_MFUNC6 PCM_ID L5 B10 CBS_CVS1
FILTER0 MFUNC6 <27> PCM_ID IDSEL CVS1/VS1# CBS_CVS1 <26,27>
1 2 FILTER1 R17
C78 [email protected]_0402_10V6K FILTER1 CBS_RSVD/D2
CRSVD/D2 F8 CBS_RSVD/D2 <26,27>
N15 +3V_CBSD H1 F17 CBS_RSVD/A18
MC_RSVD1 <16,27> CLK_PCI_PCM PCICLK CRSVD/A18 CBS_RSVD/A18 <26,27>
E3 CBS_SCL J18 CBS_RSVD/D14
SCL CRSVD/D14 CBS_RSVD/D14 <26,27>
M14 D1 CBS_SDA
MC_RSVD3 SDA
N17 MC_RSVD4
3 PHY_TEST_MA 2@PCI4510GHK_PBGA209 3
N18 MC_RSVD5 PHY_TEST_MA P18 2 1
N19 R44 [email protected]_0402_5%
MC_RSVD6
M15 MC_RSVD7 TEST0 U10 CBS_TEST0 2 1
M17 R61 2@200_0402_5%
MC_RSVD8
M18 MC_RSVD9 TEST1 R10 CBS_TEST1 2 1
M19 R60 2@200_0402_5%
+3V_CBSD MC_RSVD10 IEEE1394_TPBIAS0
CLK48_RSVD F6
B7 SC_CD#

1
C7 SC_RST 1

1
CBS_MFUNC1 1 2 F7 R18 PCI4510XI R198
R23 2@10K_0402_5% SC_CLK XI C223 @56.2_0603_1%
A6 SC_DATA U3
CBS_MFUNC2 1 2 B6 @1U_0603_10V4Z
R38 2@10K_0402_5% SC_PWR 2 TPB0- JP2
E7

2
CBS_MFUNC4 SC_MODE 8 1
1 2 C6 R19 PCI4510XO

2
R36 2@10K_0402_5% SC_FCB XO R199 7 2
6 3 1 1
CBS_MFUNC5 1 2 2@PCI4510GHK_PBGA209 [email protected]_16P @56.2_0603_1% TPB0+ 2
R39 2@10K_0402_5% X1 IEEE1394_TPB0- 5 4 TPA0- 2
3 3
CBS_MFUNC6 1 2 1 2 IEEE1394_TPB0+ 4
R26 2@10K_0402_5% IEEE1394_TPA0- @BTS0402-01_8P 4
1 1 IEEE1394_TPA0+ TPA0+ 5
C83 C106 GND1
6 GND2

1
7 GND3

1
2@22P_0402_50V8J 2@22P_0402_50V8J R196 8
2 2 R197 GND4
@56.2_0603_1% @56.2_0603_1% RP1
1 8 2@AMP_440168-2_4P

2
+3V +3V_CBSA 2 7

2
2@BLM21A601SPT_0805 3 6
L10 4 5
1 2 [email protected]_0402_16V4Z
2 1 CBS_SCL 2@0_8P4R_1206_5%

1
1 1 1 1 1 R21 2@220_0402_5% 1
4 CBS_SDA R194 4
2 1
C114 C108 C101 C102 C109 R37 2@220_0402_5% C216 @5.1K_0603_1%
2@10U_1206_10V4Z [email protected]_0402_16V4Z @270P_0603_50V8J
2 2 2 2 2 2
Dell-Compal Confidential

2
[email protected]_0402_16V4Z [email protected]_0402_16V4Z AD20 1
R41
2 PCM_ID
100_0402_5%
Compal Electronics, Inc.
Title
PCMCIA & 1394 Controller PCI4510
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 25 of 44
A B C D E
 A B C D E

PCMCIA Power Controller

+12VALW CBS_VCC

1 1
C31 U7
0.1U_0603_50V4Z 13 C18
VCC 4.7U_0805_10V4Z
VCC 12
2 2
9 12V VCC 11
CBS_VPP
1 L9 +3V_CBSD 1
+5VALW BLM21A601SPT_0805 C85 C57 C81 C90
1 1 2 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3V
VPP 10
C23 1 1 1 1 1 1 1 1 1 1
1 5 0.1U_0402_16V4Z
5V 2 C71 C49
6 5V
C25 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z VCCD0# 2 2 2 2 2 2 2 2 2 2
VCCD0 1 VCCD0# <25,27>
2 VCCD1#
VCCD1 2 VCCD1# <25,27>
+3VALW 15 VPPD0 C36 C51 C34 C92
VPPD0 VPPD0 <25,27>
14 VPPD1 0.1U_0402_16V4Z 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VPPD1 VPPD1 <25,27>
3 3.3V
1 4 3.3V OC 8
SHDN
GND

C21
2 0.1U_0402_16V4Z TPS2211AIDBR_SSOP16
7

16

V_PRST#
V_PRST# <17,25,27>

CBS_VCCL CBS_VCC
+3VALW +5VALW
1 1
2 2
1 1
1 1 C60 C50
0.01U_0402_25V7Z 4.7U_0805_10V4Z C37 C35
C17 C30 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1U_0603_10V4Z 1U_0603_10V4Z 2 2
2 2

CBS_VPP
1 1
C24 C26 1 2 CBS_VCCL
0.01U_0402_25V7Z 1U_0603_10V4Z CBS_VCC L6
2 2 KC FBM-L11-201209-221LMAT_0805

1 2 +3V_CBSD
L5
@KC FBM-L11-201209-221LMAT_0805 2 1
C76 C93
C19 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1000P_0402_50V7K 1 2
PCMCIA Cardbus socket
2 1

JP18

1 1 35 35
CBS_CAD0 2 36 CBS_CCD1#
<25,27> CBS_CAD0 2 36 CBS_CCD1# <25,27>
CBS_CAD1 3 37 CBS_CAD2 CBS_CAD2 <25,27>
<25,27> CBS_CAD1 3 37
CBS_CAD3 4 38 CBS_CAD4 CBS_CAD4 <25,27>
<25,27> CBS_CAD3 4 38
CBS_CAD5 5 39 CBS_CAD6 CBS_CAD6 <25,27>
3 <25,27> CBS_CAD5 5 39 3
CBS_CAD7 6 40 CBS_RSVD/D14 CBS_RSVD/D14 <25,27>
<25,27> CBS_CAD7 6 40
CBS_CC/BE0# 7 41 CBS_CAD8 CBS_CAD8 <25,27>
<25,27> CBS_CC/BE0# 7 41
CBS_CAD9 8 42 CBS_CAD10 CBS_CAD10 <25,27>
<25,27> CBS_CAD9 8 42
CBS_CAD11 9 43 CBS_CVS1 CBS_CVS1 <25,27>
<25,27> CBS_CAD11 9 43
CBS_CAD12 10 44 CBS_CAD13 CBS_CAD13 <25,27>
<25,27> CBS_CAD12 10 44
CBS_CAD14 11 45 CBS_CAD15 CBS_CAD15 <25,27>
<25,27> CBS_CAD14 11 45
CBS_CC/BE1# 12 46 CBS_CAD16 CBS_CAD16 <25,27>
<25,27> CBS_CC/BE1# 12 46
CBS_CPAR 13 47 CBS_RSVD/A18 CBS_RSVD/A18 <25,27>
<25,27> CBS_CPAR 13 47
CBS_CPERR# 14 48 CBS_CBLOCK# CBS_CBLOCK# <25,27>
<25,27> CBS_CPERR# 14 48
CBS_CGNT# 15 49 CBS_CSTOP# CBS_CSTOP# <25,27> CBS_CCLK 1 2
<25,27> CBS_CGNT# 15 49 CBS_CCLK_INTERNAL <25,27>
CBS_CINT# 16 50 CBS_CDEVSEL# CBS_CDEVSEL# <25,27> R27 47_0402_5%
<25,27> CBS_CINT# 16 50
CBS_VCCL 17 17 51 51 CBS_VCCL
CBS_VPP 18 18 52 52 CBS_VPP
CBS_CCLK 19 53 CBS_CTRDY# CBS_CTRDY# <25,27>
C BS_CIRDY# 19 53 CBS_CFRAME#
<25,27> CBS_CIRDY# 20 20 54 54 CBS_CFRAME# <25,27>
CBS_CC/BE2# 21 55 CBS_CAD17 CBS_CAD17 <25,27>
<25,27> CBS_CC/BE2# 21 55
CBS_CAD18 22 56 CBS_CAD19 CBS_CAD19 <25,27>
<25,27> CBS_CAD18 22 56
CBS_CAD20 23 57 CBS_CVS2 CBS_CVS2 <25,27>
<25,27> CBS_CAD20 23 57
CBS_CAD21 24 58 CBS_CRST#
<25,27> CBS_CAD21 24 58 CBS_CRST# <25,27>
CBS_CAD22 25 59 CBS_CSERR#
<25,27> CBS_CAD22 25 59 CBS_CSERR# <25,27>
CBS_CAD23 26 60 CBS_CREQ#
<25,27> CBS_CAD23 26 60 CBS_CREQ# <25,27>
CBS_CAD24 27 61 CBS_CC/BE3# CBS_CC/BE3# <25,27>
<25,27> CBS_CAD24 27 61
CBS_CAD25 28 62 CBS_CAUDIO
<25,27> CBS_CAD25 28 62 CBS_CAUDIO <25,27>
CBS_CAD26 29 63 CBS_CSTSCHNG 2 1
<25,27> CBS_CAD26 29 63 CBS_CSTSCHNG <25,27> <25,27,32> PCM_SUSP# +3V_CBSD
CBS_CAD27 30 64 CBS_CAD28 CBS_CAD28 <25,27> R40 10K_0402_5%
<25,27> CBS_CAD27 30 64
CBS_CAD29 31 65 CBS_CAD30 CBS_CAD30 <25,27>
<25,27> CBS_CAD29 31 65
CBS_RSVD/D2 32 66 CBS_CAD31 CBS_CAD31 <25,27>
<25,27> CBS_RSVD/D2 32 66
CBS_CCLKRUN# 33 67 CBS_CCD2#
<25,27> CBS_CCLKRUN# 33 67 CBS_CCD2# <25,27>
34 34 68 68
69 GND GND 70 1
71 GND GND 72
73 74 C107
4 GND GND 1000P_0402_50V7K 4
75 GND GND 76
2
77 GND GND 78
79 GND GND 80
81 GND GND 82
Dell-Compal Confidential
JAE JC21-BRB-E500
Compal Electronics, Inc.
Title
PCMCIA Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
Date: Tuesday, February 25, 2003 Sheet 26 of 44
A B C D E
 A B C D E

CBS_CAD[0..31]
CBS_CAD[0..31] <25,26>

U34B
76 CBS_CAD0
A_D3/CAD0 CBS_CAD1
A_D4/CAD1 78
PCI1510 77 CBS_CAD2
1 A_D11/CAD2 CBS_CAD3 1
A_D5/CAD3 81
79 CBS_CAD4
A_D12/CAD4 CBS_CAD5
A_D6/CAD5 83
82 CBS_CAD6
A_D13/CAD6 CBS_CAD7
A_D7/CAD7 86
87 CBS_CAD8
A_D15/CAD8 CBS_CAD9
A_A10/CAD9 89
90 CBS_CAD10
A_CE2#/CAD10 CBS_CAD11
A_OE#/CAD11 91
U34A 92 CBS_CAD12
<20,24,25,28,35> AD[0..31] Multifunction& A_A11/CAD12
94 CBS_CAD13
Miscellaneous A_IORD#/CAD13 CBS_CAD14
PCI1510 A_A9/CAD14 96
AD0 56 58 PIRQA# <20,25> 95 CBS_CAD15
AD1 AD0 MF0/INTA# CBS_1510MF1 A_IOWR#/CAD15 CBS_CAD16
55 AD1 MF1 59 A_A17/CAD16 97
AD2 53 63 CBS_1510MF2 114 CBS_CAD17

PC CARD / CARD BUS INTERFACE

AD3 AD2 MF2/DMAREQ# A_A24/CAD17 CBS_CAD18
52 AD3 MF3/IRQSER 64 SIRQ <20,25,32> A_A7/CAD18 115
AD4 51 67 CBS_1510MF4 116 CBS_CAD19
AD5 AD4 MF4/RI_OUT# CBS_1510MF5 A_A25/CAD19 CBS_CAD20
50 AD5 MF5/DMAGNT# 68 A_A6/CAD20 118
AD6 49 69 120 CBS_CAD21
AD6 MF6/CLKRUN# CLKRUN# <21,24,28,32> A_A5/CAD21
AD7 48 121 CBS_CAD22
AD8 AD7 A_A4/CAD22 CBS_CAD23
46 AD8 RI_OUT#/PME# 57 PCM_PME# <25,33> A_A3/CAD23 123
AD9 45 61 127 CBS_CAD24
AD9 SPKROUT PCM_SPK# <25,30> A_A2/CAD24
AD10 44 65 128 CBS_CAD25
AD10 SUSPEND# PCM_SUSP# <25,26,32> A_A1/CAD25
AD11 43 85 129 CBS_CAD26
AD12 AD11 CLK_48M_RSVD A_A0/CAD26 CBS_CAD27
42 AD12 A_D0/CAD27 139
AD13 41 125 140 CBS_CAD28
AD14 AD13 VR_EN# A_D8/CAD28 CBS_CAD29
39 AD14 VR_PORT 62 A_D1/CAD29 141
AD15 38 1 142 CBS_CAD30
AD16 AD15 A_D9/CAD30 CBS_CAD31
25 AD16 A_D10/CAD31 144
AD17 24 C91
AD18 AD17 [email protected]_0402_16V4Z CBS_RSVD/A18
23 AD18 A_A18/RSVD 99 CBS_RSVD/A18 <25,26>
AD19 2 CBS_RSVD/D14
22 AD19 A_D14/RSVD 84 CBS_RSVD/D14 <25,26>
2 AD20 PCI CBS_RSVD/D2 2
18 AD20 A_D2/RSVD 143 CBS_RSVD/D2 <25,26>
AD21 17 36 +3V_CBSD
AD22 AD21 PWR VCCP CBS_CC/BE0#
16 AD22 A_CE1#/CC/BE0# 88 CBS_CC/BE0# <25,26>
AD23 15 98 CBS_CC/BE1#
PCI BUS

AD23 A_A8/CC/BE1# CBS_CC/BE1# <25,26>

AD24 11 54 CBS_1510MF1 1 2 113 CBS_CC/BE2#
AD24 VCC1 +3V_CBSD A_A12/CC/BE2# CBS_CC/BE2# <25,26>
AD25 R75 1@10K_0402_5% CBS_CC/BE3#
CORE LOGIC

10 AD25 VCC2 70 A_REG#/CC/BE3# 124 CBS_CC/BE3# <25,26>

AD26 9 104 CBS_1510MF2 1 2 100 CBS_CPAR
AD26 VCC3 A_A13/CPAR CBS_CPAR <25,26>
AD27 7 126 R76 1@10K_0402_5% 102 CBS_CPERR#
AD27 VCC4 A_A14/CPERR# CBS_CPERR# <25,26>
PWR

AD28 6 137 CBS_1510MF4 1 2 110 C BS_CIRDY#

AD28 VCC5 A_A15/CIRDY# CBS_CIRDY# <25,26>
AD29 5 12 R66 1@10K_0402_5% 107 CBS_CCLK_INTERNAL
AD29 VCC6 A_A16/CCLK CBS_CCLK_INTERNAL <25,26>
AD30 4 32 CBS_1510MF5 1 2
AD31 AD30 VCC7 R62 1@10K_0402_5% CBS_CBLOCK#
3 AD31 A_A19/CBLOCK# 101 CBS_CBLOCK# <25,26>
8 103 CBS_CSTOP#
GND A_A20/CSTOP# CBS_CSTOP# <25,26>
47 21 106 CBS_CDEVSEL#
<20,24,25,28,35> C/BE#0 C/BE0# GND A_A21/CDEVSEL# CBS_CDEVSEL# <25,26>
37 40 108 CBS_CTRDY#
<20,24,25,28,35> C/BE#1 C/BE1# GND A_A22/CTRDY# CBS_CTRDY# <25,26>
26 GND 60 111 CBS_CFRAME#
<20,24,25,28,35> C/BE#2 C/BE2# GND A_A23/CFRAME# CBS_CFRAME# <25,26>
13 80 135 CBS_CSTSCHNG
<20,24,25,28,35> C/BE#3 C/BE3# GND A_BVD1/CSTSCHG CBS_CSTSCHNG <25,26>
93 134 CBS_CAUDIO
GND A_BVD2/CAUDIO CBS_CAUDIO <25,26>
PCM_ID 14 112 131 CBS_CINT#
<25> PCM_ID IDSEL GND A_READY/CINT# CBS_CINT# <25,26>
132 133 CBS_CSERR#
GND A_WAIT#/CSERR# CBS_CSERR# <25,26>
20 136 CBS_CCLKRUN#
<16,25> CLK_PCI_PCM PCLK A_WP/CCLKRUN# CBS_CCLKRUN# <25,26>
35 73 75 CBS_CCD1#
<20,24,25,28> PCI_PAR PAR VCCD0# VCCD0# <25,26> A_CD1#/CCD1# CBS_CCD1# <25,26>
34 74 138 CBS_CCD2#
Card PWR

<20,24,25,28> PCI_SERR# SERR# VCCD1# VCCD1# <25,26> A_CD2#/CCD2# CBS_CCD2# <25,26>

<20,24,25,28> PCI_PERR# 33 PERR# VPPD0 71 VPPD0 <25,26>
31 72 122 CBS_CREQ#
<20,24,25,28> PCI_STOP# STOP# VPPD1 VPPD1 <25,26> A_INPACK/CREQ# CBS_CREQ# <25,26>
S/W

28 105 CBS_CGNT#
<20,24,25,28> PCI_IRDY# IRDY# A_WE#/CGNT# CBS_CGNT# <25,26>
<20,24,25,28,35> PCI_TRDY# 29 TRDY#
19 130 CBS_CVS1
<6,10,17,20,24,25,28,32,35> PCIRST# PRST# A_VS1#/CVS1 CBS_CVS1 <25,26>
30 117 CBS_CVS2
<20,24,25,28> PCI_DEVSEL# DEVSEL# A_VS2#/CVS2 CBS_CVS2 <25,26>
<20,24,25,28,35> PCI_FRAME# 27 FRAME# GRST# 66 V_PRST# <17,25,26>
2 119 CBS_CRST#
3 <20,25> GNT#2 GNT# A_RESET/CRST# CBS_CRST# <25,26> 3
<20,25> REQ#2 1 REQ# VCC_CARD 109 CBS_VCC
1@PCI1510PGE_PQFP144

1@PCI1510PGE_PQFP144

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title
PCMCIA Controller PCI1510
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
Date: Tuesday, February 25, 2003 Sheet 27 of 44
A B C D E
 5 4 3 2 1

Place close to pin 25 AD[0..31]

<20,24,25,27,35> AD[0..31]

MINI PCI TYPE III CLK_PCI_MINI

<20,24,25,27,35> C/BE#[0..3]
C/BE#[0..3]

2
R428
D JP24 +3VMINI 33_0402_5% D
+3VMINI

1
+3VAUXMINI
2
1 TIP RING 2 +3VAUXMINI 1 2 +3VALW
C614 R400 @0_0603_5%
3 4 22P_0402_50V8J
8PMJ-3 8PMJ-1 1
5 8PMJ-6 8PMJ-2 6
7 8PMJ-7 8PMJ-4 8
9 8PMJ-8 8PMJ-5 10 1 2 +3V
11 12 R399 0_0603_5%
<24> WLAN_ACT_LED LED1_GRNP LED2_YELP WLAN_LINK_10_LED <24>
<32> RADIO_DISABLE# 13 LED1_GRNN LED2_YELN 14 WLAN_LINK_80211A <24>
15 CHSGND REVERVED 16
<20> PIRQD# 17 INTB# 5V 18 +5VMINI
19 3.3V INTA# 20 PIRQC# <20>
21 RESERVED RESERVED 22
23 GROUND 3.3VAUX 24
<16> CLK_PCI_MINI 25 CLK RST# 26 PCIRST# <6,10,17,20,24,25,27,32,35>
27 GROUND 3.3V 28
<20> REQ#1 29 REQ# GNT# 30 GNT#1 <20>
31 3.3V GROUND 32
AD31 33 34
AD31 PME# MINI_PME# <33>
AD29 35 36
AD29 RESERVED AD30 WLAN_LINK_80211A
37 GROUND AD30 38 2 1
AD27 39 40 R398 100K_0402_5%
AD25 AD27 3.3V AD28
41 AD25 AD28 42
43 44 AD26 WLAN_LINK_10_LED 2 1
C/BE#3 RESERVED AD26 AD24 R397 100K_0402_5%
45 C/BE#3 AD24 46
AD23 47 48 1 2 AD18
C
AD23 IDSEL R403 100_0402_5% WLAN_ACT_LED C
49 GROUND GROUND 50 2 1
AD21 51 52 AD22 R429 100K_0402_5%
AD19 AD21 AD22 AD20
53 AD19 AD20 54
55 56 M66EN 2 1
GROUND PAR PCI_PAR <20,24,25,27>
AD17 57 58 AD18 R401 1K_0402_5%
C/BE#2 AD17 AD18 AD16
59 C/BE#2 AD16 60
<20,24,25,27> PCI_IRDY# 61 IRDY# GROUND 62
63 3.3V FRAME# 64 PCI_FRAME# <20,24,25,27,35>
<21,24,27,32> CLKRUN# 65 CLKRUN# TRDY# 66 PCI_TRDY# <20,24,25,27,35>
<20,24,25,27> PCI_SERR# 67 SERR# STOP# 68 PCI_STOP# <20,24,25,27>
69 GROUND 3.3V 70
71 72 MPCIACT# 2 1 +3VAUXMINI
<20,24,25,27> PCI_PERR# PERR# DEVSEL# PCI_DEVSEL# <20,24,25,27>
C/BE#1 73 74 R405 100K_0402_5%
AD14 C/BE#1 GROUND AD15
75 AD14 AD15 76
77 78 AD13
AD12 GROUND AD13 AD11
79 AD12 AD11 80
AD10 81 82
AD10 GROUND AD9
83 GROUND AD09 84
AD8 85 86 C/BE#0
AD7 AD8 C/BE#0
87 AD7 3.3V 88
89 90 AD6
AD5 3.3V AD6 AD4
91 AD5 AD4 92
93 94 AD2
AD3 RESERVED AD2 AD0
95 AD3 AD0 96
+5VMINI 97 5V RESERVED_WIP 98 DIMM_SMCLK <13,14,16,20>
AD1 99 100
AD1 RESERVED_WIP DIMM_SMDATA <13,14,16,20>
101 GROUND GROUND 102
103 104 M66EN +3VAUXMINI +5VMINI +5VS
AC_SYNC M66EN L36
105 AC_SDATA_IN AC_SDATA_OUT 106
B B
107 AC_BIT_CLK AC_CODEC_ID0# 108 1 2
109 110 BLM21A05 _0805
AC_CODEC_ID1# AC_RESET#
111 MOD_AUDIO_MON RESERVED 112 1 1 1 1
113 114 C600
AUDIO_GND GROUND C596 C616 C610
115 SYS_AUDIO_OUT SYS_AUDIO_IN 116
117 118 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
AUDIO_OUTGND AUDIO_INGND 2 2 2 2
119 AUDIO_GND AUDIO_GND 120
121 122 MPCIACT#
RESEVED MPCIACT# 0.1U_0402_16V4Z
+5VMINI 123 VCC5VA 3.3VAUX 124

127 127 128 128

AMP 1318914
+3VMINI +3VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2
L35
1 1 1 1 1 BLM21A05 _0805

C613 C612 C599 C598 C609

10U_1206_10V4Z 1000P_0402_50V7K
WIRELESS SUPPORT ONLY 2 2 2 2 2

A A
0.1U_0402_16V4Z

Dell-Compal Confidential
Compal Electronics, Inc.
Title
MiniPci Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 28 of 44
5 4 3 2 1
 A B C D E F G H

+5VALW +5VDDA
+5VDDA
U26
5 C134
1 VOUT 1000P_0402_50V7K 1
1 VIN

1
1 1 HP_OUT_R 1 2
1 1 4 R6 C556 1 1
BYPASS C555
3 EN
C564 C562 @102K_0603_1% 0.1U_0402_16V4Z C481 C554 HP_OUT_L 1 2
@4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 @4.7U_0805_10V4Z
2

2
2 2 GND 2 2 C165
TPS793475DBV_SOT23-5 1 1000P_0402_50V7K
C558 4.7U_0805_10V4Z
@0.1U_0402_16V4Z

1
0.1U_0603_50V4Z
2 R10
@280K_0603_1%
<17,32,35,38,40> SUSP#

2
+5VDDA 1 2
L30
BLM21A05 _0805
+3VCC Place close to pin 2
R345 C486
AVDD_AC97 0.1U_0402_16V4Z 1 2 +3VS 1000P_0402_50V7K CLK_CODEC_14M
0_0805_5% 2 1

1
1 1 1 1 1 1
1 2 R341
C541 C551 C484 C491 C478 @10_0402_5%
0.1U_0402_16V4Z @4.7U_0805_10V4Z 4.7U_0805_10V4Z C487
2 2 2 2 2 2 1000P_0402_50V7K

2
2 2
LEFT <30> 1
0.1U_0402_16V4Z

25

38
U24

9
C477 C479
RIGHT <30> @10P_0402_50V8K
0.1U_0402_16V4Z

AVCC

AVCC

VCC

VCC
2

14 35 LEFT 1 2
AUX_L LINE_OUT_L C476 @1000P_0402_50V7K R350
15 36 RIGHT 1 2
AUX_R LINE_OUT_R @100K_0402_5%
16 37 MDMIC 1 2 MD_MIC <31>
VIDEO_L MONO_OUT C483 0.1U_0402_16V4Z
2 1
C544 0.1U_0402_16V4Z 17 39
VIDEO_R HP_OUT_L HP_OUT_L <30>
23 LIN_IN_L HP_OUT_R 41 HP_OUT_R <30>
24 LIN_IN_R 1 2 C500
BIT_CLK 6 1 2 IAC_BITCLK <21,31>
2 1 CD_L_R 1 2 18 R359 22_0402_5% @27P_0402_50V8J 1 2 CLK_CODEC_14M <16>
<23> INT_CD_L 1U_0603_10V4Z CD_L
R360 0_0603_5% C549 8 1 2 R342 0_0402_5%
SDATA_IN IAC_SDATA_IN0 <21>
2 1 CD_R_R 1 2 20 R357 47_0402_5% 1 2
<23> INT_CD_R 1U_0603_10V4Z CD_R
R363 0_0603_5% C547 2 C485
XTL_IN

2
2 1 CD_GNA 1 2 19 @22P_0402_50V8J
R362 @6.8K_0603_1% C546 1U_0603_10V4Z CD_GNA X4
2 1 21 @24.576MHz_16P
<30> MICIN MIC1
R361 @6.8K_0603_1%

1
2 1 1 2 22 3 1 2
R369 @51K_0402_5% C545 0.1U_0402_16V4Z MIC2 XTL_OUT
2 1 MDSPK 1 2 13 29 1 2 C542
<31> MD_SPK 0.033U_0402_16V4ZPHONE AFLT1
R368 0_0402_5% C550 C499 820P_0603_50V7K 0_0402_50V8J
MONO_IN 1 2 1 2 12 30 1 2 c542 have been change to 0ohm
3 <30> MONO_IN 0.1U_0402_16V4Z PC_BEEP AFLT2 3
R364 C553 C493 820P_0603_50V7K
2

47K_0402_5% 1 28
VREFOUT
<21,31> IAC_RST# 11 RESET#
R365 C552 27
4.7K_0402_5% 2700P_0603_50V7K REFFLT
<21,31> IAC_SYNC 10 SYNC
2
32 1 2 C490
1

FLT3D 1U_0603_10V4Z
<21,31> IAC_SDATAO 5 SDATA_OUT 1 1
1 0.1U_0402_16V4Z
2 1 45 31 C523 C498
C557 R344 2 ID0# BPCFG_00/NC_50 1U_0603_10V4Z
1@1K_0402_5% 46 ID1# FLTI_00/NC_50 33
0.033U_0402_16V4Z R343 @1K_0402_5% 2 2
FLTO_00/NC_50 34

2
2 EAPD SPK_SHUTDOWN#
<30> EAPD 47 EAPD NC_00/GPIO0_50 43 SPK_SHUTDOWN# <30> 1 1
44 R354 short the digital ground and analong ground
NC_00/GPIO1_50 C489 @100K_0402_5%
+3VCC 2 1 48 S/PDIF_OUT
R339 10K_0402_5% 40 @4.7U_0805_10V4Z
NC_00/HP_COMM_50 2 2
4 26

1
GND AGND
7 GND AGND 42

C492
1 @1U_0603_10V4Z
STAC9750_TQFP48
C471
1U_0603_10V4Z
CD_GNA 2
<23> CD_AGND 2 1

R367
0_0402_5%
1

R366
@6.8K_0603_1%
2

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title
AC97 CODEC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 29 of 44
A B C D E F G H
 A B C D E

+5VDDA Gain Setting GAIN0 GAIN1 AV(inv) INPUT

IMPEDANCE

0 0 6dB 90K ohm

1
1 2 +5VALW R379 R380
L31 10K_0402_5% @10K_0402_5% 0 1 10dB 70K ohm
+5VAMP BLM21A05 _0805
1 2 +5VDDA

2
L32 GAIN0 1 0 15.6dB 45K ohm
1 W=40mils
@BLM21A05_0805 * 1
GAIN1
1 1 21.6dB 25K ohm

1
1 1 1 1
R383 R384
C571 C582 C570 C583 @10K_0402_5% 10K_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z U28 10U_1206_10V4Z 0.1U_0402_16V4Z

16
15
6
2 2 2 2

2
VDD
PVDD1
PVDD2
Speaker Connector
1 2 C579 7 RIN+ GAIN0 2 GAIN0 JP16
0.47U_0603_16V4Z INTSPK_R+ 1
GAIN1 INTSPK_R- 1
GAIN1 3 2 2
INTSPK_L+ 3
RIGHT INTSPK_L- 3
<29> RIGHT 1 2 C584 17 RIN- 4 4
0.1U_0402_16V4Z 18 INTSPK_R+
ROUT+ ACES_85205-0400
15 mils trace
14 INTSPK_R-
ROUT-
1 2 C581 9 LIN+
0.47U_0603_16V4Z
4 INTSPK_L+ @DAN217_SOT23
LOUT+ D45 D43

1
LEFT 1 2 C576 5 @DAN217_SOT23
<29> LEFT 0.1U_0402_16V4Z LIN- INTSPK_L-
LOUT- 8

+3VS
2

+3VS

3
R389 12
100K_0402_5% NC
2 BYPASS 2
BYPASS 10
19 D44 D42
1

SHUTDOWN @DAN217_SOT23 @DAN217_SOT23

<29> SPK_SHUTDOWN#
1 1
+5VDDA

GND1
GND2
GND3
GND4
C588 C580
Q30 0.47U_0603_16V4Z @0.1U_0402_16V4Z 1 2
1

D 2N7002_SOT23 D D TI6017A2_TSSOP20 2 2
20
13
11
1
2 2 HP_PLUG 2 R327
<29> EAPD
G G G 1K_0402_5%
S S Q31 S Q32 1
3

1
2N7002_SOT23 2N7002_SOT23
R328 R157 C161
@2K_0402_5% 2K_0402_5% 4.7U_0805_10V4Z
2 EXT. MIC
<32> MUTE JP11

2
5

L14 4
BLM11A121SPT_0603
1 2 3
6
<29> MICIN 2 1 1 2 EXTMIC 2
L29 1
C548 BLM11A121SPT_0603
0.22U_0603_10V7K 1 7
8
C458
47P_0402_50V8J JA6333L-6S0-TR
+3VS 2
1

3 3
R431 +3VS
100K_0402_5% C621
+3VS 0.1U_0402_16V4Z +5VDDA +5VDDA
1 2
2

U15
5

U14 R430 1
10K_0402_5% NC R436 R437 +3VS
1 5
P

<32> BEEP IN1 VCC

4 1 2 2 100K_0402_5% 100K_0402_5%
O A
2 IN2 Y 4
G

2
1 3 C619 R125
2

SN74AHC1G08HDCK_TSSOP5 GND 100K_0402_5%

1 2 1 2 1 2
3

TC7SH14FU_SSOP5 C624
C617 R434 0.1U_0402_16V4Z @0.1U_0402_16V4Z HP OUT
0.1U_0402_16V4Z 2 2K_0402_5% JP9

1
HP_PLUG 5
+3V POWER <33> HP_PLUG
C620
1 2 MONO_IN R122 @220U_D_6.3M_R40 L12 4
MONO_IN <29>
R132 2 1 @0_0402_5% 0_0402_5% C142 BLM11A121SPT_0603
1

C 1U_0603_10V4Z 2 PR_RIGHT PR

+
<29> HP_OUT_R 1 2 1 1 2 3
<25,27> PCM_SPK# 1 2 1 2 2 6
R433 C623 B Q13 PR_LEFT PL

+
<29> HP_OUT_L 1 2 1 2 1 2 2
2K_0402_5% 0.1U_0402_16V4Z E 2SC2411K_SOT23 R155 L13 1
3

0_0402_5% C154 BLM11A121SPT_0603

1 1
@220U_D_6.3M_R40 7
8
C155 C144
1 2 1 2 47P_0402_50V8J 2 2
<21> ICH_SPKR
R432 C622 C636 JA6333L-6S0-TR
2K_0402_5% 0.1U_0402_16V4Z

+
1 2
47P_0402_50V8J
1

220U_10V_M
4 4
D15

+
1 2
1SS355_SOD323
C635
2

220U_10V_M
Dell-Compal Confidential
Compal Electronics, Inc.
Title
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 30 of 44
A B C D E
 5 4 3 2 1

+3V

1 +5VMDC 1 2
+3VMDC +5VALW
1 1 1 C626 R435
1 2 @1000P_0402_50V7K @1000P_0402_50V7K @0.1U_0402_16V4Z @0_0805_5%
+3V R443 0_0805_5% C627 C628 C625 2
1 2 @0.1U_0402_16V4Z
+3VALW R444 @0_0805_5% 2 2 2
1 2 JP25

C630 C629 1 2
0.1U_0402_16V4Z <29> MD_MIC MONO_OUT/PC_BEEP AUDIO_PWDN
4.7U_0805_10V4Z 3 4
D 2 1 AGND MONO_PHONE MD_SPK <29> D
5 AUXA_RIGHT RESERVED 6
7 AUXA_LEFT GND 8
9 CD_GND +5V 10
11 CD_RIGHT RESERVED 12
13 CD_LEFT RESERVED 14
15 GND PRIMARY_DN 16 1 2
As close to P17 17 18 R438 10K_0402_5%
+3V 1: Have primary CODEC on mother board
+3VMDC 3.3Vaux RESERVED
19 GND RESERVED 20
21 3.3Vmain AC97_SYNC 22 IAC_SYNC <21,29>
23 24 2 R439 1
<21,29> IAC_SDATAO AC97_SDATA_OUT AC97_SDATA_IN1 IAC_SDATA_IN1 <21>
25 26 @22_0402_5%
<21,29> IAC_RST# AC97_RESET# AC97_SDATA_IN0
27 GND GND 28 2 1
29 30 R441 10_0402_5%
AC97_MSTRCLK AC97_BITCLK
1 2 IAC_BITCLK <21,29>
R442 22_0402_5%
FOX_QT8A0301-3011

MDC Conn.

MDC Note
Touch Pad & Status LED Conn. Pin 1 is NC for Pctel and connexant MDC modem
C C
Pin 2 is NC for Pctel and connexant MDC modem
JP13
TP_CLK TP_DATA
<32> TP_CLK 1 2 TP_DATA <32>
3 4 +5VS
+5VS 5 6
7 8 PWR_LED# +5VALW
9 10 PWR_LED# <33>
ACT_LED# BATT_LED#
<23> ACT_LED# 11 12 BATT_LED# <33>
CHARGE_LED#
<33> CHARGE_LED# 13 14 Screw Hole
15 16
+3VALW 17 18 LID_SW# <32>
H7 H8 H13 H12 H3 H19 H11 H5 H4 H2 H10 H16
19 20 @C315D126 @C315D126 @C315D126 @C315D126 @C394D118 @C394D118 @C394D118 @C315D118 @C394D118 @C394D118 @C394D118 @C394D118
ACES 87216-2012_20P

1
1 2 TP_CLK
C193 @220P_0603_50V8J H14 H17 H20 H21 H28 H27 H26 H18 H29 H6 H34
@C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C138D138N @O197x138D197x138N @C315D177 @C177D87

1 2 TP_DATA
C171 @220P_0603_50V8J

1
CP1
5 4 CHARGE_LED#
6 3 ACT_LED#
7 2 PWR_LED# H33 H30 H32 H15 H25 H9 H37
8 1 BATT_LED# @O335x79D315x59@O335x79D315x59@O335x79D315x59@O335x79D315x59@H_O177x99D157x79 @O335x79D315x59 @C177D79
B B
@220P_1206_8P4C_50V8K
1

1
H38 H23 H22 H1
C138D48 C197B256D157 C197B256D157 C256D87
1

1
Fiduial Mark
FD1 FD2 FD3 FD4 FD5 FD6 FD7
1 1 1 1 1 1 1

@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK

FD8 FD9 FD10 FD11 FD12 FD13 FD14

1 1 1 1 1 1 1

@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK
A A

FD15 FD16 FD17 FD18

1 1 1 1
Dell-Compal Confidential
@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK Compal Electronics, Inc.
Title
MDC / SWITCH Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 31 of 44
5 4 3 2 1
 A B C D E

EC_AVCC
+3VALW +RTCVCC
0.1U_0402_10V6K 1 2 EC_3VDD 2 BD_ID 0V 0.5V 1.0V 1.5V
+3VALW +3VS
1 1 1 1 R411 0_0402_5%
1 C608

123
136
157
166

161
C611 C607 C595 C589 1U_0603_10V4Z REV 0.1 0.2 0.3 1.0

16

34
45

95
4.7U_0805_10V4Z 1000P_0402_50V7K C602 U32 1
2 2 2 2 0.1U_0402_16V4Z /10K 100K/10K 100K/25K 100K/43K

VDD

AVCC
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

VBAT
2
0.1U_0402_16V4Z
+5VALW I/O Address
7 81 BATT_TEMP BADDR1-0 Index Data
<20,25,27> SIRQ SERIRQ AD0 BATT_TEMP <36>
8 82 0 0 2E 2F
LDRQ# AD1

1
BLM18PG600SN1_0603 VBATT 0 1 4E 4F
L33
<21> LFRAME# 9
15
LFRAME# AD2 83
84 R393
* 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
<21> LAD0 LAD0 Host interface AD3 BATT-OVP <37>
1 2 14 87 91K_0402_5% 1 1 Reserved
1 +3VALW EC_AVCC <21> LAD1 LAD1 IOPE0AD4 1
2 1 <21> LAD2 13 LAD2 IOPE1/AD5 88
10 89 BATT_CHGI
<21> LAD3

2
C594 C593 CLK_PCI_LPC LAD3 AD Input IOPE2/AD6
<16> CLK_PCI_LPC 18 LCLK IOPE3/AD7 90 ADP_I <37,39>
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 EC_RST 19 93 BD_ID
1 2 +3VALW RESET1# DP/AD8
R402 10K_0402_5% 22 94
SMI# DN/AD9

1
1 2 ECAGND 23 PWUREQ# 2
L34 99 R394
DA0 EN_FAN2 <7>
BLM18PG600SN1_0603 100 10K_0402_5% C592
DA output DA1 EN_FAN1 <7> 0.1U_0402_10V6K
<21> SCI# 31 IOPD3/ECSCI# DA2 101 IREF <37> 1
102 IREF2 <37>

2
DA3
5 32 ECAGND
ADB[0..7] <20> GATEA20 GA20/IOPB5 IOPA0/PWM0
ADB[0..7] <33> <20> KBRST# 6 KBRST/IOPB6 IOPA1/PWM1 33 BEEP <30>
IOPA2/PWM2 36
KBA[0..19] KSI[0..7] PWM 37
KBA[0..19] <33> <33,34> KSI[0..7] IOPA3/PWM3 ACOFF <37>
KSI0 71 or PORTA 38
KSO[0..15] KBSIN0 IOPA4/PWM4 VLBA# <21>
<33> KSO[0..15] KSI1 72 39
KBSIN1 IOPA5/PWM5 EC_ON <34>
KSI2 73 40
KBSIN2 IOPA6/PWM6 LID_OUT# <21>
KSI3 74 43
KBSIN3 IOPA7/PWM7 PCM_SUSP# <25,26,27>
KSI4 77
KSI5 KBSIN4 KSO16
78 KBSIN5 IOPB0/URXD 153 KSO16 <34>
Place closely pin 18 KSI6 79 154 KSO17 ENV0 ENV1 TRIS
KBSIN6 Key matrix scan IOPB1/UTXD KSO17
1 2 TP_DATA KSI7 80 162 EC_DEBUG
+5VS R407 10K_0402_5% CLK_PCI_LPC KBSIN7 IOPB2/USCLK SMB_EC_CK1
163 SMB_EC_CK1 <17,18,33,36>
IRE 0 0 0
KSO0 PORTB IOPB3/SCL1 SMB_EC_DA1
49 KBSOUT0 IOPB4/SDA1 164 SMB_EC_DA1 <17,18,33,36>

1
TP_CLK KSO1 OBD 0 1 0
1
R404
2
10K_0402_5% R406 KSO2
50
51
KBSOUT1 IOPB7/RING/PFAIL/RESET2 165 PCIRST# <6,10,17,20,24,25,27,28,35> *
10_0402_5% KSO3 KBSOUT2
52 KBSOUT3 IOPC0 168 PWRBTN# <21> DEV 1 0 0
KSO4 53 169 SMB_EC_CK2
KBSOUT4 IOPC1/SCL2 SMB_EC_CK2 <6,8>
2 1 LID_SW# KSO5 56 170 SMB_EC_DA2 PROG 1 1 0
+3VALW SMB_EC_DA2 <6,8>
2

R410 100K_0402_5% KSO6 KBSOUT5 IOPC2/SDA2

1 57 KBSOUT6 IOPC3/TA1 171 FAN1_TACH <7>
KSO7 58 PORTC 172
2 KBSOUT7 IOPC4/TB1/EXWINT22 EC_WAKEUP# <20> 2
C597 KSO8 59 175 SHBM=1: Enable shared memory with host BIOS
15P_0402_50V8J KBSOUT8 IOPC5/TA2 EC_THRM# <21>
KSO9 60 176 TRIS=1: While in IRE and OBD, float all the
2 KBSOUT9 IOPC6/TB2/EXWINT23 FAN2_TACH <7>
KSO10 61 1 signals for clip-on ISE use
KBSOUT10 IOPC7/CLKOUT PM_PWROK <10,21,34>
KSO11 64 KBSOUT11

1
+5VS KSO12 65 26
KBSOUT12 IOPD0/RI1/EXWINT20 ACIN <20,36,38>
RP7 KSO13 66 29 R11
KBSOUT13 PORTD-1 IOPD1/RI2/EXWINT21 PM_SLP_S4# <21>
PS2_CLK 1 8 KSO14 67 30 100K_0402_5%
KBSOUT14 IOPD2/EXWINT24/RESET2 PM_SLP_S3# <16,21>
PS2_DATA 2 7 KSO15 68
KBD_DATA KBSOUT15
3 6 2 ON/OFF <34>

2
KBD_CLK EC_TINIT# IOPE4/SWIN
4 5 105 TINT# IOPE5/EXWINT40 44 PM_SLP_S5# <21>
EC_TCK 106 PORTE 24
TCK IOPE6/LPCPD/EXWIN45 EXTVGA_IN# <17>
8.2K_8P4R_1206_5% EC_TDO 107 25
TDO JTAG debug port IOPE7/CLKRUN/EXWINT46 CLKRUN# <21,24,27,28>
EC_TDI 108
EC_TMS TDI KBA0
109 TMS IOPH0/A0/ENV0 124
125 KBA1
+3VALW KBD_CLK IOPH1/A1/ENV1 KBA2
110 PSCLK1/IOPF0 IOPH2/A2/BADDR0 126
RP6 KBD_DATA 111 127 KBA3
FSEL# PS2_CLK PSDAT1/IOPF1 IOPH3/A3/BADDR1 KBA4
1 8 114 PSCLK2/IOPF2 IOPH4/A4/TRIS 128
SELIO# 2 7 PS2_DATA 115 PORTH 131 KBA5
FR D# TP_CLK PSDAT2/IOPF3 PS2 interface IOPH5/A5/SHBM KBA6
3 6 <31> TP_CLK 116 PSCLK3/IOPF4 IOPH6/A6 132
EC_SMI# 4 5 TP_DATA 117 133 KBA7
<31> TP_DATA PSDAT3/IOPF5 IOPH7/A7
LID_SW# 118
<31> LID_SW# PSCLK4/IOPF6
8.2K_8P4R_1206_5% 119 138 ADB0
<36> PS_ID PSDAT4/IOPF7 IOPI0/D0
139 ADB1
IOPI1/D1 ADB2
IOPI2/D2 140
141 ADB3
C RY1 PORTI IOPI3/D3 ADB4 +3VALW
158 32KX1/32KCLKIN IOPI4/D4 144
R423 20M_0603_5% 145 ADB5
C RY2 IOPI5/D5 ADB6
1 2 160 32KX2 IOPI6/D6 146
147 ADB7 (ENV1)
32.768KHZ_12.5P R424 IOPI7/D7 KBA1 2 1
2 1 150 FR D# R412 10K_0402_5%
3 PORTJ-1 IOPJ0/RD FRD# <33> 3
1 1 120K_0402_5% 151 FWR# (BADDR0)
X5 IOPJ1/WR0 KBA2 2 1
C615 C618 152 SELIO# R414 10K_0402_5%
12P_0402_50V8J SELIO# SELIO# <33>
10P_0402_50V8K (BADDR1)
2 2 EC_SMI# KBA3
<21> EC_SMI# 62 IOPJ2/BST0 IOPD4 41 SCRLED# <34> 2 1
LAN_DISABLE# 63 42 R416 @10K_0402_5%
<24> LAN_DISABLE# IOPJ3/BST1 PORTD-2 IOPD5 NUMLED# <34>
<17> G_RST# 2 1 69 IOPJ4/BST2 IOPD6 54 CAPSLED# <34> (SHBM)
R390 0_0402_5% 70 PORTJ-2 55 KBA5 2 1
<21> EC_SWI# IOPJ5/PFS IOPD7
75 R418 10K_0402_5%
<28> RADIO_DISABLE# IOPJ6/PLI
76 143 KBA8
<16,21> PM_SLP_S1# IOPJ7/BRKL_RSTO IOPK0/A8
142 KBA9
IOPK1/A9 KBA10
<35,40> SYSON 148 IOPM0/D8 IOPK2/A10 135
149 PORTK 134 KBA11
<17,29,35,38,40> SUSP# IOPM1/D9 IOPK3/A11
155 130 KBA12
<35,41> VR_ON IOPM2/D10 PORTM IOPK4/A12
R415 156 129 KBA13
<21,41> VGATE IOPM3/D11 IOPK5/A13_BE0 +3VALW
2 1 3 121 KBA14
<21,34> RSMRST# IOPM4/D12 IOPK6/A14_BE1
@0_0402_5% 4 120 KBA15
<30> MUTE IOPM5/D13 IOPK7/A15_CBRD
27 JP17
<41> VR_TT# IOPM6/D14
28 113 KBA16 1
<17,18> BKOFF# IOPM7/D15 IOPL0/A16 1
1 2 112 KBA17 EC_TINIT# 2 C591 0.01U_0402_25V7Z
FSEL# PORTL IOPL1/A17 KBA18 EC_TCK 2 BATT_CHGI ECAGND
<33> FSEL# 173 SEL0# IOPL2/A18 104 3 3 1 2
R417 174 103 KBA19 EC_TDO 4
100K_0402_5% SEL1# IOPL3/A19 EC_TDI 4
47 CLK IOPL4/WR1# 48 FSTCHG <37> 5 5
EC_TMS 6 BATT_TEMP 1 2
6 C587 0.01U_0402_25V7Z
7 7
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7

KSO16
NC10

8
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

KSO17 8
9 9
EC_DEBUG 10 C585 0.01U_0402_25V7Z
10 BATT-OVP ECAGND
1 2
17
35
46
122
159
167
137

96

11
12
20
21
85
86
91
92
97
98

+3VALW @96212-1011S
+3VALW
VBATT 1 2
SUS_STAT# <17,21>
2

4 ECAGND C586 0.01U_0402_25V7Z 4

2

R422
3.3K_0402_5% +3VALW R421 PC87591L-VPCN01 A2_LQFP176
100K_0402_5%
2
G
14

Dell-Compal Confidential
1

4 1 3
P

FWE# A EC_FLASH# <21>

6
Compal Electronics, Ltd.
D

<33> FWE# O
B 5 FWR# Q35
G

2N7002_SOT23 Title
U33B EC PC87591L
7

SN74LVC32APWLE_TSSOP14
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom Abacus-MT LA-1682 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 32 of 44
A B C D E
 A B C D E

Output Port
Input Port
+5VALW

1 2 +3VALW 1 2
+3VS
R386 100K_0402_5%
+3VALW 1 2 C575
1 R233 100K_0402_5% 0.1U_0402_16V4Z 1

20
1 2
1 2 C577 0.1U_0402_16V4Z U27
R382 100K_0402_5% +3VALW ADB0 3 2

VCC
D0 Q0 PWR_LED# <31>
ADB1

20
4 D1 Q1 5 CHARGE_LED# <31>
U30 ADB2 7 6
D2 Q2 BATT_LED# <31>
2 18 ADB0 1 2 ADB3 8 9

VCC
<17,19> M_SEN# 1A1 1Y1 0.1U_0402_16V4Z D3 Q3 VCHG <37>
4 16 ADB1 C605 ADB4 13 12
<6,21> PROCHOT# 1A2 1Y2 D4 Q4
6 14 ADB2 ADB5 14 15 90W/130W# <37,39>
PME# 1A3 1Y3 ADB3 ADB6 D5 Q5

14
8 1A4 1Y4 12 17 D6 Q6 16
11 9 ADB4 U33C ADB7 18 19
<30> HP_PLUG 2A1 2Y1 D7 Q7
13 7 ADB5 KBA2 9

P
<10,17,18> ENABKL 2A2 2Y2 A
15 5 ADB6 8 AA 11

GND
2A3 2Y3 ADB7 SELIO# O LARST# CP
<36> 9C/12C#/8C# 17 2A4 2Y4 3 10 B 1 MR

G
1 SN74LVC32APWLE_TSSOP14 SN74HCT273PW_TSSOP20

GND

10
+3VALW 1G
19 2G
SN74LVC244APWR_TSSOP20

10
14
+5VALW 1 2 1 2
U33D R377 20K_0402_5%
KBA1 12 C569

P
A
O 11 C C 1U_0603_10V4Z
SELIO# 13
<32> SELIO# B G
SN74LVC32APWLE_TSSOP14 NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#
7

+5VALW

+5VALW

1
1 2 R375
2 100K_0402_5% 2
+3VALW C590
+3VALW 0.1U_0402_16V4Z U29

2
8 VCC A0 1
1

+5VALW 7 2
R387 AA WP A1
1 2 <17,18,32,36> SMB_EC_CK1 6 SCL A2 3
10K_0402_5% R419 100K_0402_5% 5 4
<17,18,32,36> SMB_EC_DA1 SDA GND
1 2 SMB_EC_DA1
CC 1 2 R453 8.2K_0402_5% AT24C16_SO8
2

R420 100K_0402_5% 1 2 SMB_EC_CK1

LAN_PME# 1 2 R454 8.2K_0402_5% EC I2C Bus Address:
<24> LAN_PME#
R49 0_0402_5%
MINI_PME# 1 2 24C164: 1011xxx R/W#
<28> MINI_PME#
R48 0_0402_5% 24C16: 1010xxx R/W#
PCM_PME# 1 2 PME#
<25,27> PCM_PME#
R45 0_0402_5%

+3VALW
JP33
@6278-34P-DEBUG +3VALW
<32> KBA[0..19] U16

KSO0 34 BIOS_RST# KBA0

4 5 33 21 A0 VCC0 31
KSO1 3 6 CP2 KBA0 KBA1 20 30 1 1
KSO2 32 KBA1 KBA2 A1 VCC1
2 7 31 19 A2
KSO3 1 8 @100P_1206_8P4C_50V8K KBA2 KBA3 18 C632 C631
30 KBA3 KBA4 A3 ADB0 0.1U_0402_16V4Z 0.1U_0402_16V4Z
3 Internal KB connector 29 KBA4 KBA5
17
16
A4 D0 25
26 ADB1 2 2 3
CP3 28 KBA5 KBA6 A5 D1 ADB2
27 15 A6 D2 27
KSO12 4 5 KBA6 KBA7 14 28 ADB3
KSO13 26 KBA7 KBA8 A7 D3 ADB4
3 6 25 8 A8 D4 32
KSO14 2 7 KBA8 KBA9 7 33 ADB5
KSO15 24 KBA9 KBA10 A9 D5 ADB6
1 8 23 36 A10 D6 34
KBA10 KBA11 6 35 ADB7
@100P_1206_8P4C_50V8K 22 KBA11 KBA12 A11 D7
21 5 A12 ADB[0..7] <32>
CP4 KBA12 KBA13 4
KSO4 4 20 KBA13 KBA14 A13
5 3 10 1 2
INT_KBD CONN. KSO5 3 6
19
18
KBA14 KBA15 2
A14
A15
RP#
NC 11 R440 100K_0402_5%
+3VALW
KSO6 2 7 KBA15 KBA16 1 12
KSO7 1 17 KBA16 KBA17 A16 READY/BUSY#
8 16 40 A17 NC0 29
KBA17 KBA18 13 38 BIOS_RST#
@100P_1206_8P4C_50V8K 15 KBA18 KBA19 A18 NC1
14 37 A19
CP5 KBA19
KSI7 13 ADB0 FSEL#
4 5 12 <32> FSEL# 22 CE#
KSI6 3 6 ADB1 FR D# 24 23
11 <32> FRD# OE# GND0
KSI0 ADB2 FWE#
KSO10

KSO14

KSO12

KSO6

KSO7

KSO2

KSO1
KSI3

KSO0
KSI4

KSI6

KSI1

2 7 10 <32> FWE# 9 WE# GND1 39

KSI1 1 8 ADB3
9 ADB4
@100P_1206_8P4C_50V8K 8 ADB5 SST39VF080-70_TSOP40
CP6 7 ADB6
25

23

21

19

17

15

13

11

6
9

JP32 KSO8 4 5 ADB7

KSO9 3 5 FWE#
6
Dummy

23

21

19

17

15

13

11

KSO10 2 4 FR D#
7 3
KSO11 1 8 FSEL#
24

22

20

18

16

14

12

10

2
8

@100P_1206_8P4C_50V8K 1
24

22

20

18

16

14

12

10

CP7
KSI2 4 5
KSO15

KSO11

KSO13

KSI3
KSO3

KSO8

KSO4
KSI0

KSO5
KSI2

KSI5

KSO9

KSI7

3 6
4 KSI4 4
2 7
KSI5 1 8

@100P_1206_8P4C_50V8K
Dell-Compal Confidential
FOX_GS22250-0001
can swap Compal Electronics, Inc.
KSO[0..15] Title
<32> KSO[0..15]
EC Extend I/O KB Conn. & BIOS
KSI[0..7]
<32,34> KSI[0..7] THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 33 of 44
A B C D E
 A B C D E

+3VALW
RTC Battery

1
BATT1
R186
2 1 RTCPWR 100K_0402_5%
Power BTN
PM_PWROK <10,21,32> D12

2
1 ON/OFF
ON/OFF <32>
ML1220T13RE ON/OFFBTN# 3
2 EC_ON# <39>

1
1 C638 D41
@1000P_0402_50V7K +3VALW DAN202U_SC70

VL

1
1 2 +RTCVCC 1
1 1000P_0402_50V7K

1
VL R188 C209

2
4.7K_0402_5% D16

1
D17 1SS355_SOD323 CHGRTC RLZ20A_LL34
BAS40-04_SOT23 2
2 1

2
1

2
R449 EC_ON 22K
<32> EC_ON 1 2 2
R447 470K_0402_5% R189

100K
1 2 +RTCVCC 22K
100K_0402_5% R448 470K_0402_5% 22K_0402_5%

100K
2
Q21
3 1 1 2 WHEN R=0,Vbe=1.35V DTC124EK_SOT23
SM_INTRUDER# <20>
2

3
WHEN R=33K,Vbe=0.8V

1
D C633
2 Q41 0.1U_0402_16V4Z
G 2N7002_SOT23 Q22
S DTC115EKA_SOT23
3
+3VALW

1
C639
1

D +3VALW 0.1U_0402_16V4Z
SHDN_1632 <38> +3VALW 2 +3VALW
2 Q40
<38> SHDN#
G 2N7002_SOT23

1
S
3

R455
150K_0402_5%

14

14
U56A U56B
R510

P
2
2 1 1 I O 2 3 I O 4 RSMRST# <21,32>

G
2 2
1M_0402_5% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
1
USB Over Current

7
C640
0.1U_0402_16V4Z
2
+5VALW USB_AS USB_BS +3VALW
1

R212
R12 100K_0402_5%
USB_AS
USB_A
USB PORT USB_B
USB_BS
2

U6
1 8 1 2 OVCUR#0 1 2 2 1
GND OC1# OVCUR#0 <21>
2 7 100K_0402_5% R210 47K_0402_5% L38 1 1 L40
IN OUT1

1
1 3 6 FBM-11-451616-800T 1 1 FBM-11-451616-800T
EN1# OUT2 OVCUR#2 + + + +
4 EN2# OC2# 5 1 2 OVCUR#2 <21>
C16 R211 47K_0402_5% 1 1 C641 C10 C12 C231 C229 C642
0.1U_0402_16V4Z TPS2042ADR_SO8 @100U_4A_10V 0.1U_0402_16V4Z @100U_4A_10V

2
2 C238 C237 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Note: 2 2 150U_D3_10VM 150U_D3_10VM
USB_AS=USB_BS=Trace width=40mils 0.1U_0402_16V4Z
JP4
1 VCC VCC 5
<35> SYSON# USB0D- 2 6 USB2D-
USB0D+ D0- D1- USB2D+
3 D0+ D1+ 7
4 VSS VSS 8
3 3
1 1 10 G2 G1 9 1 1
12 G4 G3 11
C232 C11 C13 C230
@15P_0402_50V8J FOX_UB11123-8Z4-HT @15P_0402_50V8J
2 2 2 2

@15P_0402_50V8J
@15P_0402_50V8J

C805 @100P_0402_50V8J
KSO16 1 2
2 1 2 1
R209 0_0402_5% R9 0_0402_5%

JP5 U21 U17

<32> KSO16 KSO16 1 2 USBP0- USB0D- USB2D- USBP2-
1 2 KSI0 <32,33> <21> USBP0- 1 4 4 1 USBP2- <21>
<32> CAPSLED# 3 3 4 4 SCRLED# <32>
5 5 6 6 NUMLED# <32>
7 8 ON/OFFBTN# USBP0+ USB0D+ USB2D+ USBP2+
7 8 <21> USBP0+ 2 3 3 2 USBP2+ <21>
+3VS 9 9 10 10 +3VALW
@JTS0402-02_4P @JTS0402-02_4P

SUYIN_12750AR-10G2T-9 2 1 2 1
R208 0_0402_5% R8 0_0402_5%

Power SW Function Button

4 4

Dell-Compal Confidential
Compal Electronics, Inc.
Title
Power OK/Reset/RTC battery/USB Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 34 of 44
A B C D E
 A B C D E

+12VALW

1
+12VALW
+1.5VALW to +1.5VS Transfer R445
68K_0402_5%

1
+1.5VALW +1.5VS R451

2
100K_0402_5%
U66
8 1 0.1U_0402_16V4Z

2
D S

1
7 2 SUSON SYSON#
D S <34> SYSON#

1
1 6 3 1 1 R446
D S

1
1 R378 D 47K_0402_5% 1
5 D G 4 1

1
C568 C573 C572 470_0805_5% D Q2
<32,40> SYSON 2
10U_1206_10V4Z SI4800DY_SO8 10U_1206_10V4Z SYSON# 2 C634 G 2N7002_SOT23

2
2 2 2 G 0.01U_0402_25V7Z S

1 2

3
Q39 S 2

2
D 2N7002_SOT23
2 SUSP Q61
G R450 @SM05_SOT23
S 1M_0402_5%

3
Q60
RUNON 2N7002_SOT23

1
+CPU_CORE
+3VALW +12VALW

1
R427

1
@330_0603_5%
R425 R426
@100K_0402_5% 10K_0402_5%

2
1

2
1
D
Q38
+3VALW to +3V Transfer 2
G @2N7002_SOT23
<19> SUSP
S

1
+3VALW +3V D
2 Q36
<17,29,32,38,40> SUSP#

1
D G 2N7002_SOT23
U70
8 1 0.1U_0402_16V4Z VR_ON 2 Q37 S
<32,41> VR_ON

3
D S

1
7 2 G @2N7002_SOT23
D S
1
2 2
6 3 1 1 S

3
D S R187 R456
5 D G 4
1 C208 C210 470_0402_5% 100K_0402_5%
SI4800DY_SO8

2
C207 2 2
2

22U_1206_10V4Z
2
1

22U_1206_10V4Z D
2 SYSON#
SUSON G +5VS
S Q20
3

2N7002_SOT23
CLK_PCI_DEBUG JP27
<20,24,25,27,28> AD9 1 2 PCI_TRDY# <20,24,25,27,28>

2
<20,24,25,27,28> PCI_FRAME# 3 4 PCIRST# <6,10,17,20,24,25,27,28,32>
R458
5 6 CLK_PCI_DEBUG <16>
33_0402_5%
7 8 C/BE#3 <20,24,25,27,28>
<20,24,25,27,28> C/BE#2 9 10 C/BE#1 <20,24,25,27,28>
<20,24,25,27,28> AD8 AD7 <20,24,25,27,28>

1
11 12
+5VALW to +5VS Transfer 1 <20,24,25,27,28> AD5
<20,24,25,27,28> AD1
13 14 AD3 <20,24,25,27,28>
15 16 AD0 <20,24,25,27,28>
C637 <20,24,25,27,28> AD2
+12VALW 10P_0402_50V8K 17 18 AD4 <20,24,25,27,28>
<20,24,25,27,28> AD6 C/BE#0
2 19 20 C/BE#0 <20,24,25,27,28>
@AMP 5-175638-0
1

+5VALW +5VS
R408
100K_0402_5% U31 22U_1206_10V4Z
8 D S 1
7 2
Debug PORT
2

D S
1

1M_0402_5% 6 3
D S R413
5 D G 4 1 1
1

3 470_0805_5% 3
1
1

D R409 SI4800DY_SO8 C603 C604

SUSP 2 C601 RUNON
2

G 0.01U_0402_25V7Z 2 2 +3V
S 2
3

Q33
2N7002_SOT23 +3V
1

1
0.1U_0402_16V4Z D

2
2 SUSP R567 +3V
+5VALW G 47K_0402_5% R568
S Q34
3

249K_0402_1%

5
1 2N7002_SOT23 U81A

1
+ C606 1 6
150U_D3_10VM <41> VID_PWRGD I O ENLL <41>

G
2 SN74LVC2G07_SOT23-6

2
1
C32
@0.1U_0402_16V4Z +3V
+3VALW to +3VS Transfer 2
+3VALW +3VS

5
U81B
U20 C131

P
8 1 0.1U_0402_16V4Z 3 4
D S I O H_VID_PWRGD <6>
7 D S 2 1 1
1

G
6 D S 3
1 5 4 R100 SN74LVC2G07_SOT23-6

2
D G C133 470_0402_5%
1 2 22U_1206_10V4Z2
4 + C145 SI4800DY_SO8 4
150U_D2_6.3VM C132
CPU LEVEL SHIFT
2

10U_1206_10V4Z
2 2
1

D
RUNON 2 SUSP
Dell-Compal Confidential
G
S Q19 Compal Electronics, Inc.
3

2N7002_SOT23
Title
DC/DC Circuit / Debug Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 35 of 44
A B C D E
 A B C D E

Detector

+3VALWP
PL24
BLM11A121S_0603 BATT+

2
2 1 PSID_IN
PR161
BATT++ 100K_0402_1%

BATT+
1 1

1
PL5
PCN1 VIN FBM-L18-453215-900LMA90T_1812 PR162
PL25 1 2 BATT++ 1 2
1 FBM-L18-453215-900LMA90T_1812 1K_0402_5% 9C/12C#/8C# <33>
Low_PWR
9 GND_4

2
2 ADPIN 1 2
DC+_1 PC43 PC44 PR163
8 GND_3

1
3 0.1U_0805_25V7K 0.1U_0805_25V7K @1K_0402_5%

2
DC+_2

100P_0603_50V8G

100P_0603_50V8G
1000P_0603_50V8J

1000P_0603_50V8J
7 4 PR309

1
GND_2 DC-_1

1
PC240

PC241
10_1206_5%

1
PC242

PC243
6 5

1 2
GND_1 DC-_2
MH1
MH2

2
PZD6 PR45
MH1
MH2

DC PW R JACK RLZ24B 1 2 BATT_TEMP

1K_0402_5% BATT_TEMP <32>

2
ADPGND 1 2

1
PCN2
PL26 1
FBM-L18-453215-900LMA90T_1812 BATT+
BATT+ 2
3 PD6
ID

1
PC219 4
2200P_0603_50V7K B/I @BAS40-04_SOT23
5

2
TS
6

2
SMD
SMC 7
+3VALW +3VALW 10 8
GND GND-

1K_0402_5%
11 9 PR47
GND GND-

PR46
1 2
1

1
2 PR385 +3VALWP 2
PR384 25.5K_0402_1%
4.7K_0402_5% SUYIN-200275MR009G516ZL 9P
@4.7K_0402_5%

1
2

PR383 PR48
0_0603_5% 1 2 SMB_EC_DA1 <17,18,32,33>
PSID_IN 1 2 PS_ID <32> 100_0402_5%
2 PR49 1

1
<17,18,32,33> SMB_EC_CK1 100_0402_5%

1
PD7
D

1 3
PQ105
3

PD8 @BAS40-04_SOT23

2
@0_0603_5%

PQ106 @2N7002_SOT23 @BAS40-04_SOT23

G
2
1

SM05_SOT23
PR386

3
+5VALWP

ACIN
2

+5VALWP PR51
1

2.2M_0603_5%
PCN2 battery connector pin assignment 1 2 2 1 B+
VL VS

S MART Battery: PR50

100K_0603_1%
1.BATT+

1
1
2.BATT+
PR52
PC52 499K_0603_1%
3 . 9C/12C#/8C# 0.01U_0603_50V7K

2
PU5A
4 .B/I

2
8
3 LM393M_SO8 3

5. TS PD9 3

P
+
2 1 1
Vin Detector 6 . S M B _ E C_ DA1 <6,38> SHDN_1632# O
- 2

499K_0603_1%
7. SMB _EC_CK1 RB751V_SOD323

1
191K_0603_1%

PR53
17.90V/17.24V 8.GND

4
1

1
PD10 PC49

PR55
PC50 PC51 1000P_0603_50V8J
9.GND 2 1

2
<37> ACON 0.1U_0603_25V7K 1000P_0603_50V8J

2
RB751V_SOD323
PR56

2
1 2

VIN 1M_0603_1% VIN

VL 1 PR54 2
34K_0603_1% PQ12
1

1
D 2N7002_SOT23
PR57 VS PR58 PR59 2

2
84.5K_0603_1% 10K_0603_0.1% 1 2 ACIN G PR60
10K_0603_0.1% ACIN <20,32,38> PR32 S 2 1 PACIN

3
66.5K_0603_1% 47K_0603_1%
Precharge detector
2

2
8

PR61
1 2 5 15.97V/14.84V FOR
P

1
22K_0603_5% + PACIN
O 7 PACIN <37>

1
6 - ADAPTOR
1

G
20K_0603_1%

PU5B PQ13
1

1
PR62

PC53 LM393M_SO8 DTC115EUA_SC70

4

1000P_0603_50V8J PC54 PZD2 PR63

0.1U_0603_25V7K 10K_0603_0.1% 100K
RLZ4.3B_LL34 2
2

+5VALWP
2

100K
4 4

3
PR64
2 1 RTCVREF
10K_0603_0.1%
Dell-Compal Confidential
Compal Electronics, Inc.
Title
Detector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 36 of 44
A B C D E
 A B C D E

Iadp=0~4.10A(90W) Charger
PQ85
Iadp=0~3.20A(70W) SI4835DY_SO8
B+++
Iair=0~2.25A(Air) 1 8
P3 B+
P2 2 7
PQ14 PQ15 3 6
SI4825DY_SO8 PL8 5
SI4825DY_SO8 FBM-L18-453215-900LMA90T_1812
VIN 8 PR65 1
S 1 1 8 2 1 2

4
D S D

0.1U_0805_25V7K
7 D S 2 2 S D 7

1
10U_1210_25V6M

10U_1210_25V6M

2200P_0603_50V7K
PC56
6 0.012_2512_1%
D S 3 3 S D 6

1
200K_0402_5%

PC55

PC57
5 PQ16
D G 4 4 G D 5

PR66 1

PC58
1 SI4835DY_SO8 1

2
1 8

2
2 7
3 6
5

3
2
1
PQ17

4
1

1
SI4835DY_SO8 PR67
PR68 PR69 4 1 2
PD11 150K_0402_5% PU6 0_0603_5% 47K_0603_1% VIN

2
ACOFF# 1 2 MB3887
1 24 PR70

2
1SS355_SOD323 -INC2 +INC2 10K_0603_0.1%
<32,39> ADP_I
2 1 2 23

5
6
7
8

1
1 D PR71 OUTC2 GND PC59
1 PR72 2 2 PQ19 100K_0603_1% 2200P_0603_50V7K ACOFF#
<36> PACIN
22K_0402_5% G 2N7002_SOT23 3 22 CS 1 2
+INE2 CS

51.1K_0603_1%

0.01U_0402_16V7K
S
3

1
PC60

1
21K_0603_1%

PR74

PC61
@16.9K_0603_1%
ACON 4 21 1 2 PQ18
<36> ACON -INE2 VCC(o)

1
30.9K_0603_1%
2 DTC115EUA_SC70

1 PR73

PR75
PC62 PR76 0.1U_0805_25V7K

2
100K
PR393

1 2 1 2 5 FB2 OUT 20 2 ACOFF <32>

10K_0603_0.1%

2
VREF_MB3887 4700P_0603_50V7K PC63

2
VREF_MB3887 6 19 1 2 LXCHRG 100K
1

VREF VH

0.1U_0603_25V7K

3
1

1
PC64

@30.1K_0603_1%
PC65 PR79 0.1U_0603_25V7K PC66

PR80
1 2 1 2 7 FB1 VCC 18 1 2
PQ109 1K_0603_5%

2
2N7002_SOT23 <32> IREF2 2200P_0603_50V7K 0.1U_0805_25V7K ACON PR82 BATT+
1

2 PR390 D BATT+ 2
8 17 1 PR81 2 1 PL9 2 1 2

2
-INE1 RT 47K_0603_1% 0.02_2512_1%
1 2 2
0_0402_5% G 15U_SPC-1204P-150_4A_20%
@0.01U_0402_16V7K

4.7U_1210_25V5K

4.7U_1210_25V5K
3,39> 90W/130W# S 1 2 9 16 1
3

+INE1 -INE3
1

2
<32> IREF

47U_25V_M
PR83 PD13

1
PC309

PC68

PC70

PC71
21K_0603_1% PC69 EA60QC04 +
1

20K_0603_1% 2 PR84 1 10 15 1 PR85 2 1 2

2

OUTC1 FB3
1
PR86

10K_0603_0.1% 330K_0603_5%

2
PC72 1500P_0603_50V7K 2
0.01U_0402_16V7K
IREF=0.82*Icharge 11 14
2

3
OUTD CTL PC73
2

1
IREF=0~3.3V 12 13
1 2
PR87
-INC1 +INC1 10P_0603_50V8J @10K_0603_5%

+3VALWP

2
CS
1

PR231
1

47K_0603_1%
PQ63
DTC115EUA_SC70
2

100K
2 PR164
2 1 2 PR89 1
104K_0603_0.1% 312K_0603_0.1%
1

100K
PQ64 PR36
3

DTC115EUA_SC70 BATT++
S

3 1 2 1
PC74
3 100K 3
2 PQ40 2.2M_0805_5% 1 2
<32> FSTCHG 2N7002_SOT23
G

Charge voltage
2

22P_0603_50V8J
1

100K
PR90
4S CC-CV MODE : 16.8V
3

845K_0603_1%
VS
2 PR37 1
100K_0603_1% +5VP
VCHG is H
4S PULSE MODE : 17.4V
1
2

PQ41 VCHG is L
0.01U_0603_50V7K

DTC115EKA_SOT23
2

PC154
100K
1

1
PC119

0.1U_0603_25V7K 2
PR91 VCHG <33>
1

300K_0603_0.5%
2

100K
2

3
8

3
P

+
1 0
<32> BATT-OVP 2
-
G

LM358A_SO8
PU7A
4

143K_0603_0.5%

PU7B
1

LM358A_SO8 6
-
1

PR92 7 0
1

1
PR93

@2.2K_0603_5% PC76 5
PC75 0.01U_0603_50V7K +
@0.1U_0603_25V7K
2

2
2

4 4

OVP voltage :
Dell-Compal Confidential
LI-4S :18.0V----BATT-OVP=2.00V
Compal Electronics, Inc.
Title
LI-3S :13.5V----BATT-OVP=1.50V Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
BATT-OVP=0.2206*BATT++ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Abacus-MT LA-1682 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 37 of 44
A B C D E
 A B C D E

+3.3V/+5V/+12V
PC77
1 2

1
4.7U_1210_25V5K

2
PD14
PC78 EC11FS2_SOD106
PL10 PC79 470P_0805_100V7K

1
FBM-L11-322513-151LMAT_1210 1 2 BST31 BST51
B++++

2
3

2
B+ 2 1 SNB 2 1 FLYBACK
0.1U_0805_25V7K PD15 PR94

2
DAP202U_SOT323 22_1206_5%

4.7U_1210_25V5K
1 1

8
7
6
5
2200P_0603_50V7K
0.1U_0805_25V7K

4.7U_1210_25V5K
VL PT1
PQ21 9U_SDT-1204P-9R0-120_4.5A_20%

D
D
D
D

1
1

1
PC80

PC81

PC82

PC83
SI4800DY_SO8 VS PC84
1 2

3
0.1U_0603_25V7K
2

G
S
S
S

4.7U_1206_10V7K
PR95 0.1U_0805_25V7K B++++

1
10_1206_5%
DH31 1 2

1
2
3
4

2
PR97

PC85

PC86
0_0402_5% PR96
0_0402_5% +12VALWP

5
6
7
8
2200P_0603_50V7K

0.1U_0805_25V7K

4.7U_1210_25V5K

4.7U_1210_25V5K
2

1
LX3 PQ22

D
D
D
D
2

1
10U_SPC-1204P-100_4.5A_20%

PC87

PC88

PC89

PC90
SI4800DY_SO8

8
7
6
5

2
PQ23 PR98
+3.3V Ipeak = 6.66A ~ 10A

D
D
D
D

2
1

G
S
S
S
4.7U_1210_25V5K

0.1U_0805_25V7K
SI4810DY_SO8 0_0402_5%

1
47P_0402_50V8J

PC93
PC91

4
3
2
1
1

PC92
0.1U_0805_25V7K

1
G
S
S
S
PC94

2
DH3
1

DL3
2

1
2
3
4
PL11

1 2 DH51

5
6
7
8
PR99
0_0402_5% PQ24

D
D
D
D

1
SI4810DY_SO8

22

21
2

PU8 PC96
25 4 47P_0402_50V8J

V+

VL

2
BST3 12OUT
2

G
S
S
S
1M_0402_5%

VDD 5
PR100

27 18 DL5 CSH5

4
3
2
1
DH3 BST5
1

DH5 16
PR101 26 17
LX3 LX5

1
+3VALWP 0.012_2512_1% 24 19
1

DL3 DL5

1
2 PR102 2
20
MAX1632_SSOP28 PGND 14 2M_0402_5% PR103
2

CSH3 CSH5 0.012_2512_1%

1 CSH3 CSL5 13
2 12

2
CSL3 FB5
3 15

2
FB3 SEQ
150U_D_6.3VM

3.57K_0603_1%

1 1 <20,32,36> ACIN 1 2 10 SKIP# REF 9 2.5VREF

1

PR104 23 6
SHDN# SYNC
1

1
100P_0402_50V8K
PC99

PR105

PC102

PC98 + + 10K_0402_1% 11
RST#

1
150U_D_6.3VM PD16 PR106 7
EP10QY03 @300K_0402_5% TIME/ON5 PC103 CSL5 +5VALWP
2

2 2 4.7U_1206_10V7K
28

GND
2

2
RUN/ON3

2
+3VALWP 1

1
PR108 1

1
PC104 1 2 1 2 PR109 + PC106
VL
2

+5VP
10K_0402_1%

1000P_0402_50V7K 0_0402_5% 10.2K_0402_1% PC108 PD17 + PC105 150U_D_6.3VM

2
2

1
PR111

PR107 100P_0402_50V8K EP10QY03 150U_D_6.3VM

2
1
PR110 PC109 @0_0402_5% 2

2
1

@0_0603_5% @1000P_0402_50V7K PR112 2

2

PR113 @100K_0402_1%
1

10K_0402_1%
0_0402_5%
1

PR114
TP6

1
PD18
2

SHDN_1632# <6,36> VL POK PC110

1 2
PR115 @100P_0402_50V8K

2
@RB751V_SOD323 @0_0603_5%
1

1
VL

2
VL PC111 PR177
@0.047U_0603_16V7K 20K_0603_1%
2

PR118 PR178
+5V Ipeak = 6.66A ~ 10A
TP7

2
1

1 2 1 2
3 PR117 47K_0603_1% PR116 200K_0603_1% 3

1
1.96K_0603_1% 47K_0402_1% D
VS 2
1

G SHDN_1632 <34>
2

PC158 S PQ42
3
8

PR119 PU9B 0.47U_0603_16V7K 2N7002_SOT23

2

1 2 5
P

19.1K_0603_1% +
7
6 -
O SHDN# <34> +12V MAX=0.5A,PEAK=1A,OCP=1.2A
G

PQ86
1

LM393M_SO8
4

PC112 SI3455DV-T1_TSOP6
0.047U_0603_16V7K PL27 +12V_FANP
2
10K_TH11-3H103FT_0603

1U_0805_25V4Z

D
6 SPC-06704-220
1

S
PC114

4 5 1 2
1

1
2
1

PH1

PR120 VL PQ108 1

EC10QS04
PC113 2 1

G
2

PD37
1000P_0603_50V8J 100K_0603_1% PL28 SI2303DS_SOT23
2

3
1

470P_0603_50V7K
B+ FBM-L11-322513-151LMAT_1210 1

PC244
PR121 1 2 3 1
200K_0402_5%

357K_0603_1%
0.01U_0603_50V7K

PR310
100K_0603_1% + PC245
1

15U_D2_25VM_R90

2
1
PC308
1U_0805_25V4Z
2

2
2
PC307

PR388
1

100P_0603_50V8G

100P_0603_50V8G
22U_1812_25V3M
PC247
2

59K_0603_1%

PU21
2

1
PC246

PC301
1 8
2

ISENSE VIN
1

PR311

2 GND PGATE 7
PR389 3 6 PR312
2

2
150K_0402_5% NC PWR GND 41.2K_0603_1%
4 FB ADJ 5
CPU thermal protection at 90 degree C
2

2
4 4
LM3485MM_MSOP8
2

Recovery at 45 degree C
1

D
2 PQ107
<17,29,32,35,40> SUSP#
G Dell-Compal Confidential
2N7002_SOT23
S
3

Compal Electronics, Inc.

Title
+3.3V/+5V/+12V/+12V_FANP
Add a switch for THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
12V_FAN on 2/11 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 38 of 44
A B C D E
 A B C D E

PL29
FBM-L11-322513-151LMAT_1210
B+ 2 1

2200P_0603_50V7K

10U_1210_25V6M

10U_1210_25V6M
0.1U_0603_25V7K

1
+5VALWP

PC251
PR313

1
PC248

PC250
10_0603_5% PR376

PC249
10_0603_5%

5
6
7
8
2

0.1U_0603_25V7K
PQ87

D
D
D
D
SI4800DY_SO8

2 2

1U_0805_25V4Z
1
PC253

G
S
S
S
PC252
1 1
+1.5V MAX=3.5A,PEAK=4.5A,OCP=5.5A

4
3
2
1
PD38

1
PU22 EC10QS04
PR314

VIN
140K_0603_1% 11 2 1
VCC PL30
2 1 4 ILIM +1.5VALWP
PC254 4.7U_SPC-1205P-4R7A_+40-20%
0.1U_0603_25V7K 1 2
BOOT 15 1 2

PR315
Adaptor Current Detector(90W)

5
6
7
8

1
0.1U_0805_25V7K

1.2K_0603_5%
PC255

PR316

@150U_D_6.3VM
+5VALWP 0_0603_5%

1
PR322

150U_D_6.3VM
PQ88
14 2 1 1 1 ADP_I : 1.207V.... clock throttle(Iin=5.03A)

D
D
D
D
HDRV

PC258

PC256
1U_0805_25V4Z
1 2 16 FPWM SI4810DY_SO8

PC257
+ +
ADP_I : 1.145V....No clock throttle(Iin=4.77A)

2
@100K_0603_1%

2
1

G
S
S
S
10

1
LDRV 2 2

4
3
2
1
PR318

10K_0603_0.1% 13
2

SW
Adaptor Current Detector(130W)

1
0_0603_5%

1.8K_0603_1%
PR319

PR320
3 PR321
EN 1.5K_0603_5%
12 2 1
ADP_I : 1.673V.... clock throttle(Iin=6.97A)
ISNS
1

PR317
2 1 7 SS ADP_I : 1.61V....No clock throttle(Iin=6.71A)

2
PC259
0_0603_5% 1000P_0603_50V8J 9
PGND
2

2 2
2 PGOOD
VSEN 6
TP5
AGND

VOUT 5

FAN5234QSCX_QSOP16
8

VL
PR303 PR304
1 2 2 1
47K_0402_1% 2M_0402_5%
VS

1
H_PROCHOT# PC236
<6> H_PROCHOT# 0.01U_0603_50V7K

2
8
PU9A

1
1 PR134 2 PQ83 D LM393M_SO8 3 1 2

P
2N7002_SOT23 + ADP_I <32,37>
2 1 O
PD21 200_0603_5% G 2 VREF_MB3887 PR306
-

G
0.022U_0402_16V7K
S 25.5K_0402_1%
RLS4148

3
VS1

0.01U_0603_50V7K
PD22

4
1

1
PC238

PC239
VIN 2 1 1 PR135 2 RLS4148
2 1

1
200_0603_5%

2
PD23 VS PR305
RLS4148 312K_0603_0.1%

1.5K_1206_5%
3 3
1

PR138 1

1
PR391
1.5K_1206_5%

BATT+ 2 1 PR136

2
PR137

1.5K_1206_5% 1 2
PR33

1
1.5K_1206_5% 267K_0603_1% D PR392
PR307 2 2 1
2

2
PR139 PZD3 154K_0603_1% G 90W/130W# <33,37>
2 1 2 1 3 1 1 PR140 2 +5VP PQ110 S 0_0402_5%

3
200_0603_5% PQ31 10K_0603_0.1%

2
RLZ4.3B_LL34 TP0610T_SOT23 B+ 2N7002_SOT23
2
1

1
150K_0603_5%

0.1U_0603_25V7K

PR141
PJP2 PJP5
1

1
PR142

PC128

PZD4
100K_0603_1% PC126 PC127 RLZ5.1B 4MM 3MM
0.22U_1206_25V7K 0.1U_0805_25V7K 1 2 1 2
2

+2.5VP +2.5V +3VALWP +3VALW

2

PJP6
PJP3
2MM
3MM
<34> EC_ON# 1 PR143 2 +12VALWP 1 2
22K_0603_5% +1.5VALWP 1 2 +12VALW
+1.5VALW

PJP1 PJP4 PJP8

2MM 3MM 3MM
PU10 1 2 1 2 1 2 +1.25VS
RTCVREF +12V_FANP +12V_FAN +5VALWP +5VALW +1.25VP
S-81233SGUP-T1_SOT89
4 4

2 3 PR144 PR34
CPU Fan Only
CHGRTCP 2 3 CHGRTC
1 2 1 2
200_0603_5% 200_0603_5%
Dell-Compal Confidential
1
1

1
1
1

PZD5
PC130
PC129
4.7U_1206_25VFZ
Compal Electronics, Inc.
2

RLZ16B_LL34 1U_0805_25V4Z Title

2

+1.5VS
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 39 of 44
A B C D E
 5 4 3 2 1

D D
PL21
HCB4532K-800T90_1812

1 2 B+

2
2200P_0603_50V7K

0.1U_0805_25V7K

4.7U_1210_25V5K

4.7U_1210_25V5K
1

1
PC196

PC197

PC198

PC199
PR278
PC200 51_1206_5%
4.7U_1210_25V5K +5VALWP

2
+2.5V/+1.25V

2
PR299

1
2.2_0603_5%

1
PD34 PC201
+2.5V Ipeak =8.49A ~ 14.78A

1
DAP202U_SOT323 PC202 2.2U_0805_10V6K

2
8
7
6
5
0.1U_0805_25V7K
PQ79 +2.5VP

D
D
D
D

2
SI4800DY_SO8

3
G
S
S
S

14

28
DDR Termination Voltage

1
2
3
4
PC203 PC204

1
2 1 12 17 2 1 PC224

VIN

VCC
SOFT1 SOFT2 PC205
PL22 0.01U_0603_50V7K 0.01U_0603_50V7K PC207 0.1U_0603_25V7K 10U_1206_6.3V7K

2
C +2.5VP 4.7U_SPC-1205P-4R7A_+40-20% PC206 PR279 0.1U_0805_25V7K C
1 2 2 1 1 2 6 BOOT1 BOOT2 23 1 PR280 2 2 1
0_0603_5% 0_0603_5%
8
7
6
5
0.1U_0805_25V7K PQ81
1

1 PQ80 PR283 FDS6984S

D
D
D
D
1

1 PR281 SI4810DY_SO8 1 PR282 2 5 24 1 2 4 5

PC209 + PC208 @100_0603_5% 0_0603_5% UGATE1 PU20 UGATE2 0_0603_5% +1.25VP
220U_4V_M + 220U_4V_M PD35 4 25 3 6 PL23
PHASE1 PHASE2
G
S
S
S

@EC31QS04 1.5U_TPR6D38-1R5M_4A_20%
1 2

2
ISL6225CA 2 7 1 2
2

1
2
3
4

4.7U_0805_10V4Z
PR284 PR285

1
PC210 1 2 7 22 1 2 1 8
@1000P_0603_50V8J 1K_0603_5% ISEN1 ISEN2 2K_0603_5% PR286 1
2
1

2
0.01U_0603_50V7K

220U_D2_2.5VM

PC212
2 27 @100_0603_5%
LGATE1 LGATE2
1

@0_0603_5%
PC213

PR288

PC211
PR287 +
18.2K_0603_1%

12

1
2

PC214 2
3 26
2

PGND1 PGND2 @1000P_0603_50V8J

2
9 VOUT1 VOUT2 20
10 VSEN1 VSEN2 19
8 EN1 EN2 21
15 16 SDREF
PG1 PG2/REF

GND

DDR

1
11 OCSET1 OCSET2 18
1

PC215 PC216
1

PR289 4.7U_0805_10V4Z @1000P_0603_50V8J

ISL6225CA

13

2
1

10K_0603_0.1% PR290
0_0603_5% PC217 PR291
@1000P_0603_50V8J 51K_0603_1%
2

2
2

B +5VALWP B
2

+2.5VP

PR30
PR292 Currently, only VER. ISL6225CA 2 1 SUSP#
SUSP# <17,29,32,35,38>

1
<32,35> SYSON SYSON 2 1 can be used for PU20. 0_0402_5%
VER. ISL6225BCA is prohibited PR293
0_0603_5% 10K_0603_0.1%

2
+3VALWP

1
1
PR295
PC218 10K_0603_0.1%
1

470P_0603_50V7K

2
PR296

2
10K_0603_0.1%
2

+2.5VPGD

A A

Dell-Compal Confidential
COMPAL ELECTRONICS, INC
Title
DDR POWER 2.5V & 1.25V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B Abacus-MT LA-1682
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 40 of 44
5 4 3 2 1
 A B C D E F G H

CPU_B+
Battery Feed
Forward CPU_B+
PL31 B+

2
CPU_B+ 2 1
PR323 +5VS 1 1 FBM-L18-453215-900LMA90T_1812

1
+5VS

2200P_0402_50V7K
10U_1210_25V6M

10U_1210_25V6M

0.1U_0603_25V7K
PC260

PC261

PC262

PC263

PC264
@10U_1210_25V
80.6K_0402_1%
PC266 PR324 + PC265

6
2
1
7

6
2
1
7
IRF6604_DFET-7
Dell 1U_0603_10V6K 10K_0402_1% 220U_25V_M

2
2

PQ89
1 2 +5VS PU23 2 1
command

2
2
32 VCC RAMPS 7
1 2 PR326

@IRF6604_DFET-7
<6,8> CPU_VID4 PR325 0_0603_5% 1 39 2 PR3271 +3VS 10K_0402_1%
VID4 PGOOD

0.15U_0805_16V7K
1 2 2 10K_0402_1% PR330 3 3
<6,8> CPU_VID3 VID3

PQ90
PR328 0_0603_5% 3 0_0603_5%

1
VID2 VGATE <21,32>
<6,8> CPU_VID2 1 2 4 VID1 PWM1 25 1 2
1 ENLL <35> PR329 0_0603_5% 5 1
VID0

2
PC267
1U_0805_25V4Z
1 2 6 24 PU24
<6,8> CPU_VID1

4
5

4
5
VID12.5 ISEN1+

2
0.1U_0603_16V7K

PC268
PR331 0_0603_5% 23 6 2
ISEN1- VCC BOOT PR333
<6,8> CPU_VID0 1 2 34

1
ENLL
1
PC306

PR332 0_0603_5% 3 1 1 2 PL32

1
PWM UGATE 0_0603_5% 0.7U_ETQP2H0R7BFA_30A_20%
<6,8> CPU_VID5 1 2 33 DRSEN PWM2 26 +CPU_CORE
ENLL PR334 0_0603_5% 7 8 1 2 +CPU_CORE
2

EN PHASE

0.01U_0603_25V7K
1 2 ISEN2+ 27

6
2
1
7

6
2
1
7

1
IRF6603_DFET-7
PR335 0_0603_5% +5VS
1 2 35 28 4 5
DSEN# ISEN2- GND LGATE

1
PQ91
<21> PM_DPRSLPVR PR379 @0_0402_5%

2
499K _0402_1%

@EC31QS04
1 2 ISL6207CB-T_SO8

61.9K_0603_1%
PD39

PR343
PR336 @0_0402_5% 20 PD40
PWM3

PR339
+5VS 1 2 10 EC31QS04

2
<16,21> PM_STPCPU# PR338 @0_0402_5% OCSET
21 3 3

2
ISEN3+

1
1 2 22

1
ISEN3-
2

0.056U_0603_16V7K
@0_0402_5% PR380

PR337 0_0603_5%

1
11

2
SOFT

PC269
73.2K_0603_1% 31 2 1 PQ92

4
5

4
5
PWM4
1
0.01U_0603_50V7K

PRESCOTT_OCP 1 2 PR340 IRF6603_DFET-7

PC270

PR395 PR377 30 0_0402_5%

1

VL PR342 @0_0402_5% ISEN4+

9 29
2

DSV ISEN4- +5VS 0.01U_0603_50V7K

2 1 2 1
PC271
1
PC300

26.1K_0603_1% 1 2
LM358A_SO8 Frequency Select 36 15
FS COMP
8

PU28A
2

3 2 PH2 1
P

+ +5VS
1 0 37 DRSV FB 13
1

2
@0_0402_5%
PR344 442_0402_1%

S THERM_820+-5%_0603
- 2
G

PR381 2
PR341

PR378
38 14 @0_0402_5% CPU_B+
4

VR-TT# NC
2

220P_0603_50V
1

6
2
1
7

2200P_0402_50V7K
10U_1210_25V6M

10U_1210_25V6M

0.1U_0603_25V7K
IRF6604_DFET-7
PC273

PC274

PC275

PC276

PC278

PC279
@10U_1210_25V

@10U_1210_25V
2 PR387 2
40 16
25.5K_0402_1% 2

1
NTC VDIFF

6
2
1
7
PQ93

PC277
17
1

0_0402_5% VSEN
1

@IRF6604_DFET-7
12 18
2

2
GND VRTN
1

0.15U_0805_16V7K
100P_0402_50V7K PH6 PR346
1

PC302 2 1 19 8 0_0603_5%
GND OFS +5VS

PQ94
330K_0402_5% 1 2 3
2

ISL6247_MLFP40 3
2

2
PC280
+3VS PR347 PU25
10K_0402_1% 6 2
VCC BOOT
1U_0805_25V4Z

2 PR3481 PR349 PL33

4
5
<32> VR_TT# PR350 0_0402_5% 3 1 1 2

4
5
PWM UGATE
1
PC281

1 2 2 PR3511 0_0603_5% 0.7U_ETQP2H0R7BFA_30A_20% +CPU_CORE

<6> VSSSENSE
2

0_0402_5% @0_0603_5% 7 8 2 1 +CPU_CORE

EN PHASE
1.2M_0603_5%

442K_0603_1%
2

PR354 1

6
2
1
7

6
2
1
7
499K _0402_1%

IRF6603_DFET-7
+CPU_CORE 2 PR352 1 4 GND LGATE 5
PR353

PQ95
1U_0805_25V4Z
0_0402_5%

61.9K_0603_1%
PC283

PR364
PU28B +5VS ISL6207CB-T_SO8

@EC31QS04
LM358A_SO8 6 2 PR3551 PR357
- <6> VCCSENSE
1

PD41
7 @0_0603_5% 5.1K_0603_1% PC282
1 2

0
0.1U_0603_16V7K

+ 5 Remote 1 2 3 3
2

@22P_0402_25V8K
Sensing
2

1
TP0610T_SOT23
1
PC284

PR358 PR359 2

2
10K_0603_0.1% 27K_0603_1% PQ97
1

PR356
PQ96 PC285
2

4
5

4
5
32.4K_0603_1%

PQ68 PC286 0.01U_0603_50V7K

1

2
2

D 2N7002_SOT23 IRF6603_DFET-7
1000P_0402_50V7K 1 2
2
2

PR362

PR361 2
PR363 45.3K_0603_1% G
2

90.9K_0603_1% S
3

PR360 2 PH3 1
1

1 1

20K _0402_1%
1

D S THERM_820+-5%_0603
3 PRESCOTT_OCP 3
2
1

PQ98 G CPU B+
1

47K_0603_5% 2N7002_SOT23 S
3
1

6
2
1
7

6
2
1
7

1
2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
10U_1210_25V6M

10U_1210_25V6M

0.1U_0603_25V7K
PC289

PC290

PC291

PC292

PC293

PC303

PC304

PC305
@10U_1210_25V
PR394 PC287

IRF6604_DFET-7
PQ99
2 2 1 @ 1000P_0603_50V
2

MMBT3904_SOT23

2
0.15U_0805_16V7K

@IRF6604_DFET-7
PR366
3

PQ111 <5> PR367

1

PQ100
PR365

PC294
@ 0_0603_5%
2.37K_0603_1%

BOOTSELECT 47K_0603_5% 1 2 3 3
1

+5VS
MMBT3904_SOT23

1 22
2

2
S
PR382

PU26 0_0603_5%
PQ101

G
PR368 2 6 2 PR369
3

100K_0402_1% PR370 VCC BOOT 0_0603_5% PL34 Dell EMI Request

4
5

4
5
16.2K_0603_1%
D 3 1 1 2 0.7U_ETQP2H0R7BFA_30A_20%
1

PQ102 PWM UGATE

2 1 +CPU_CORE
1

+CPU_CORE
@1U_0805_25V4Z

2N7002_SOT23 7 8 2 1
EN PHASE
2
499K _0402_1% PC299

6
2
1
7

6
2
1
7

1
IRF6603_DFET-7
4 GND LGATE 5

2
PQ103

@EC31QS04

PR373
61.9K_0603_1%
1

PD42
Panasonic ERTJ0EV334J (0402) @ ISL6207CB-T_SO8
Locate this NTC resistor on NTC Linearization
2
1U_0805_25V4Z

Network for load-line

2
2
PC295

PR371

PCB between phase 2 and 3 3 3

1
for thermal compensation. compensation
1

PR372 PQ104 PC296

4
5

4
5
0_0402_5% IRF6603_DFET-7 0.01U_0603_50V7K
1 2
1

+3VALWP 1 2
PC297 PU27 +1.2VP
4.7U_0805_10V4Z PH5
2

4 S THERM_820+-5%_0603 4
1 VIN OUT 5
2 1
4
<35> VID_PWRGD PG
Dell-Compal Confidential
1

3 EN GND 2
PC298
2 PR374 1 4.7U_0805_10V4Z
2

0_0603_5% MIC5258_SOT23-5
COMPAL ELECTRONICS, INC
2

<32,35> VR_ON PR375 Title

100K_0402_1%
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B Abacus-MT LA-1682 0.1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 25, 2003 Sheet 41 of 44
A B C D E F G H
 5 4 3 2 1
2

Power Version change list (P.I.R. List)

CKT
Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

D 1 +CPU_CORE voltage error CPU ID net error 0.1A P41 Swap net CPU_VID0 and CPU_VID4 , CPU_VID1 and CPU_VID3(rework) 0.1 SST D

add a switch for 12V_FAN with

2 FAN turns on when system off with battery only need to add a switch to control 12V_FAN power 0.1A P 38 PR388 200K 5% 0402 PR389 150K 5% 0402
when system off with battery only PC307 1uF/25V 0805 P C308 0.01uF/50V 0603 0 .2 PT
PQ107 2N7002 PQ108 SI2303DS

doulbe pulses on the output of U81.4 when the for H-VID_PWRGD transtion timing with VID_PWRGD meet Intel
3 0.1A P 41 change PU27 CM2843 to PU27 MIC5258 0 .2 PT
input U81.3 slowly rises to 1.58v SPEC.

Change PQ89, PQ90, PQ91, PQ92, PQ93, PQ94, PQ95, PQ96,

4 MOSFET SMT damage to provide MOSFET damage 0.1A P 41
PQ99, PQ100, PQ103, PQ104 symbol footprint
0 .2 PT
Issue found in ISL6225BCA 0.1A P 40 change PU20 from ISL6225BCA to ISL6225CA
5 Oscillation behavior found in ISL6225BCA

Load line is not suit Intel SPEC. Change load line 0.1A P 41 Change PR354 from 340K to 442K and PR382 from 1.91K to 2.49K
C
6 0 .2 PT C

Detect adapter 130W/90W 0.1A P 37 Add PQ109,PR390,PC309,PR393

7 Adapter is 90W/130W
0 .2 PT
8 Change capacitor meterial Capacitor material is not available 0.1A P 38 Change PC245 from100U to 15U

0 .2 PT
9 Adapter is 90W/130W Detect adapter 130W/90W 0.1A P 39 Add PR391,PQ110,PR392,and change PR305 from 0 to 115K

De-pop PC282,change PR382 to 2.37K, PR361 to

10 Load line test Base on Dell power team load line test 0.1A P 41 0 .2 PT
45.3K,PR341 to 442 Ohm,PR344 to
25.5K,PR343,PR364,PR373 to 61.9K

11 +RTCCLK and S3# will a pulse when AC plug in delay +3VALW output 0.1A P 38 Change PC104 to 1000P
0 .2 PT

12 +RTCCLK and S3# will a pulse when AC plug in delay +1.5VALW output rise time 0.1A P 39 Change PC259 to 1000P; PD38 EC10QS04 for cost down

B B

13 12V FAN OCP point Change 12V FAN OCP point,and modofy circuit 0.1A P 38 Change PR311 to 59K,PC244 to 470P, PC245 to 15uF/25V 0 .2 PT

14 Issue found in ISL6225BCA With fix PWM condition 0.1A P 40 Change PR290 to 0 and De-pop PR288
0 .2 PT
Not easy to adjust OCP setting only, due to separate OCP setting point from the DSV setting point; Particularly, Use the PU28A for DSV setting only; use PR342 26.1K for
15 use the BootSelect signal to control different OCP setting points for 0.1A P 41
DVS and OCSET both within same network NW CPU ocp setting; for prescott-MT CPU ocp setting, add
divider NW CPU and Prescott-MT CPU PR395 73.2K, PQ111 MMBT3904, PR394 47K, and change 0 .2 PT
PR367 to 47K. Dep PR378 requested from Dell

0 .2 PT

0 .2 PT

A A

Dell-Compal Confidential
COMPAL ELECTRONICS, INC
Title
Power PIR
Size Document Number Rev
Abacus-MT LA-1682 0.2
Date: Tuesday, February 25, 2003 Sheet 42 of 44
5 4 3 2 1
 5 4 3 2 1

H/W Version change list (P.I.R. List)

CKT
Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

D 1 System cann't turn on B+ is shutdown when AC in,Because the timing sequence of +12VALW is 0.1A P7 Change U76 VCC net from +12VALW to +12V_FAN(rework) 0 .1 SST D

later than +12V_FAN

2 H_VID_PWRGD delay time from VID_PWRGD VID_PWRGD with H_VID_PWRGD Sequence need to meet the Intel 0.1A P 35 Change R567 on BOM SD028100200 10K_0402 _5% to SD028200200 0 .2 PT
is not enough specification (H_VID_PWRGD delay 1~10ms from VID_PWRGD) 2 0K_0402_5% and add C32 0.1U_0402_16V4Z
Change K/B connector JP32 from SP01J00133L S H-CONN JAE
FK2S030W11 30P to SP01F005110 S H-CONN FO XCONN
3 Abacus and Abacus-MT K/B is different Change K/B connector to Abacus compatible 0.1A P 33 0 .2 PT
GS22250-0001 25P P1 and delete the net KSO17 and C805
Change net pin 164/166/168/170 of JP8 from INVPWR_B+ to B+ and
LA-1682 MB INVPWR_B+ cann't used the We will use the LS-1452 to BDW11/12 project, will reduce some 0.1A P 17 Q71, C79 3, C795, R560, R562, Q74 add "1@" 0 .2 PT
4 L S-1452 VGA BD parts for External Graphic.

Change Board ID to 0.5V ,So replace and pop the R393 with
5 Board ID change Board ID change for EC code, due to the KB change 0.1A P 32 SD028910200 S RES 1/16W 91K +-5% 0402 0 .2 PT

6 KB back to Abacus JP5 pin1 signal KSO17 change to KSO16 0.1A P 34 JP5 pin1 signal KSO17 change to KSO16 0 .2 PT

Add R17 1@33_0402_5% (SD028330A00 S RES 1/16W 33 +-5%

0402) And C33 1@10P _0402_25V8K (SE068100K00 S CER CAP 10P
7 Prevent EMI impact Prevent CLK_AGP_66M antenna impact when no used 0.1A P 17 0 .2 PT
25V +-10% N PO 0402)
Change the BOM U8 from SA093461030 without LAN
C C

8 Lan EEPROM Material control U8 will used the eeprom same as Abacus 0.1A P 24 code to SA093461040 with Abacus LAN code 0 .2 PT

9 Extra connector Jp33 just for A-test BIOS debug connector 0.1A P 33 Remove Jp33 on BOM 0 .2 PT

10 RTCCLK ringback Need to add series termination on RTCCLK at the ICH 0.1A P 21 Add R18 SD0282 20A00 S RES 1/16W 22 +-5% 0402 and C62 0 .2 PT
because of signal quality/undershoot and ringback at Q69 SE068101K00 S CER CAP 100P 2 5V +-10% NPO 0402
Change the BOM U77 fro m SA243500000 S IC RG82G4350M A1
11 Part Number error Correct U77 A2 revision Part Number 0.1A P 21 UFCBGA-732 MONTARA-GT to SA828520100 S IC RG82852GME 0 .2 PT
A2 UFCBGA-732 MONTAR A-GT. SST

12
Reversed the capacitor about RTCCLK circuit Just do the reserved the RTCCLK modify waveform cap. 0.1A P 21 Depop the C62 (add @ ) 0 .2 PT

13 Remove capacitor @C659 & @C660 extra component from PCB because
Extra Pads about @C659 & @C660 we have not used. 0.1A P7 Depop the parts C659 & C660 from Circuit & PCB 0 .2 PT

H_VID_PWRGD waveform have nagative pulse

14 after rise up at VID_PWRGD voltage at H_VID_PWRGD waveform abnormal 0.1A P 35 Change R567 on BOM from SD02 8200200 20K_0402_5% to
B
SD028470200 10K_0402_5% and pop C32 0.1U_0402_16V4Z 0 .2 PT B

1.58V(riseing)

Default the ITPCLK/ITPCLK# to Intel Add @ to RP61 and add SD014499A09 49.9 +-1% 0603
15 circuit specification. For meet Intel specification 0.1A P6 R572/R573 for ITPCLK/ITPCLK# pull down 0 .2 PT

Audio cost reduction from Dell request Cost reduction 0.1A P 29 Depop the parts C481, C554, C551
16 P 30 0 .2 PT
C553, C483, C6 22, C623, C624 change from 1uF to 0.1uF

17 Improve audio performance Improve audio performance 0.1A P 29 Populate C490 1uF 0 .2 PT

18 Investigate Beep circuit cost down Cost 0.1A P 30 Add R132 0 ohm, but depop. Test at PT step 0 .2 PT

19 Fix HP plug in phonejack delay time Plug in External SPK will delay some timing 0.1A P 30 C588 change from 4.7uF_0805 to 0.47uF_0603, and depop C580 0 .2 PT

20 Reversed the capacitor about Fan circuit C687 & C701 make the voltage leakage so depop the parts . 0.1A P7 Depop the parts C687,C701 (add @ ) 0 .2 PT

A A
21 1394 can not link at 400 speed. Improve 1394 link test by TI test tool 0.1A P 25 Depop C223, C216, R198, R197, R196, R194, R199 0 .2 PT
add C822(270P), C823(1uF), R574(5.1K), R575~R578(56.2) Dell-Compal Confidential
COMPAL ELECTRONICS, INC
Title
H/W PIR
Size Document Number Rev
Abacus-MT LA-1682 0.2
Date: Tuesday, February 25, 2003 Sheet 43 of 44
5 4 3 2 1
 5 4 3 2 1

H/W Version change list (P.I.R. List)

CKT
Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase

D 22 Audio cost reduction from Dell request cost 0.1A P 29 pop R342 0ohm, depop X4, C485. 0 .2 PT D

C542 change to 0ohm

23 Add adapter 90W/130W# select function pin. Detect adapter 130W/90W 0.1A P 33 U27 Pin 12 add net 90W/130W# 0 .2 PT

Add R579 (0ohm_0603) for +12V Fan, and R580(0ohm_0603) for +5V
Fan, also add JP34 for +5V Fan connector. But depop R580 and JP34.
24 Add +5V Fan for CPU thermal Fan thermal module same with Abacus 0.1A P7 0 .2 PT
And R471 must change to 66.5K_1% if use +5VS Fan source.

25 update :Add +5V Fan for CPU thermal Fan thermal module same with Abacus 0.1A P7 R579 R580 prevent current issue, R579 change to jumper 0 .2 PT
and R580 change to 0805_bead(L53:3A rating, depop)

26 improves Vcore copper plane decreasing the size of isolated ground islands 0.1A P7 remove C664 and C665 0 .2 PT

27 Vcore test report recommend Vcore test report recommend 0.1A P7 depop C645, C648, C65 0, C651, C662, C647, C653: 470uF of 0 .2 PT
CPU bulk capacitors

C C

B B

A A

Dell-Compal Confidential
COMPAL ELECTRONICS, INC
Title
H/W PIR
Size Document Number Rev
Abacus-MT LA-1682 0.2
Date: Tuesday, February 25, 2003 Sheet 44 of 44
5 4 3 2 1