intel’ 27128A 128K (16K x 8) PRODUCTION AND UV ERASABLE PROMs m Fast 150 nsec Access Time i inteligent Identifier™ Mode —HMOS* II-E Technology — Automated Programming Operations = Low Power m+ 10% Voc Tolerance Available — 100 mA Maximum Active oma Maximum Standby ™ Available in 28-Pin Cerdip Package (S00 Packaging Spec, Order #231969) ‘The intel 27128A is a SV only, 131,072-bit ultraviolet erasable and electrically programmable read-only memo- ty (EPROM). The 271284 is fabricated with Intel's HMOS* IE technology which significantly reduces die size land greatly improves the device's performance, reliability and manufacturabilty ‘The 27128A is currently available in the CERDIP package providing flexibility in prototyping and R&D environ- ments where reprogrammability is required. ‘The 27128Ais available in fast access times including 150 ns (27128A-1). This ensures compatibility with high- performance microprocessors, such as Intel's 8 MHz 80186 allowing full speed operation without the addition of WAIT states, The 27128A is also directly compatible with the 12 MHz 8051 family. “HMOS is a patented process of Intel Corporation. 7 DATA OUTPUTS es oad GND o——> ——___. Ver o——> [OUTPUT ENABLE] CHIP ENABLE, ‘AND Pon lpaie ‘OUTPUT BUFFERS RonAay ADDRESS, INPUTS 131,072.81 CELL MATRIX Figure 1. Block Diagram ctober 1990 5-28 ‘Order Number: 230849-00827128A Pin Names AocAia | ADDRESSES. [ee [CaP ENABLE ‘OE —[ourpur enasie O50;_[ourruts GM | PROGRAM No__ [ ROINTERNAL CONNECT} mss | ze | Fes | nen | ane 271208 arve| aren rece | 2728 | 2512 tro roe as | ww | ve vec | var | veo te | ke | oe vou |e] ke | Ly | vee] veo | Ne | a | a3 ml elated elm |e | om | es, e lets ls SL Rp AL S| as mp RL xp aL vel a | ay | ay fe spate fs ts OF | tte | OF | OE | tine alata lala Bo |e” | Ae | Ae | ae ml | fm Pe e|e|2/)2| 2 sl a|al| als o} o |e | “er | & | & | & | |e a| a fo] oa | o &] oe fof fa ajalala]a & |e | oo |e | oc org | gon) | to | oto | ato | cto | ovo alealeéleals ‘0849-2 NOTE: ino “Universal Sto"—Compatible EPROM Pin Configurations are Shown inthe Blocks Adjacent othe 27128A Pins Figure 2. Cerdip(D) DIP Pin Configuration 5-29intel EXTENDED TEMPERATURE (EXPRESS) EPROMS The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS Type | Operating Temperature | Burn-in 125°C (hr) Q Cte +70°C 168 28 T 40°Cto +850 None it =A0Gto +85"C 168 +8 READ OPERATION 271280 available with 168 +8 hour, 125°C dynamic burn-in using Intel's standard bias configuration. This pro- cess exceeds or meets most industry specifications ‘of burn-in, The standard EXPRESS EPROM operat ing temperature range is 0°C to 70°C. Extended op- ‘erating temperature range (—40°C to +85°C) EX- PRESS products are available. Like all_intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AGL. This may allow the user to reduce or eliminate incoming inspection testing EXPRESS OPTIONS 27128A Versions Packaging Options: ‘Speed Versions Cerdip. 20 TLQ DC CHARACTERISTICS Electrical Parameters of Express EPROM Products ate identical to standard EPROM parameters except for: Symbol Parameter oo Test Conditions min Max 18 Voc Standby Ourent (mA) 50 CE = Vin, OF = Vip aa Vor Active Curent (mA) 125 OE = C= Va Voo Active Current 100 OF = CE = Vu. Ver = Veo _ at High Temperature (mA) 5G NoTE: 1. The maximum current value is with Outputs Oo to O7 unloaded. 2 271284 0849-10 Voc = +54 GE = GND Re tke Vss = GNO s 0849-11 Binary Sequence tom Ay to Arg Burn-in Bias and Timing Diagrams 5-30intel 271280 ABSOLUTE MAXIMUM RATINGS* Operating Temperature During NOTICE: This is a production data sheet. The speci ‘ations are subject to change without notice. WARNING: Stressing the devico beyond the “Absolute Read. 7 OC to + 70°C ‘Maximum Ratings" may cause permanent damage. ees ioc vero | MMe, Rates’ may cause permanent dag, peau ee es tet ay emma oe rete rar esa tended expose beyond the “Opering Condon ee Oey Sear a Respect to Ground 0.6V to +13.5V Vpp Supply Voltage with Respect to ‘Ground During Programming ....-0.6Vto +14V Voc Supply Voltage with Respect to Ground 0.6V to +7.0V READ OPERATION DC CHARACTERISTICS o°c < T, < +70°C i ee ee ee a reat a TEE lo | Output Leakage Current 10 ~T Vour= 0V to Vac. top: | VepCurentRead | 2 5 | Voe=5.5V ‘se Voc Current Standby 40 CE=Vin loot Voc Current Active 2 100 mA | CE=OE=Vi_ ee a Went Wonton Sst esta Ye Loma vane ta ain AC CHARACTERISTICS orc < Ta < +70°C oe et ee Ta arian | aries Syma | erene wae es taco Address to Output Delay | 150 200 250 ns. toe CE to Output Delay 150, 200 250 ns a atcamaoasy = = ee = SE RAR = epee (oeacne foe 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vep. 2. Vpp may be connected directly to Veo except during program yring. The supply current would then be the sum of loc and ley. The maximum currant valua is with Outputs Op fo Or unloaded, 3. Typical values are for Ta = 25°C and nominal supply voltages. 44 Thss parameter is only Sampled and is not 100% tested. Output Float is defined as the point where data is no longer riven—s00 liming diagram, 5.31intel 27128A CAPACITANCE(2) T, = 25°C, f = 1MHz ‘Symbol Parameter Typ) | Max | Unit | Conditions Gy | teputCapacitance | 4 | 6 | pF Cour | OutputGapacitance | 8 | 12 | pF | Vour= Ov ‘AC TESTING INPUT/OUTPUT WAVEFORM ‘AC TESTING LOAD CIRCUIT sv swore = fis ua | 2st rots <= 2 out anny sons ey on [AG testing inputs ae driven at 24V fora Logi "t” and 0.45 for a Loge "0" Timng measurements are made at 20V for @ ogi and 0 8V fra Loge. noes so084o-4 Gf nctudes sip Capacitance AC WAVEFORMS poness ADDRESSES or 230849-5 Notes: 4. Typical values are for Ta=25°C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tasted, 3, OE may be dolayad up to toe—toe after the falling edge of CE without impact on tce: 5:32intel 271280, DEVICE OPERATION ‘The modes of operation of the 27128A are listed in Table 1. A single 5V power supply is required in the read ‘mode. All inputs are TTL levels except for Vpp and 12V on Ag for intgligent Identifier, Table 1. Modes Selection Mode Notes | GE | OE | PGM | As | Ao | Vp | Voc | Outputs Read 1PM [vn [ve [x [x [vec [s.0v [Dour Output Disable Vi | Va | Vw | xX | x | Voc | Sov | Highz ‘Standby Vin |x x x | xX | Voc | 50V | HighZ Programming 4 [va [vm [ve [x [x | vee [6ov [Dy Program Verity 4 ve vu | a [x [x [Vee | 60v [Dour Program Inhibit 4 [vm [x [x |x [x | ver | 6ov | Highz intgligent | Manufacturer |_23 | Vu | Vu | Vm | Vw | Vu _| Vcc | 50v | 89H Identifier Device 23 Min] Vie Vin Va | Vin | Voc | 5.0V. 89H NOTES: 4. X can be Vit oF Vig 2Vy~ 120 2050 3. Ar~Ag, Aro~Ara = Vit 4. Soe Tablo 2 for Voc and Vpp voltages. Read Mode The 27128A has two contro! functions, both of which must be logically active in order to obtain data at the ‘outputs. Chip Enable (CE) is the power contro! and should be used for device selection. Output Enable (E) is the output contro! and should be used to gate data from the output pins, independent of de- Vice selection. Assuming that addresses are stable, the address access time (tac) is equal to the delay from CE to output (toe). Data is available at the out- puts after a delay of tog from the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc-toe: Standby Mode EPROMs can be placed in standby mode which re- duces the maximum current of the device by apply- ing a TTL-high signal to the CE input. When in stand- by mode, the outputs are in a high impedance state, independent of the OE input. Two Line Output Control Because EPROMs are usually used in larger memo- 'y arrays, Intel has provided 2 control lines which ‘accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not ocour 5-33 To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while OE should be made a com- mon connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are active only when data is desired trom a particular memory device. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- Quire careful decoupling of the devices. The supply current, Igo, has three segments that are of interest to the system designer—the standby current level, the active current level, and the transient current peaks that are produced by the falling and rising ‘edges of Chip Enable. The magnitude of these tran- sient current peaks is dependent on the output ca- acitive and inductive loading of the device. The as- Sociated transient voltage peaks can be suppressed by complying with Intel's Two-Line Control, and by properly selected decoupling capacitors. It is recom- mended that a 0.1 uF ceramic capacitor be used on every device between Voc and GND. This should be fa high frequency capacitor for low inherent induc: tance and should be placed as close to the device as possible. In addition, a 4.7 uF bulk electrolytic ‘capacitor should be used between Voc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to ‘overcome the voltage droop caused by the inductive effect of PC board-traces.intel 271280 PROGRAMMING MODES Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all bits of the EPROM are in the “1” state. Data is introduced by selectively programming “0s” into the desired bit lo- ‘Although only “Os” will be programmed, and “0s” can be present in the data word. ‘The only way to change a “0” toa "1" is by ultravio- let light erasure. is in the programming mode when Vp is rais rogramming voltage (See Table 2) and CE and PGM are both at TTL low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Program inhibit Programming of multiple EPROMS in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input inhibits the other devices trom being programmed. Except for TE, all ike inputs (including OE) of the Parallel EPROMs may be common. A TTL low-level pulse applied to the PGM input with Vpp at its pro- gramming voltage and CE at TTL-Low will program the selected device. Program Verity ‘A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verify is performed with OE at Vi., CE at Vi_, PGM at Vi and Vpp and Voc at their pro- gramming voltages. inteligent Identifier Mode The intgligent Identifier Mode allows the reading out of a binary code from an EPROM that wil identity its manufacturer and type. This mode is intended for use by programming equipment for the putpose 5:34 of automatically matching the device to be pro- grammed with its corresponding programming aigo- fithm, This mode is functional in the 25°C +5°C am- bient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line Ag of the, EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line Ag from Vi, to Vip. All other address lines must be held at Vi. during the intgligent Identifier Mode. Byte 0 (Ap = Vi) represents the manufacturer code and byte 1 (Ap — Viy) the device identifier code. ‘These two identifier bytes are given in Table 1 ERASURE CHARACTERISTICS The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-40004 range. Data shows that constant expo- sure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the device is to be ex- posed to these types of lighting conditions for ex- tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (.e., UV intensity * exposure time) for erasure should be a minimum of 15 Wsec/em?. The erasure time with this dosage is approximately 15 to 20 minutes using an uitraviolet lamp with a 12000 uW/cm? power rat- ing, The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/em2 (1 week @ 12000 »W/ ‘om2). Exposure of the device to high intensity UV light for longer periods may cause permanent dam- age.271280 0840-6 Figure 3. Inteligent Programming Flowchart inteligent Programming™ Algorithm The inteligent Programming™ Algorithm, a standard in the industry for the past few years, is required for the 27128A. A flow-chart of the intgligent Program- ming Algorithm is shown in Figure 3. ‘The intgligent Programming Algorithm utilizes two: different pulse types: initial and overprogram. The duration of the initial pulse(s) is one millisecond, which will hen be followed by a larger overprogram pulse of length 3X msec. X is an iteration counter and is equal to the number ofthe initial one milisec- cond pulses applied to a particular location, before a correct verity occurs. Up to 25 one-milisecond puls- 8 per byte are provided for before the overprogram pulse is applied. The entire sequence of program pulses and byte verifications 1s performed at Voc = 6.0V and Vpp = 12.5V. When the inteligent Programming cy- cle has been completed, all bytes should be com- pared to the original data with Vog = Vpp = 5.0V. 5:35intel 271280 DC PROGRAMMING CHARACTERISTICS T, = 25°C +5°C *AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) ......20.ns Input Pulse Levels . 0.45V 10 2.4V Input Timing Reference Level 0.8V and 2.0V Output Timing Reference Level ......0.8V and 2.0V . Limits Conditions symbol Parameter Min Max Unit (Note 1) Input Current (All Inputs) 10 HA _| Vin = Vie or Vin Input Low Level (All Inputs) =0.4 08 Vv Input High Level 20_| Voott | _V ‘Output Low Voltage During Verity 0.45 Vv | lo = 2.1mA Vou Output High Voltage During Verify 24 v oH = —400 nA lca | Voc Supply Current (Program & Verify) 100. mA Ippo Vpp Supply Current (Program) 50 mA CE = Vin Vio Ag intgligent Identifier Vollage us | 5 | Vv Ver intgligent Programming Algorithm v0 | 130 | v | Ce=PGM=v Veo. intgligent Programming Algorithm 5.75 6.25 Vv AC PROGRAMMING CHARACTERISTICS ‘Ta = 25°C +5°C (See Table 2 for Voc and Vpp voltages.) Limits Conditions* ‘Symbol | Parameter i TP sj nna (Note 1) tas Address Setup Time 2 BS toes OE Setup Time 2 1s a tos Data Setup Time 2 HS ta ‘Address Hold Time 0 Es ton Data Hold Time 2 Bs tOFP ‘GE High to Output Float Delay 0 130 ns (Note 3) ‘wes Vep Setup Time 2 #S ‘tyes: ‘Voc Setup Time 2 HS ‘oes TE Setup Time 2 as tpw PGM Initial Program Pulse Width | 0.95 | 1.0 1,05 ms: topw GM Overprogram Pulse Width 2.85 78.75 ms_| (Note 2) toe Data Valid from OF 150_[_ns -_ Notes: 1. Voc must be applied simultaneously or before Vpp and removed simultaneously of after Vp. 2, The tength of the overprogram pulse may vary from 2.85 maoc to 78.75 msec as a function of the iteration ‘counter value X. 3. This parameter is only sampled and is not 100% tested. ‘Output Fioat is defined as the point whore data is no long: ‘er deiven—s0e timing diagram. 4. The maximum current value is with outputs Op-O7 un- loaded 5:36intel 271288 PROGRAMMING WAVEFORMS cese-7 NoTes: 1. The Input Timing Reterence Level is 0.8V for Vi, and 2V for a Vi. 2. tog and torp are characteristics of the device but must be accommodated by the programmer. 3, When programming the 27128A, @ 0.1 pF capacitor is required across Vpp and ground to suppress spurious voltage ‘tansionis which can damage the device. REVISION HISTORY ‘Number Description 009 Removed Plastic Package 5:37