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VHDL of The Moore Machine With A Synchronous Reset and MEALY SEQ DETECTOR

The document describes a Moore machine and a Mealy machine implemented in VHDL. It includes: 1) A 4 state Moore machine with 1 input, 1 output, and 5 transitions represented by a bubble diagram. 2) The VHDL code for the Moore machine with 1 process and 4 states. 3) A 4 state Mealy machine that detects the input sequence "1011" without resetting to the initial state after recognition. 4) The VHDL code for the Mealy machine with a single process and output associated with state transitions.

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1K views5 pages

VHDL of The Moore Machine With A Synchronous Reset and MEALY SEQ DETECTOR

The document describes a Moore machine and a Mealy machine implemented in VHDL. It includes: 1) A 4 state Moore machine with 1 input, 1 output, and 5 transitions represented by a bubble diagram. 2) The VHDL code for the Moore machine with 1 process and 4 states. 3) A 4 state Mealy machine that detects the input sequence "1011" without resetting to the initial state after recognition. 4) The VHDL code for the Mealy machine with a single process and output associated with state transitions.

Uploaded by

dhr893
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Following is an example of the Moore Machine with Asynchronous Reset, "RESET".

• 4 states: s1, s2, s3, s4


• 5 transitions
• 1 input: "x1"
• 1 output: "outp"

This model is represented by the following bubble diagram:

Related Constraints

Related constraints are:

• FSM_extract
• FSM_encoding
• FSM_fftype
• ENUM_encoding

FSM with 1 Process

Please note, in this example output signal "outp" is a register.

VHDL

Following is the VHDL code for an FSM with a single process.

library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port ( clk, reset, x1 : IN std_logic;
outp : OUT std_logic);
end entity;
architecture beh1 of fsm is
type state_type is (s1,s2,s3,s4);
signal state: state_type ;
begin
process (clk,reset)
begin
if (reset ='1') then
state <=s1; outp<='1';
elsif (clk='1' and clk'event) then
case state is
when s1 => if x1='1' then state <= s2;
else state <= s3;
end if;
outp <= '1';
when s2 => state <= s4; outp <= '1';
when s3 => state <= s4; outp <= '0';
when s4 => state <= s1; outp <= '0';
end case;
end if;
end process;
end beh1;

mealy machine seq detector

Example of a Mealy Machine

The sequence following detector recognizes the input bit sequence X: "1011". The
machine will keep checking for the proper bit sequence and does not reset to the initial
state after it recognizes the string. In case we are implementing a Mealy machine, the
output is associated with the transitions as indicated on the following state diagram
(Figure 6).

Figure 6: Sequence detector (1011), realized as a Mealy Machine.

The VHDL file is given below.


VHDL file for a sequence detector (1011) implemented as a Mealy Machine
library ieee;

use ieee.std_logic_1164.all;

entity myvhdl is

port (CLK, RST, X: in STD_LOGIC;

Z: out STD_LOGIC);

end;

architecture myvhdl_arch of myvhdl is

-- SYMBOLIC ENCODED state machine: Sreg0

type Sreg0_type is (S1, S2, S3, S4);

signal Sreg0: Sreg0_type;

begin

--concurrent signal assignments

Sreg0_machine: process (CLK)

begin

if CLK'event and CLK = '1' then

if RST='1' then

Sreg0 <= S1;

else

case Sreg0 is

when S1 =>

if X='0' then

Sreg0 <= S1;


elsif X='1' then

Sreg0 <= S2;

end if;

when S2 =>

if X='1' then

Sreg0 <= S2;

elsif X='0' then

Sreg0 <= S3;

end if;

when S3 =>

if X='1' then

Sreg0 <= S4;

elsif X='0' then

Sreg0 <= S1;

end if;

when S4 =>

if X='0' then

Sreg0 <= S3;

elsif X='1' then

Sreg0 <= S2;

end if;

when others =>


null;

end case;

end if;

end if;

end process;

-- signal assignment statements for combinatorial outputs

Z_assignment:

Z <= '0' when (Sreg0 = S1 and X='0') else

'0' when (Sreg0 = S1 and X='1') else

'0' when (Sreg0 = S2 and X='1') else

'0' when (Sreg0 = S2 and X='0') else

'0' when (Sreg0 = S3 and X='1') else

'0' when (Sreg0 = S3 and X='0') else

'0' when (Sreg0 = S4 and X='0') else

'1' when (Sreg0 = S4 and X='1') else

'1';

end myvhdl_arch;

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