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Deber Digitales Nombre: Jossuet Farfan A. Codigo VHDL

The document contains code for several VHDL modules: 1. A sum module that adds two 4-bit inputs and outputs a 5-bit sum. 2. A variaspuertas module that implements various logic gates like AND, OR using other modules. 3. An ejemplo module that implements an AND gate followed by an OR gate. 4. A PUERTAS module that implements an XOR gate using a NOT, OR and XOR logic.

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Jossuet Gallagher
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39 views

Deber Digitales Nombre: Jossuet Farfan A. Codigo VHDL

The document contains code for several VHDL modules: 1. A sum module that adds two 4-bit inputs and outputs a 5-bit sum. 2. A variaspuertas module that implements various logic gates like AND, OR using other modules. 3. An ejemplo module that implements an AND gate followed by an OR gate. 4. A PUERTAS module that implements an XOR gate using a NOT, OR and XOR logic.

Uploaded by

Jossuet Gallagher
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Deber Digitales

Nombre: Jossuet Farfan A.

Codigo VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.all;

ENTITY sum IS
PORT (a : IN std_logic_vector(3 DOWNTO 0);
b : IN std_logic_vector(3 DOWNTO 0);
salida : OUT std_logic_vector(4 DOWNTO 0));
END sum;

ARCHITECTURE synth OF sum IS


BEGIN

PROCESS (a, b) IS
BEGIN
salida <= a + b;
END PROCESS;
END synth;
;
-- Programa principal

library ieee;

library milibreria;

use ieee.std_logic_1164.all;

use milibreria.puertas.all;

entity variaspuertas is port(

r,s,t,p: in std_logic;

y: out std_logic);

end variaspuertas;

architecture archvariaspuertas of variaspuertas is

signal x,w,z: std_logic;

signal dum1:std_logic_vector(1 downto 0);

signal dum2: std_logic_vector(2 downto 0);

begin

u1: and_de_3 port map(r,s,t,x);

dum1<=r & p;

u2: or_de_n port map(a=>dum1,y=>z);

dum2<=r&s&p;

u3: or_de_n generic map(3) port map (dum2,w);

y<=x or z or w;

end;port (a, b, d : in bit;

e : out bit);

end ejemplo;

architecture rtl of ejemplo is

signal c: bit;
begin

AND2 : process g

begin

c<= a and b;

wait on a, b;

end process;

OR2 : process (c,d)

begin

e<= c or d;

end process;

end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.all;

ENTITY sum IS
PORT (a : IN std_logic_vector(3 DOWNTO 0);
b : IN std_logic_vector(3 DOWNTO 0);
salida : OUT std_logic_vector(4 DOWNTO 0));
END sum;

architecture DOS of PUERTAS is

signal AUX : std_logic;

begin

AUX <= not(A or B);


Z <= AUX xor C;

end DOS;

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