MOSFET Overview

Paul Hasler
 A MOSFET Transistor

Source Drain

Gate
Drain

Source Gate

Substrate
MOS Capacitor Picture
 MOS-Capacitor Regions

Surface potential
moving from
depletion
to inversion

(Ψ - Vs)/UT (κ(Vg - VT) - Vs)/UT

Qs = e Qs = ln( 1 + e )

Depletion (κ(Vg - VT) - Vs < 0) Inversion (κ(Vg - VT) - Vs > 0)

(κ(Vg - VT) - Vs)/UT

Qs = e Qs = (κ(Vg - VT) - Vs)/UT
MOSFET Channel Picture

= (
I I0 e
κVg −VS / UT

−e
κVg −Vd / UT
)
 Subthreshold MOSFET Curves
-6 -7
10 10

-8
-7
10 10

Drain current (A)

Drain current (A)

-9
-8
10
10
-10
10
-9
10
-11
10
UT = 25.84mV
κ = 0.58680
-10
10 -12
10
Io = 1.2104fA 0.6 0.65 0.7 0.75 0.8
Source voltage (V)
0.85 0.9
-11
10
0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
Gate voltage (V)

Drain current (nA)

Drain voltage (V)

Above-Threshold MOSFET
Moving from subthreshold to above-threshold

Conduction band bends due to

electrostatic force of the electrons
moving through the channel.

Significant at channel current > Ith

∝Qs
I = (K/2κ) ( (κ(Vg - VT) - Vs)2
- (κ(Vg - VT ) - Vd) 2 )
∝Qd

Saturation: Qd = 0
I = (K/2κ) ( (κ(Vg - VT) - Vs)2
∝Qs
 Drain Current - Gate/Source Voltage
0.02 4
0.018
3.5
0.016
K/κ = 74.585 µA/V2

sqrt(Drain current (µA))

sqrt(Drain current (A))

3
0.014 (κ = 0.7)
0.012 2.5

0.01 2
0.008
1.5
0.006 VT = 0.806
1
0.004 κ (Vg - VT) = 0.595
0.002
K κ = 37.861 µA/V2 0.5

0 0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Gate voltage (V) Gate voltage (V)
 MOSFET Equations

I = (K/2κ) ( (κ(Vg - VT) - Vs)2 - (κ( Vg - VT) - Vd) 2 )

Above-Threshold:
Saturation: (Qd = 0) I = (K/2) (κ(Vg - VT) - Vs)2
Vd > κ(Vg - VT )

κVg-Vs/UT -Vds/UT
I = Is e (1 – e )
Subthreshold:
Saturation: (Vds> 4 UT) I = Is e κVg-Vs/UT
 Velocity Saturation

Si Crystal Velocity Limit

Ideal Drift (Ohm’s Law)

Square-law
region

L = 76 nm MOSFET
VT
Origin of Drain Dependencies
Increasing Vd effects
the drain-to-channel
region:
• increases barrier
height
• increases depletion
width
Current versus Drain Voltage
Why is this not flat?

Id = Id(sat) (1 + (Vd/Vo) )
Vd/Vo
Id = Id(sat) e
 DC-Removed Modeling
Needed for nonlinear analysis; do not want to carry biasing details through the analysis

Formulating the Approach Solving for Transistor Gain

Vd Assume bias conditions, some Vdd
set, some set by the circuit: input/output relationship?
Vg
Vg0, Vd0, Vs0
Ibias - Transitor in saturation
Vs Resulting in a bias current = Ibias
Vout
We expand
Vg = Vg0 + ΔVg, Vd = Vd0 + ΔVd, Vin

Vs = Vs0 + ΔVs GND

For for MOSFET in saturation, we get Ibias = Ibiasexp(κΔVin/ UT) exp(ΔVout/VA)

I = I0 exp( (κ Vg - Vs)/ UT) exp(Vd/ VA) Gain = ΔVout / ΔVin = - κVA / UT

= Ibias exp( (κ ΔVg - ΔVs)/ UT) exp(ΔVd/ VA)

Ibias = Io exp( (κ Vg0 - Vs0)/ UT) exp(Vd0/ VA)

 Key parameters of EKV model

K’ Kp

κ γ
γ = 1 / (2κ 䌥㻕φf)
2φf

VT0 VT0 (not voltage dependant)

VA DL
λ
and some short-channel parameters