D D D D D D: A78L00 Series Positive-Voltage Regulators
D D D D D D: A78L00 Series Positive-Voltage Regulators
POSITIVE-VOLTAGE REGULATORS
SLVS010I – JANUARY 1976 – REVISED JULY 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL OUTLINE PLASTIC CYLINDRICAL SOT-89 CHIP
VO(NOM) (D) (LP) (PK)
TJ FORM
(V)
OUTPUT VOLTAGE TOLERANCE (Y)
5% 10% 5% 10% 5% 10%
2.6 µA78L02ACD – µA78L02ACLP µA78L02CLP µA78L02ACPK µA78L02CPK µA78L02Y
5 µA78L05ACD µA78L05CD µA78L05ACLP µA78L05CLP µA78L05ACPK µA78L05CPK µA78L05Y
6.2 µA78L06ACD µA78L06CD µA78L06ACLP µA78L06CLP µA78L06ACPK µA78L06CPK µA78L06Y
0°C to 8 µA78L08ACD µA78L08CD µA78L08ACLP µA78L08CLP µA78L08ACPK µA78L08CPK µA78L08Y
125°C 9 µA78L09ACD µA78L09CD µA78L09ACLP µA78L09CLP µA78L09ACPK µA78L09CPK µA78L09Y
10 µA78L10ACD – µA78L10ACLP µA78L10CLP µA78L10ACPK µA78L10CPK µA78L10Y
12 µA78L12ACD µA78L12CD µA78L12ACLP µA78L12CLP µA78L12ACPK µA78L12CPK µA78L12Y
15 µA78L15ACD µA78L15CD µA78L15ACLP µA78L15CLP µA78L15ACPK µA78L15CPK µA78L15Y
D and LP packages are available taped and reeled. Add the suffix R to the device type (e.g., µA78L05ACDR). The PK package is only available
taped and reeled (e.g., µA78L02ACPKR). Chip forms are tested at TA = 25°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
schematic
INPUT
20 kΩ
OUTPUT
1 kΩ to 14 kΩ
1.4 kΩ
COMMON
NOTE: Resistor values shown are nominal.
absolute maximum ratings over operating temperature range (unless otherwise noted)†
µA78Lxx UNIT
µA78L02AC, µA78L05C–µA78L09C, µA78L10AC 30
Input voltage
voltage, VI V
µA78L12C, µA78L12AC, µA78L15C, µA78L15AC 35
D package 97
Package thermal impedance, θJA (see Notes 1 and 2) LP package 156 °C
PK package 52
Virtual junction temperature range, TJ 0 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
Storage temperature range, Tstg –65 to 150 °C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. Due to
variations in individual device electrical characteristics and thermal resistance, the built-in thermal-overload protection may be
activated at power levels slightly above or below the rated dissipation.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
Input voltage
g VI = 10.5 V to 23 V 42 200 42 175
25°C mV
regulation VI = 11 V to 23 V 36 150 36 125
Ripple rejection VI = 13 V to 23 V, f = 120 Hz 25°C 36 46 37 46 dB
Output voltage
g IO = 1 mA to 100 mA 18 80 18 80
25°C mV
regulation IO = 1 mA to 40 mA 10 40 10 40
Output
f = 10 Hz to 100 kHz 25°C 54 54 µV
noise voltage
Dropout voltage 25°C 1.7 1.7 V
25°C 4 6 4 6
Bias current mA
125°C 5.5 5.5
Bias VI = 5 V to 20 V 1.5 1.5
0°C to 125°C mA
current change IO = 1 mA to 40 mA 0.2 0.1
† Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a 0.33-µF capacitor across the input and a 0.1-µF capacitor across the output.
Ripple
VI = 18.5 V to 28.5 V, f = 120 Hz 25°C 33 39 34 39 dB
rejection
Output IO = 1 mA to 100 mA 25 150 25 150
voltage 25°C mV
regulation IO = 1 mA to 40 mA 15 75 15 75
Output
f = 10 Hz to 100 kHz 25°C 82 82 µV
noise voltage
Dropout
25°C 1.7 1.7 V
voltage
25°C 4.6 6.5 4.6 6.5
Bias current mA
125°C 6 6
Bias VI = 10 V to 30 V 1.5 1.5
0°C to 125°C mA
current change IO = 1 mA to 40 mA 0.2 0.1
† Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a 0.33-µF capacitor across the input and a 0.1-µF capacitor across the output.
APPLICATION INFORMATION
VI µA78Lxx VO
0.33 µF 0.1 µF
IN OUT
+ µA78Lxx G
VI IL
COM
– –VO
R1
IO
0.33 µF 0.1 µF
R2
Input µA78Lxx
R1
0.33 µF VO(Reg)
Output
IO
IO = (VO/R1) + IO Bias Current
APPLICATION INFORMATION
1N4001
0.33 µF 0.1 µF
1N4001
–20-V Input µA79L15 VO = –15 V
1N4001
VI µA78Lxx VO
1N4001
or
Equivalent
– VO
reverse-bias protection
Occasionally, the input voltage to the regulator can collapse faster than the output voltage. This can occur, for
example, when the input supply is crowbarred during an output overvoltage condition. If the output voltage is
greater than approximately 7 V, the emitter-base junction of the series-pass element (internal or external) could
break down and be damaged. To prevent this, a diode shunt can be employed as shown in Figure 7.
VI µA78Lxx VO
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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