IV SEMESTER HDL Lab

1) VHDL code to realize all the logic gates

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BASIC_GATES is
port(a,b: in bit;
c,d,e,f,g,h: out bit);
end BASIC_GATES;

architecture Behavioral of BASIC_GATES is

begin
c<= not a;
d<= a and b;
e<= a or b;
f<= a nand b;
g<= a nor b;
h<= a xor b;

end Behavioral;

Verilog code
module basic_gates (a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
assign c= ~a;
assign d=a&b;
assign e=a|b;
assign f=~(a&b);
assign g=~(a|b);
assign h=a^b;
endmodule

Department of Electronics & Communication Engg. 1 Dr. TTIT, KGF

IV SEMESTER HDL Lab

2) VHDL code to implement HALF ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALF_ADDER is
port( a,b: in bit;
sum, carry: out bit);

end HALF_ADDER;

architecture Behavioral of HALF_ADDER is

begin
sum<= a xor b;
carry<= a and b;

end Behavioral;

Verilog code
module half_adder (a,b,sum,carry);
input a,b;
output sum, carry;
assign sum=a^b;
assign carry =a&b;
endmodule

Department of Electronics & Communication Engg. 2 Dr. TTIT, KGF

IV SEMESTER HDL Lab

3)VHDL code to implement Full Adder in Dataflow Method

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Full_adder is
port(a,b,c: in bit;
sum, carry: out bit);
end Full_adder;

architecture Behavioral of Full_adder is

begin
sum<= a xor b xor c;
carry<= ( a and b) or (b and c) or (c and a);
end Behavioral;

Verilog code

module full_adder (a,b,c,sum,carry);

input a,b,c;
output sum, carry;
assign sum=a^b^c;
assign carry = (a&b)|(b&c) | (c &a );
endmodule

Department of Electronics & Communication Engg. 3 Dr. TTIT, KGF

IV SEMESTER HDL Lab

4) VHDL code to implement FULL ADDER in BEHAVIOURAL METHOD.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_beh1 is
Port ( a,b,c : in std_logic;
sum,carry : out std_logic);
end full_beh1;
architecture Behavioral of full_beh1 is
begin
process(a,b,c)
begin
sum<= a xor b xor c;
carry<= (a and b) or (b and c) or (c and a);

end process;
end Behavioral;

Verilog code
module full_adder (a,b,c,sum,carry);
input a,b,c;
output sum, carry;
reg sum,carry;
always@ (a,b,c)
begin
sum=a^b^c;
carry = (a&b)|(b&c) | (c &a );
end
endmodule

Department of Electronics & Communication Engg. 4 Dr. TTIT, KGF

IV SEMESTER HDL Lab

5) VHDL code to implement FULL ADDER in STRUCTURAL METHOD.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_add_struct is
port( x,y,z: in bit;
sum, carry: out bit);
end full_add_struct;

architecture Behavioral of full_add_struct is

component HALF_ADDER
port( a,b:in bit;
sum, carry: out bit);
end component;

component BASIC_GATES
port( a,b: in bit;
e: out bit);
end component;
signal p,q,r: bit;

begin

U1: HALF_ADDER port map(x,y, p,q);

U2: HALF_ADDER port map(p,z, sum,r);
U3: BASIC_GATES port map(q,r,carry);
end Behavioral;

Verilog code
module full_struc_14(x,y,z,sum,carry);
input x,y,z;
output sum,carry;

HA (x,y,s0,c0);
HA(z,s0,sum,c1);
Or (carry,c0,c1);
endmodule

Module HA(x,y,s,c);
Input x,y;
Output s,c;

xor (s,x,y);
and (c,x,y,);
endmodule

Department of Electronics & Communication Engg. 5 Dr. TTIT, KGF

IV SEMESTER HDL Lab

6) VHDL code to implement 8 :1 MULTIPLEXER.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_8_1 is
Port ( I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
y : out std_logic);
end Mux_8_1;
architecture Behavioral of Mux_8_1 is
begin
with S select
Y<= I(0) when "000",
I(1) when "001",
I(2) when "010",
I(3) when "011",
I(4) when "100",
I(5) when "101",
I(6) when "110",
I(7) when "111",
'Z' when others;
end Behavioral;

Verilog code
module mux_8_1(s,i,y);
input [2:0]s;
input [7:0]i;
output y;
reg y;
always@ (i,s);
begin
case (s)
3’d 0 :y = i[0];
3’d 1 :y = i[1];
3’d 2 :y = i[2];
3’d 3 :y = i[3];
3’d 4 :y = i[4];
3’d 5 :y = i[5];
3’d 6 :y = i[6];
3’d 7 :y = i[7];
default:y= ”z”;
end case
end
endmodule

Department of Electronics & Communication Engg. 6 Dr. TTIT, KGF

IV SEMESTER HDL Lab

7) VHDL code to implement 2 TO 4 DECODER.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Decoder2to4 is
Port ( r : out std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0));
end Decoder2to4;

architecture Behavioral of Decoder2to4 is

begin
process(s)
begin
case s is
when "00"=> r<= "0001";
when "01"=> r<= "0010";
when "10"=> r<= "0100";
when "11"=> r<= "1000";
when others=> r<= "ZZZZ";
end case; end process;
end Behavioral;

Verilog code
module decoder (s,r);
input [1:0]s;
output [3:0]r;
reg [3:0]r;
always@ ( s)
begin
case (s)
2’b 00:r=4’d1;
2’b 01:r=4’d2;
2’b 10:r=4’d3;
2’b 11:r=4’d4;
default:r=”z”;
end case
end
endmodule

Department of Electronics & Communication Engg. 7 Dr. TTIT, KGF

IV SEMESTER HDL Lab

8) VHDL code to implement 1: 8 DEMULTIPLEXER.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Demux is
Port ( I : in std_logic;
sel : in std_logic_vector(2 downto 0);
Y : out std_logic_vector(7 downto 0));
end Demux;

architecture Behavioral of Demux is

begin

process(sel,I)
begin
if(sel="000") then Y(0) <= I;
else Y(0) <= 'Z';
end if;

if(sel="001") then Y(1) <= I;

else Y(1) <= 'Z';
end if;

if(sel="010") then Y(2) <= I;

else Y(2) <= 'Z'; end if;

if(sel="011") then Y(3) <= I;

else Y(3) <= 'Z'; end if;

if(sel="100") then Y(4) <= I;

else Y(4) <= 'Z'; end if;

if(sel="101") then Y(5) <= I;

else Y(5) <= 'Z'; end if;

if(sel="110") then Y(6) <= I;

else Y(6) <= 'Z'; end if;

if(sel="111") then Y(7) <= I;

else Y(7) <= 'Z'; end if;

end process;
end Behavioral;

Department of Electronics & Communication Engg. 8 Dr. TTIT, KGF

IV SEMESTER HDL Lab

Verilog code

module demux (i,sel,y);

input i;
input [2:0]sel;
output [7:0]y;
reg [7:0]y;
always@ (sel,i)
begin
if (sel==3’d0)
y[0]=i;
else
y[0]=”z”;
if (sel==3’d1)
y[1]=i;
else
y[1]=”z”;
if (sel==3’d2)
y[2]=i;
else
y[2]=”z”;
end
if (sel==3’d3)
y[3]=i;
else
y[3]=”z”;
if (sel==3’d4)
y[4]=i;
else
y[4]=”z”;
if (sel==3’d5)
Department of Electronics & Communication Engg. 9 Dr. TTIT, KGF
IV SEMESTER HDL Lab

y[5]=i;
else
y[5]=”z”;
if (sel==3’d6)
y[6]=i;
else
y[6]=”z”;
if (sel==3’d7)
y[7]=i;
else
y[7]=”z”;
end
endmodule

9) VHDL code to implement ENCODER WITHOUT PRIORITY.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Encoder_wihtoutpriority is
Port ( a : in std_logic_vector(0 to 7);
b : out std_logic_vector(2 downto 0));
end Encoder_wihtoutpriority;

architecture Behavioral of Encoder_wihtoutpriority is

begin
process(a)
begin
case a is
when "00000001" => b<= "111";
when "00000010" => b<= "110";
when "00000100" => b<= "101";
when "00001000" => b<= "100";
when "00010000" => b<= "011";
when "00100000" => b<= "010";
when "01000000" => b<= "001";
when "10000000" => b<= "000";
when others => b<= "ZZZ";
end case;
end process;
end Behavioral;

Department of Electronics & Communication Engg. 10 Dr. TTIT, KGF

IV SEMESTER HDL Lab

Verilog code

module enc_wop(a,b);
input [7:0]a;
output [2:0]b;
reg [2:0]b;
always@ (a);
begin
case (a)
8’b 00000001: b=3’d7;
8’b 00000010: b=3’d6;
8’b 00000100: b=3’d5;
8’b 00001000: b=3’d4;
8’b 00010000: b=3’d3;
8’b 00100000: b=3’d2;
8’b 01000000: b=3’d1;
8’b 10000000: b=3’d0;
default : b=”zzz”;
end case
end
end module

10) VHDL code to implement ENCODER WITH PRIORITY.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encodr_with is
Port ( a : in std_logic_vector(0 to 7);
b : out std_logic_vector(2 downto 0));
end encodr_with;

architecture Behavioral of encodr_with is

begin
process(a)
begin
case a is

Department of Electronics & Communication Engg. 11 Dr. TTIT, KGF

IV SEMESTER HDL Lab

when "XXXXXXX1" => b<= "111";

when "XXXXXX10" => b<= "110";
when "XXXXX100" => b<= "101";
when "XXXX1000" => b<= "100";
when "XXX10000" => b<= "011";
when "XX100000" => b<= "010";
when "X1000000" => b<= "001";
when "10000000" => b<= "000";
when others => b<= "ZZZ";
end case;
end process;
end Behavioral;

Verilog code

module encdr(a,b);
input [7:0]a;
output [2:0]b;
reg [2:0]b;
always@ (a);
begin
case (a)
8’b xxxxxxx1: b=3’d7;
8’b xxxxxx10: b=3’d6;
8’b xxxxx100: b=3’d5;
8’b xxxx1000: b=3’d4;
8’b xxx10000: b=3’d3;
8’b xx100000: b=3’d2;
8’b x1000000: b=3’d1;
8’b 10000000: b=3’d0;
default : b=”zzz”;
end case
end
endmodule

Department of Electronics & Communication Engg. 12 Dr. TTIT, KGF

IV SEMESTER HDL Lab

11)VHDL code to implement 4-Bit comparator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator is
Port ( a,b : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(2 downto 0);
agb,alb,aeb, anb : out std_logic);
end comparator;

architecture Behavioral of comparator is

begin
process(sel,a,b)
begin
case sel is
when "000" => if( a=b) then aeb<= '1'; else aeb<='0'; end if;
when "001" => if( a>b) then agb<= '1'; else agb<='0'; end if;
when "010" => if( a<b) then alb<= '1'; else alb<='0'; end if;
when "011" => if(a/=b) then anb <= '1'; else anb<='0'; end if;
when others => aeb<= 'Z'; agb<= 'Z'; alb<= 'Z'; anb<= 'Z';
end case;
end process;
end Behavioral;

Verilog code
module copm_2(x,y,z,a,b);
input [1:0] a,b;
Output x,y,z;
assign x = (~(a[1]^b[1])) & (~( a[0]^b[0]));
assign y=(a[1]& (~b[1])) |(a[1]&a[0]&(~b[0])) |
(a[0] & (~b[1]) & (~b[0]));
assign z=( v[1]& (~a[1])) | (b[1]&b[0]&(~a[0]))|
((~a[1]) &~a[0]) &b[0]);
endmodule
12)VHDL code to implement BINARY TO GRAY code conversion
Department of Electronics & Communication Engg. 13 Dr. TTIT, KGF
IV SEMESTER HDL Lab

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Bin_gray is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end Bin_gray;

architecture Behavioral of Bin_gray is

begin

g(3) <= b(3);

g(2) <= b(3) xor b(2);
g(1) <= b(2) xor b(1);
g(0) <= b(1) xor b(0);
end Behavioral;

Verilog code
module bin_gray(b,g);
input [3:0]b;
output [3:0]g;
reg [3:0]g;
always@ ( b)
begin
g[0]=b[0]^b[1];
g[1]=b[1]^b[2];
g[2]=b[2]^b[3];
g[3]=b[3];
end
endmodule
13) VHDL code to implement SR- FLIP-FLOP.

Department of Electronics & Communication Engg. 14 Dr. TTIT, KGF

IV SEMESTER HDL Lab

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRFF is
Port (reset, s : in bit;
r : in bit;
clk : in bit;
q : inout bit;
qn : out bit:='1');
end SRFF;
architecture Behavioral of SRFF is
begin
process(clk,reset)
begin
if(reset=’1’) then q<= ‘0’;
elsif(clk'event and clk='1')then
q <= s or((not r) and q);
end if;
end process;
qn<=not q;

end Behavioral;

Verilog code
module SR_FF(s,r,clk,q,qn);
input s,r,clk;
output q,qn;
reg q,qn;
always@ (posedge (clk))
begin
q=(s|((~r)&q));
qn=~q;
end
endmodule
14) VHDL code to implement D-FLIP FLOP.

Department of Electronics & Communication Engg. 15 Dr. TTIT, KGF

IV SEMESTER HDL Lab

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( clk,d,set,reset : in bit;
q : inout bit;
qn : out bit:='1');
end dff;

architecture Behavioral of dff is

begin
process( clk, set,reset)
begin
if ( reset='1') then q<='0';
elsif(set = '1')then q<='1';
elsif( clk'event and clk='1')then
q<= d;

end if;
qn<= not q;
end process;

end Behavioral;

Verilog code

module d_ff(clk, d,set,reset,q,qn);

input clk, d, set, reset;
output q,qn;
reg q,qn;
always@ (posedge (clk))
begin
if(reset==1)

Department of Electronics & Communication Engg. 16 Dr. TTIT, KGF

IV SEMESTER HDL Lab

q=0;
else if(set==1)
q=1;
else
q=d ;
qn= ~q ;
end
endmodule

15) VHDL code to implement T- FLIP FLOP.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tff is
Port ( clk,t,set,reset : in bit;
q : inout bit;
qn : out bit:='1');
end tff;

architecture Behavioral of tff is

begin
process( clk, set,reset)
begin
if ( reset='0') then q<='0';
elsif(set = '0')then q<='1';
elsif( clk'event and clk='1')then
q<= q xor t;
end if;
qn<= not q;
end process;
end Behavioral;

Verilog code

Department of Electronics & Communication Engg. 17 Dr. TTIT, KGF

IV SEMESTER HDL Lab

module t_ff(t,clk,set,reset,q,qn);
input t, clk, set, reset;
output q,qn;
reg q,qn;
always@ (posedge (clk))
begin
if(reset==0)
q=0;
else if(set==0)
q=1;
else
q=q^t ;
qn= ~q ;
end
endmodule

16) VHDL code to implement JK- Flip Flop.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jk is
Port ( clk,j,k : in bit;
set,reset : in bit;
q : inout bit;
qn : out bit:=’1’);
end jk;

architecture Behavioral of jk is

begin
process(clk,set, reset)
variable t: bit_vector (1 downto 0);
begin
if ( reset='0') then
q<='0';
elsif(set = '0')then
q<='1';
elsif( clk'event and clk='1')then
t :=j & k;
case t is
when "00" => q<=q;
when "01" => q<='0';

Department of Electronics & Communication Engg. 18 Dr. TTIT, KGF

IV SEMESTER HDL Lab

when "10" => q<='1';

when "11" => q<=not q;
end case;
end if;
end process;
qn<= not q;
end Behavioral;

Verilog code

module jkff (clk, j,k, s,r, q, qn);

input clk, s, r;
input [1:0]j,k;
output q,qn;
reg q,qn;
always@ (posedge (clk))
begin
if(r==0)
q=0;
else if(s==0)
q=1;
else
case (j,k)
2’d0: q=q;
2’d1: q=0;
2’d2: q=1;
default: q=~q;
end case
qn=~q;
end
endmodule

17) VHDL code to implement 32 - BIT ALU.

Department of Electronics & Communication Engg. 19 Dr. TTIT, KGF

IV SEMESTER HDL Lab

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( a,b : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(3 downto 0);
enable: in bit;
res1 : out std_logic_vector(31 downto 0));
end ALU;

architecture Behavioral of ALU is

begin
process(enable,opcode,a,b)
begin
if(enable = '1') then
case opcode is
when "0000" => res1<= a + b;
when "0001" => res1<= a - b;
when "0111" => res1<= a(15 downto 0) * b(15
downto 0);
when "0010" => res1<= not a;
when "0011" => res1<= a and b;
when "0100" => res1<= a or b;
when "0101" => res1<= a nand b;
when "0110" => res1<= a nor b;
when "1000" => res1<= a xor b;
when others => res1<=(others => 'X');
end case;
else
res1 <= (others => 'Z');
end if; end process;
end Behavioral;

Verilog code

Department of Electronics & Communication Engg. 20 Dr. TTIT, KGF

IV SEMESTER HDL Lab

module alu (a, b, opcode, enable, resi);

input [31:0]a,b;
input [3:0]opcode;
input enable;
output [31:0] resi;
reg[31:0]resi;
always@ (enable,opcode,a,b)
begin
if (enable= =’1’)
case (opcode)
4’b 0001: resi=a+b;
4’b 0010: resi=a-b;
4’b 0011: resi=a [15:0]*b [15:0];
4’b 0100: resi=~a;
4’b 0101: resi=a&b;
4’b 0110: resi=a|b;
4’b 0111: resi=~ (a|b);
default: resi=”x”;
end case
else
resi=’z’;
end
endmodule

18) VHDL code to implement BINARY ASYNCHRONOUS RESET COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binary_asyn is
Port ( clk,reset,load,p : in std_logic;
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end binary_asyn;

architecture Behavioral of binary_syn is

signal sclkdiv : std_logic_vector(15 downto 0);
signal sclk: std_logic;
begin

process(clk)
begin
if(rising_edge(clk))then

Department of Electronics & Communication Engg. 21 Dr. TTIT, KGF

IV SEMESTER HDL Lab

sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;

process(reset,sclk, load, p,t)

begin
if(reset = '1') then
q<= "0000";
elsif (sclk'event and sclk ='1') then
if( load = '1')then
q <=d;
else
if(p='1') then
q <= q + 1;
else
q<=q-1;

end if;
end if;
end if;
end process;
end Behavioral;

19) VHDL code to implement BINARY SYNCHRONOUS RESET COUNTER.

Department of Electronics & Communication Engg. 22 Dr. TTIT, KGF

IV SEMESTER HDL Lab

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Bin_synreset is
Port ( clk,reset,load,p,t : in std_logic;
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));

end Bin_synreset;

architecture Behavioral of Bin_synreset is

signal sclkdiv : std_logic_vector (15 downto 0);
signal sclk: std_logic;
begin

process(clk)
begin
if(rising_edge(clk)) then
sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;

process(reset,sclk, load, p,t)

begin
if (sclk'event and sclk ='1') then
if(reset = '1') then
q<= "0000";
elsif( t = '1') then
if( load = '1') then
q <=d;
else
if(p='1') then
q <= q + 1;
elsif(p='0')then
q<=q-1;

end if;
end if; end if; end if;
end process;
end Behavioral;

Department of Electronics & Communication Engg. 23 Dr. TTIT, KGF

IV SEMESTER HDL Lab

VERILOG CODE

module syn_count(clk,reset,load,p, d, q);

input clk,reset,load,p;
input [3:0] d;
output [3:0] q;

reg [3:0] q;

always@ (posedge clk)

begin
if(reset == 1)
q<= "0000";

else if( load == 1)

q <=d;
else if(p==1)
q <= q + 1;
else
q<=q-1;
end
endmodule

20) VHDL code to implement BCD SYNCHRONOUS RESET COUNTER.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd_synreset is
Port ( clk,reset,load,p,t : in std_logic;
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end bcd_synreset;

Department of Electronics & Communication Engg. 24 Dr. TTIT, KGF

IV SEMESTER HDL Lab

architecture Behavioral of bcd_synreset is

signal sclkdiv : std_logic_vector(15 downto 0);
signal sclk: std_logic;
begin

process(clk)
begin
if(rising_edge(clk)) then
sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;

process(reset,sclk, load, p,t)

begin

if (sclk'event and sclk ='1') then

if(reset = '1') then

q<= "0000";
elsif( t = '1') then
if( load = '1') then
q <= d;
else
if(p='1') then
q <= q + 1;
if(q = "1001") then
q<= "0000";
end if;
else
q<= q-1;
if(q = "0000") then
q<= "1001";
end if
end if;
end if; end if; end if;
end process;
end Behavioral;

Department of Electronics & Communication Engg. 25 Dr. TTIT, KGF

IV SEMESTER HDL Lab

VERILOG CODE

module BCD_c(clk,reset,load,p, d, q);

input clk,reset,load,p;
input [3:0] d;
output [3:0] q;

reg [3:0] q;

always@ (reset,posedge clk, load, p)

begin

if(reset == 1)
q<= 0000;
else if( load == 1)
q <=d;
else if(p==1)
q <= q + 1;
if(q == 1001)
q<= 0000;

end

endmodule

21) VHDL code to implement BCD ASYNCHRONOUS RESET COUNTER.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd_asynreset is
Port ( clk,reset,load,p,t : in std_logic;
d : in std_logic_vector(3 downto 0);

Department of Electronics & Communication Engg. 26 Dr. TTIT, KGF

IV SEMESTER HDL Lab

q : inout std_logic_vector(3 downto 0));

end bcd_asynreset;

architecture Behavioral of bcd_asynreset is

signal sclkdiv : std_logic_vector(15 downto 0);
signal sclk: std_logic;
begin

process(clk)
begin
if(rising_edge(clk)) then
sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;

process(reset,sclk, load, p,t)

begin
if(reset = '1') then
q<= "0000";
elsif (sclk'event and sclk ='1') the

if( t = '1') then

if( load = '1') then

q <= d;
else
if(p='1') then

q <= q + 1;

if(q = "1001") then q<= "0000"; end if;

else q<= q-1;

if(q = "0000") then q<= "1001"; end if;

end if;
end if; end if; end if;
end process;

end Behavioral;

Department of Electronics & Communication Engg. 27 Dr. TTIT, KGF

IV SEMESTER HDL Lab

22. VHDL code to simulate elevator operation

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K: in std_logic
);
end TKBELE;

architecture behavioral of TKBELE is

signal scurflr,snxtflr,skeyflr : integer range 0 to 15;

signal sdir, skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal lkeyscn : std_logic_vector(3 downto 0);
signal lkeyret : std_logic_vector(3 downto 0);
signal sclkdiv : std_logic_vector(15 downto 0);
signal sflrclk,skeyclk : std_logic;

begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';

Department of Electronics & Communication Engg. 28 Dr. TTIT, KGF

IV SEMESTER HDL Lab

when "1011" => skeyhit <= '1';

when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;

-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyflr <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyflr <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyflr <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyflr <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
then skeyflr <= 4;
elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyflr <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyflr <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyflr <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyflr <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")

then skeyflr <= 9;

elsif(lkeyscn = "1011" and lkeyret = "1011")
then skeyflr <= 10;
elsif(lkeyscn = "1011" and lkeyret = "0111")
then skeyflr <= 11;
elsif(lkeyscn = "0111" and lkeyret = "1110")
then skeyflr <= 12;
elsif(lkeyscn = "0111" and lkeyret = "1101")
then skeyflr <= 13;
elsif(lkeyscn = "0111" and lkeyret = "1011")

Department of Electronics & Communication Engg. 29 Dr. TTIT, KGF

IV SEMESTER HDL Lab

then skeyflr <= 14;

elsif(lkeyscn = "0111" and lkeyret = "0111")
then skeyflr <= 15;
end if;
end if;
end process;

-- process clk divider

--
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

skeyclk <= sclkdiv(6);

sflrclk <= sclkdiv(15);
end process;

-- process for key scan clkscan

process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
elsif skeyscn = "1011" then skeyscn <= "0111";
elsif skeyscn = "0111" then skeyscn <= "1110";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;

-- process floor motion

process(sflrclk)

begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;
end if;
end if;
end if;
end process;

-- process display 7seg

Department of Electronics & Communication Engg. 30 Dr. TTIT, KGF

IV SEMESTER HDL Lab

process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000
111",
"1111111
","1101111","1110111","1111100","1011000","1011110","1111001","1110001");
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
end process;

end behavioral;

23. VHDL code for accepting hexakey pad input data and to display the value on
the given seven segment display

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBHKY is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pledind : out std_logic_vector (7 downto 0);
pclk100K : in std_logic
);

end TKBHKY;

architecture behavioral of TKBHKY is

signal skeyval : integer range 0 to 15;

signal skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal lkeyscn : std_logic_vector(3 downto 0);
signal lkeyret : std_logic_vector(3 downto 0);
signal sclkdiv : std_logic_vector(7 downto 0);
signal skeyclk : std_logic;

begin
-- process keypress
process(pkeyret)

Department of Electronics & Communication Engg. 31 Dr. TTIT, KGF

IV SEMESTER HDL Lab

begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;

process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;

-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyval <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyval <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyval <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyval <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")

then skeyval <= 4;

elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyval <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyval <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyval <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyval <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")
then skeyval <= 9;
elsif(lkeyscn = "1011" and lkeyret = "1011")
then skeyval <= 10;
elsif(lkeyscn = "1011" and lkeyret = "0111")

Department of Electronics & Communication Engg. 32 Dr. TTIT, KGF

IV SEMESTER HDL Lab

then skeyval <= 11;

elsif(lkeyscn = "0111" and lkeyret = "1110")
then skeyval <= 12;
elsif(lkeyscn = "0111" and lkeyret = "1101")
then skeyval <= 13;
elsif(lkeyscn = "0111" and lkeyret = "1011")
then skeyval <= 14;
elsif(lkeyscn = "0111" and lkeyret = "0111")
then skeyval <= 15;
end if;
end if;
end process;

-- process clk divider

--
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

skeyclk <= sclkdiv(6);

end process;

-- process for key scan clkscan

process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
elsif skeyscn = "1011" then skeyscn <= "0111";

elsif skeyscn = "0111" then skeyscn <= "1110";

else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;

-- process display 7seg

process(skeyval)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000
111",
"1111111
","1101111","1110111","1111100","1011000","1011110","1111001","1110001");

Department of Electronics & Communication Engg. 33 Dr. TTIT, KGF

IV SEMESTER HDL Lab

begin
pdspseg <= segval(skeyval);
pdspmux <= "1110";
end process;

-- process display ledind

process(skeyval)
type tled8 is array(0 to 15) of std_logic_vector (7 downto 0);
constant led8val : tled8 :=
("00000000","00000001","00000010","00000100",
"00001000","00010000","00100000","01000000",
"10000000","00001001","00001010","00001011",
"00001100","00001101","00001110","00001111");
begin
pledind <= led8val(skeyval);
end process;

end behavioral;

24. VHDL code to display the message on the LCD

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tkblcd is
Port (
plcddat : out std_logic_vector (7 downto 0);
plcdrs,plcdrw,plcden : out std_logic;
pclk100K : in std_logic
);
end tkblcd;

architecture behavioral of tkblcd is

signal sclkdiv : std_logic_vector(15 downto 0);

signal sdspclk : std_logic;
signal tchr1 : character;

constant mystr : string := "TKBASE";

begin

-- clkdivider

Department of Electronics & Communication Engg. 34 Dr. TTIT, KGF

IV SEMESTER HDL Lab

process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

sdspclk <= sclkdiv(15);

plcden <= sclkdiv(15);
end process;

-- display
process(sdspclk)
variable vdspseq : integer range 0 to 15;
variable vdspnum : integer range 0 to 15;
variable i1 : integer;

type tlcdtyp is array(0 to 15) of std_logic_vector (7 downto 0);

constant tlcddat : tlcdtyp :=

("00111000","00001110","00000010","00000001",
"01000001","01000100","01001101","00100000",
"01000001","01000100","01001101","00100000",
"01000001","01000100","01001101","00100000"
);

begin

if(falling_edge(sdspclk) ) then
vdspseq := vdspseq+1;
end if;
if(falling_edge(sdspclk) ) then
if(vdspseq > 3) then
vdspnum := vdspnum+1;
end if;
end if;

if(vdspseq < 4) then

plcddat <= tlcddat(vdspseq);
vdspnum := 0;
else

-- plcddat <= tlcddat(vdspseq);

tchr1 <= mystr(vdspnum);

plcddat <= std_logic_vector(to_unsigned(character'pos(tchr1),8));
end if;

Department of Electronics & Communication Engg. 35 Dr. TTIT, KGF

IV SEMESTER HDL Lab

plcdrw <= '0';

if(vdspseq < 4) then
plcdrs <= '0';
else
plcdrs <= '1';
end if;

end process;

end behavioral;

25. VHDL code to control the SPEED AND DIRECTION OF STEPPER MOTOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBSTP is
Port ( pkeycol : in std_logic_vector (3 downto 0);
pkeyrow : out std_logic_vector (3 downto 0);
pstpsig : out std_logic_vector(3 downto 0);
pspdcntrl : in std_logic_vector (1 downto 0);
pclk100K : in std_logic );
end TKBSTP;

architecture behavioral of TKBSTP is

signal sclkdiv : std_logic_vector(20 downto 0);
signal sstpcnt : std_logic_vector(1 downto 0);
signal sstpclk,skeyhit : std_logic;
signal skeysts :std_logic_vector (3 downto 0);

begin

-- clkdivider
process(pclk100k,pspdcntrl)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
if ( pspdcntrl = "00") then
sstpclk <= sclkdiv(14);
elsif ( pspdcntrl = "01") then
sstpclk <= sclkdiv(16);

Department of Electronics & Communication Engg. 36 Dr. TTIT, KGF

IV SEMESTER HDL Lab

elsif ( pspdcntrl = "10") then

sstpclk <= sclkdiv(18);
elsif ( pspdcntrl = "11") then
sstpclk <= sclkdiv(20);
end if;
end process;

-- key process
-- out key row = 0 check key col
pkeyrow <= "0000";
process(pkeycol)
begin

if(pkeycol(0) = '0' or
pkeycol(1) = '0' or
pkeycol(2) = '0' or
pkeycol(3) = '0' ) then skeyhit <= '0';
else skeyhit <= '1';
end if;
end process;

-- latch key press

process(skeyhit)
begin
if( falling_edge(skeyhit)) then
skeysts <= pkeycol;
end if;
end process;

-- 4 step counter
process(sstpclk)
begin
if(rising_edge(sstpclk)) then
if(skeysts(0) = '0') then
sstpcnt <= sstpcnt+1;
elsif(skeysts(1) = '0') then
sstpcnt <= sstpcnt-1;
end if;
end if;
end process;

-- outputs signal pstpsig = D, C, B & A for stepper motor

-- als stepper controller = 4, 6, 3 & 5
process(sstpcnt)
begin
if (sstpcnt = "00") then pstpsig <= "0001";
elsif(sstpcnt = "01") then pstpsig <= "0111";

Department of Electronics & Communication Engg. 37 Dr. TTIT, KGF

IV SEMESTER HDL Lab

elsif(sstpcnt = "10") then pstpsig <= "1110";

elsif(sstpcnt = "11") then pstpsig <= "1000";
end if;
end process;

end behavioral;

26. DAC

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TKBDAC is
Port ( pdigout : out std_logic_vector(7 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pledind : out std_logic_vector (7 downto 0);
pclk100K : in std_logic;
pcwave : in std_logic;
psqrwave : out std_logic
);
end TKBDAC;

architecture Behavioral of TKBDAC is

signal sclkdiv : std_logic_vector(7 downto 0);
signal sclkin,sfclk : std_logic;
signal scount : std_logic_vector(7 downto 0);
signal scmode : std_logic;

begin
-- process clk divider
--
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;

Department of Electronics & Communication Engg. 38 Dr. TTIT, KGF

IV SEMESTER HDL Lab

sfclk <= sclkdiv(1);

sclkin <= sclkdiv(3);
end process;

-- process count up/down/ramp

process(sclkin)
begin

if( rising_edge(sclkin)) then

-- ramp wave
if(pcwave = '0') then
scount <= scount+1;
end if;
-- triangular wave
if(pcwave = '1') then
if(scmode = '0') then
-- upcounter
scount <= scount+1;
else
-- down counter
scount <= scount-1;
end if;
end if;
end if;
pdigout <= scount;
end process;

process(sfclk)
begin
if( rising_edge(sfclk)) then
if(scount = "11111111") then
scmode <= '1';
end if;
if(scount = "00000000") then
scmode <= '0';
end if;
end if;
psqrwave <= scmode;
end process;

end Behavioral;

27. VHDL code to convert ANALOG TO DIGITAL

library IEEE;

Department of Electronics & Communication Engg. 39 Dr. TTIT, KGF

IV SEMESTER HDL Lab

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TKBADC1 is
Port ( pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
padcclk,padccs : out std_logic;
padcdat : in std_logic;
pclk100K : in std_logic);
end TKBADC1;

architecture behavioral of TKBADC1 is

signal sclkdiv : std_logic_vector(16 downto 0);
signal sadcreg : std_logic_vector(11 downto 0);
signal sadcregbuf : std_logic_vector(11 downto 0);
signal sadccnt : std_logic_vector(4 downto 0);
signal sadcclk, sadccs : std_logic;
signal sledval : std_logic_vector (3 downto 0);
signal sledseg : std_logic_vector (6 downto 0);
signal sdspseq : std_logic_vector(2 downto 0);
signal sdspmux : std_logic_vector(3 downto 0);
signal smuxclk : std_logic;
signal stmpclk : std_logic;

begin
-- process clk divider
process(pclk100k)
begin
if( pclk100k = '1' and pclk100k'event) then
sclkdiv <= sclkdiv+1;
end if;

smuxclk <= sclkdiv(0);

sdspseq(0) <= sclkdiv(1);
sdspseq(1) <= sclkdiv(2);
sdspseq(2) <= sclkdiv(3);
stmpclk <= sclkdiv(15);

sadccs <= sclkdiv(16);

padccs <= sadccs;

if( (sadccnt /= "1111") and sadccs = '0')

then sadcclk <= sclkdiv(11);
end if;
padcclk <= sadcclk;

Department of Electronics & Communication Engg. 40 Dr. TTIT, KGF

IV SEMESTER HDL Lab

end process;

-- process adc count

process(sadcclk)
begin
if( falling_edge(sadcclk) )
then sadccnt <= sadccnt+1;
end if;
if(sadccs = '1')
then sadccnt <= "00000";
end if;
end process;

-- process adc read

process(sadcclk)
begin
if( rising_edge(sadcclk))
then
sadcreg(0) <= padcdat;
sadcreg(1) <= sadcreg(0);
sadcreg(2) <= sadcreg(1);
sadcreg(3) <= sadcreg(2);
sadcreg(4) <= sadcreg(3);
sadcreg(5) <= sadcreg(4);
sadcreg(6) <= sadcreg(5);
sadcreg(7) <= sadcreg(6);
sadcreg(8) <= sadcreg(7);
sadcreg(9) <= sadcreg(8);
sadcreg(10) <= sadcreg(9);
sadcreg(11) <= sadcreg(10);
end if;
-- if(sadccs = '0' and sadccnt = "00000") then
-- sadcreg <= "000000000000";
-- end if;

end process;

-- process trf to buff

process(sadccs)
begin

if(rising_edge(sadccs))
then sadcregbuf <= sadcreg;
end if;
end process;

-- tst counter

Department of Electronics & Communication Engg. 41 Dr. TTIT, KGF

IV SEMESTER HDL Lab

-- process(stmpclk)
-- begin
-- if(rising_edge(stmpclk)) then
-- sadcreg <= sadcreg+1;
-- end if;
-- end process;
-- process pdspmux
process(sdspseq)
begin
if(sdspseq = "000") then sdspmux <= "1110";
elsif(sdspseq = "010") then sdspmux <= "1101";
elsif(sdspseq = "100") then sdspmux <= "1011";
elsif(sdspseq = "110") then sdspmux <= "0111";
else sdspmux <= "1111";
end if;
pdspmux <= sdspmux;
end process;

-- process bin to 7seg

process(sledval)
begin
case sledval is
when "0000" => pdspseg <= "0111111";
when "0001" => pdspseg <= "0000110";
when "0010" => pdspseg <= "1011011";
when "0011" => pdspseg <= "1001111";
when "0100" => pdspseg <= "1100110";
when "0101" => pdspseg <= "1101101";
when "0110" => pdspseg <= "1111101";
when "0111" => pdspseg <= "0000111";
when "1000" => pdspseg <= "1111111";
when "1001" => pdspseg <= "1100111";
when "1010" => pdspseg <= "1110111";
when "1011" => pdspseg <= "1111100";
when "1100" => pdspseg <= "1011000";
when "1101" => pdspseg <= "1011110";
when "1110" => pdspseg <= "1111001";
when "1111" => pdspseg <= "1110001";
when others => pdspseg <= "0000000";

end case;
end process;

-- process muxdisp
-- process(sdspmux)
-- begin
-- if(sdspmux = "0111") then

Department of Electronics & Communication Engg. 42 Dr. TTIT, KGF

IV SEMESTER HDL Lab

-- sledval <= (sadcreg(3),sadcreg(2),sadcreg(1),sadcreg(0));

-- elsif(sdspmux = "1011") then
-- sledval <= (sadcreg(7),sadcreg(6),sadcreg(5),sadcreg(4));
-- elsif(sdspmux = "1101") then
-- sledval <= (sadcreg(11),sadcreg(10),sadcreg(9),sadcreg(8));
-- else sledval <= "0000";
-- end if;
-- end process;

-- process muxdisp
process(sdspmux)
begin
if(sdspmux = "0111") then
sledval <=
(sadcregbuf(3),sadcregbuf(2),sadcregbuf(1),sadcregbuf(0));
elsif(sdspmux = "1011") then
sledval <=
(sadcregbuf(7),sadcregbuf(6),sadcregbuf(5),sadcregbuf(4));
elsif(sdspmux = "1101") then
sledval <=
(sadcregbuf(11),sadcregbuf(10),sadcregbuf(9),sadcregbuf(8));
else sledval <= "0000";
end if;
end process;

end behavioral;

28. VHDL code to control the speed of DC motor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBDCM is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
p100k : in std_logic
);
end TKBDCM;

architecture behavioral of TKBDCM is

signal sclkdiv : std_logic_vector(11 downto 0);

begin

-- count upto 3000

Department of Electronics & Communication Engg. 43 Dr. TTIT, KGF

IV SEMESTER HDL Lab

process(p100k)
begin
if( rising_edge(p100k)) then
sclkdiv <= sclkdiv+1;
end if;

if(sclkdiv = "101110111000") then

sclkdiv <= "000000000000";
end if;
end process;

process(psw,sclkdiv)
variable vdcm : bit;
begin
if(sclkdiv = "000000000000") then
vdcm := '1';
end if;
-- 1f4,320,44c,578,6a4,7d0,8fc,9c4
if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';
elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0';
elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0';
elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0';
elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0';
elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0';

elsif(psw = "111" and sclkdiv = "100111000100") then vdcm := '0';

end if;

if(vdcm = '1') then pdcm <= '1';

else pdcm <= '0';
end if;

end process;

end behavioral;

29. VHDL code to control external lights using relay

library IEEE;

Department of Electronics & Communication Engg. 44 Dr. TTIT, KGF

IV SEMESTER HDL Lab

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity relay_con is
Port ( a : in std_logic;
b : out std_logic);
end relay_con;

architecture Behavioral of relay_con is

begin

process(a)
begin

if (a='1') then
b<= '1';

else
b<= '0';

end if;
end process;

end Behavioral;

Department of Electronics & Communication Engg. 45 Dr. TTIT, KGF