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Ripple Carry Adder Aim:: Page 36 of 70

The document describes a student project to develop VHDL source code for a 4-bit ripple carry adder. It includes the algorithm, logic diagram, truth table and VHDL code for a full adder and 4-bit adder. The code is compiled, simulated and synthesized using Xilinx ISE 7.1i software. The output is verified for different input combinations.

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Ganesh03071988
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© Attribution Non-Commercial (BY-NC)
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Topics covered

  • Port Mapping,
  • Debugging Techniques,
  • Circuit Simulation,
  • Binary Addition,
  • XILINX ISE,
  • Design Entities,
  • Synthesis,
  • Sequential Logic,
  • Signal Declaration,
  • Simulation
55 views4 pages

Ripple Carry Adder Aim:: Page 36 of 70

The document describes a student project to develop VHDL source code for a 4-bit ripple carry adder. It includes the algorithm, logic diagram, truth table and VHDL code for a full adder and 4-bit adder. The code is compiled, simulated and synthesized using Xilinx ISE 7.1i software. The output is verified for different input combinations.

Uploaded by

Ganesh03071988
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

Topics covered

  • Port Mapping,
  • Debugging Techniques,
  • Circuit Simulation,
  • Binary Addition,
  • XILINX ISE,
  • Design Entities,
  • Synthesis,
  • Sequential Logic,
  • Signal Declaration,
  • Simulation

EX No: 5 NAME: Kannan.

REG No: 3013823 DATE: 12.02.2012

RIPPLE CARRY ADDER AIM: To develop source code for ripple carry adder circuit by using VHDL and obtain the simulation, synthesis using XILINX ISE 7.1i

ALGORITHM:

Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

Page 36 of 70

EX No: 5 NAME: Kannan.H

REG No: 3013823 DATE: 12.02.2012

TRUTH TABLE:

INPUT A0 0 0 0 0 0 0 0 1 A1 0 0 0 0 1 1 1 1 A2 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 B0 0 0 0 0 0 0 1 1 B1 0 0 0 0 1 1 1 1 B2 0 0 1 1 0 1 1 1 B3 0 1 0 1 1 1 0 1 CIN 0 0 0 0 0 0 1 1 S0 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 1 1 1

OUTPUT S2 0 1 0 1 1 1 0 1 S3 0 0 0 0 0 1 1 1 COUT 0 0 0 0 0 0 1 1

FULL ADDER:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity onebit is Port (a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; s : out STD_LOGIC; cout : out STD_LOGIC); end onebit; architecture Behavioral of onebit is begin s<=a xor b xor cin; cout<=(a and b) or (a and cin) or (b and cin); end Behavioral; 4-BIT ADDER:

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

Page 37 of 70

EX No: 5 NAME: Kannan.H

REG No: 3013823 DATE: 12.02.2012

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fourbit is Port ( clk : in STD_LOGIC; a4 : in STD_LOGIC_VECTOR (3 downto 0); b4 : in STD_LOGIC_VECTOR (3 downto 0); cin4 : in STD_LOGIC; s4 : out STD_LOGIC_VECTOR (3 downto 0); cout4 : out STD_LOGIC); end fourbit; architecture Behavioral of fourbit is component onebit Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; s : out STD_LOGIC; cout : out STD_LOGIC); end component; SIGNAL c : STD_LOGIC_VECTOR(3 downto 1); begin FA0: onebit PORT MAP ( FA1: onebit PORT MAP ( FA2: onebit PORT MAP ( FA3: onebit PORT MAP (

a4(0), b4(0), cin4, s4(0), c(1)); a4(1), b4(1), c(1), s4(1), c(2)); a4(2), b4(2), c(2), s4(2), c(3)); a4(3), b4(3), c(3), s4(3), cout4);

end Behavioral;

SIMULATION REPORT:

Page 38 of 70

EX No: 5 NAME: Kannan.H

REG No: 3013823 DATE: 12.02.2012

SYNTHESIS REPORT:

RESULT:
Thus the VHDL codes for Ripple Carry Adder were written, simulated synthesized and the outputs verified.

Page 39 of 70

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