ANNA UNIVERSITY OF TECHNOLOGY MADURAI ME/VLSI ( Part Time)
Internal Test II COMPUTER AIDED DESIGN FOF VLSI CIR CUITS
Part A (5X2=10) 1.
2. 3.
Write the types of minimum design rules Draw a cell, port and data model of a NAND gate Define a Layout compaction Define Bellman Ford Algorithm Write the optimization Problem in floor Estimation Part B (40 Marks) Explain partitioning (8) Or Write the rules of Layout compaction (8)
4.
5.
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8.
Explain the algorithm for constraint graph compaction (16) Or Explain Various placement problems in details (16)
9.
10.
Explain various application of compaction(16) Or
11.
Explain Floor Planning (16)