0% found this document useful (0 votes)
108 views1 page

Cube33 02

This document provides a schematic for an electronic board. The schematic shows various components including a 68040 CPU, transfer control logic, memory control, phase locked loop, configuration logic, and ADB interface. It connects these components and indicates signals between them. The schematic also specifies pin connections and includes component designations, values, and notes related to configurations.

Uploaded by

Bayanaa Peace
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
108 views1 page

Cube33 02

This document provides a schematic for an electronic board. The schematic shows various components including a 68040 CPU, transfer control logic, memory control, phase locked loop, configuration logic, and ADB interface. It connects these components and indicates signals between them. The schematic also specifies pin connections and includes component designations, values, and notes related to configurations.

Uploaded by

Bayanaa Peace
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

8

68040

AD(31:0)

SIZR(1:0)

R_W

_LOCK
_LOCKE
_CIOUT

TRANSFER
TRAITS
R16
T14
S13
T10

_TSR
_TA
_TEA
_TCITBI

S11
T9

PULLUP1

T13
T17

_BG(0)
_BBR
_IPL(2:0)
_AVEC

T11
1

SC(1:0)
S7

_MODEN
PULLUP1

T5
S6

TESTTDI
TESTTCK
TESTTMS
PON

S3
S4
S5
T3

AD(31:0)
SIZ(1:0)
R_W
TT(1:0)
S18
R18
R1

96

_BR(2:0)

_BR(2:0)
102
_BB
151
_LOCK
147
_LOCKE

_LOCK
_LOCKE

DLE

163

PON
_BR

_IPEND

_IPL(2:0)
_AVEC

_MI
_RSTO

_RSTI

T18

_BRR(0)

VCC

R27
10K

VCC

S1

VD(15:0)

R51
10K

R26
10K

_AVEC

_LOCK

_RESETOUT

R3

T2

_VRAS
_VCAS(1:0)
_VWE
VMA(8:0)
_VDTOE
VDSF
_VSYNC
HSYNC_
VBLANK_
_VSOE(1:0)
VSC(1:0)

TESTTDO040

VCC

R21
10K
NO LOAD
2

173

VLOAD

VCLK

_RASA
_RASB
_RASC
_RASD
_RASV
_CAS0(3:0)
_CAS1(3:0)
_WE(3:0)
MA0(10:0)
MA1(10:0)
_ROMSEL

PD0(3:0)
PD1(3:0)

VCC

MEMCTL

R24
10K
NO LOAD
1

R25
10K
NO LOAD
0

_RDLE0
_RDLE1
_RDLOE0
_RDLOE1
WRLE0
WRLE1
_WRLOE

LATCH CTL

CR20

CR17

MMBD201T1
P2

P1

MMBD201T1
P2

31

MMBD201T1

MMBD201T1

MISC

P2

29

28

BITS 31:28 SD FIELD:0


_CONFIGRST
CR10

P1

NO_LOAD

P1

CR9

MMBD201T1
P2

166
TDI
164
TCK
165
TMS
168
ATPG

TESTDOPC
TESTTCK
TESTTMS

AD(31:0)

P1

MMBD201T1

GPOUT
_TMCINT(2:0)
TDO

14
18
19
15
13
17

10

VLOAD

44
40
42
41
43

_RASA
_RASB
_RASC
_RASD

P1

P2

NO_LOAD

CR5

P1

P2

11

NO_LOAD
10

RESETOUT

74F00

R79
CLKC25M

U40
74ACT00
10
8
9

RESETOUT

P1

CR16

RESETOUT2

LA TEST POINTS
_DEVRST

NO_LOAD
9

FL3
100MHz

MMBD201T1

20
23

JP5

P2

NO_LOAD

ADBF

22
28
27
26
25
24

ADBJ

CLKBCLKB

WRLE0

10

74F00
8

R83

_LATWRLE0

_LATWRLE0R

C99
0.1
50V

_WRLOE

171

ADBDRIVE

172

GPOUT
_TMCINT(2:0)

167

TESTTDO

NO_LOAD
GPOUT

1
2

R95

R94

10

RC1

1.0K

TESTPLLEN

VCC
R119
10K

RC1

U42

R115

MC88915FN70

FEEDBACK

SYNC(0)
11
SYNC(1)
6
REFSEL
18
PLLEN
12
FREQSEL
4
_RST

CLKBCLK2

VCCA
LOCK
2XQ
Q0
Q1
Q2
Q3
Q4
_Q5
QDIV2

21.5
R117

19
26 CLKPLLOUTX2

CLKPCLK

14

21.5
R114

16
CLKPLLQ0
21
23
28
2 CLKPLLQ5

CLKBCLK

21.5
R114
CLKBCLKB

25
21.5
R122

CLKQDIV2
SPEEDSEL

VCC

10UH

C100
3300PF
50V

VCC

L10

CLKPLLQ1
9

GNDA

CLKNBIC

21.5

R118
10K

R23

VCC

162

1.0K
BITS 11:8 = Board Revision

MMBD7000L

MEMSPSEL1

MEMSPSEL0

C102
0.1
50V

R2
1.0K

R105
475

_CONFIGSPD

JP3

VCC

C101
0.1
50V

L9
10uH

PLLSIG1

1.0M

1
2

GPOUT JUMPER

PWRPLLGND

AD(31:0)

_LATWRLE1R
10

PWRPLLVCC

WRLE0
WRLE1

JP4
R106

R73

_LATWRLE1

U36

CLKPLLQ3

ADBDATAIN

PHASE LOCKED LOOP

_RDLE0
_RDLE1
_RDLOE0
_RDLOE1

NO_LOAD

CR38

74F00

WRLE1

1
2

U36

10

JTAG

CR18

CLK25PLLIN
10

INTERLEAVE LATCH CLOCKS

MA0(10:0)
MA1(10:0)
_ROMSEL

12

MMBD201T1
P2

_CAS0(3:0)
_CAS1(3:0)
_WE(3:0)

ADB DRIVER

MMBD201T1

CLOCK SPEED SELECT

NO_LOAD

VCC

MMBD201T1

_VRAS
_VCAS(1:0)
_VWE
VMA(8:0)
_VDTOE
VDSF
_VSYNC
HSYNC
VBLANK
_VSOE(1:0)
CLKVSC(1:0)

MMBD201T1

BITS 15:12 = CPU TYPE: 1000 = TCUBEBW

CR6

_CONFIGRST

P2

13

_CONFIGRST
P1

CLKC33M
CLK25PLLIN

AD(31:0)

ADBDRIVE

182

CR7

P2

14

74ACT00

P1

CR8

MMBD201T1
P2

15

ADB

ADBDATAIN

CR19

P2

30

169

ADBDATAIN

P1

CR11

_RESETOUT

RESETOUT

_CPURSTIN

_LOCKE

P1

160

RST

_CONFIGRST
P1

RESETOUT

U26

CONFIGURATION
B

U9

LOW CURRENT SELECT:


2 Installed = DATA BUS
1 Installed = ADDRESS and CONTROL
0 Installed = ARBITRATION and MISC
_BB

RESET INVERTERS

ARBITRATION

_IPL(2:0)

PULLUP1

U2
AM27C010

_BG(2:0)

_BG(2:0)

VD(15:0)

CLKVCLK

R40
221

_CE
_OE
_P
VPP

VCC

R39
221

22
24
31
VCC

PD1(3:0)

D(7:0)

A(16:0)
_ROMSELR

3:0

ROM_D(7:0)

ROM_A(16:0)

SYSTEM BUS

Q16

VCC
VCC

MA1R(5:0)

JTAQ

PULLUPS

PD0(3:0)
7:4

16:11

261

VIDEO

TDO

TDI
TCK
TMS
_TRST

CLKC25M

R4

PON

RESET

_CDIS
_MDIS

EPROM
10:0

_ROMSEL

162
_CPURSTIN
161
_RESETIN

_CPURSTIN
_DEVRST

PD0(3:0)
PD1(3:0)

VCC

AD(31:0)
SIZ(1:0)
_RW
TT(1:0)

177
176
175

_TS
100
_TA
99
_TEA
98
_TCITBI

_TCITBI

TRANSFER
CONTROL

ARB

R15

_TBI

_BG
_BB

CLK20
CLK25
CLK33

CLOCKS

101

_TS
_TA
_TEATMC

_LOCKR
_LOCKER

_BB

SC(1:0)

_RESETOUT

_TIP

_TS
_TA
_TEA
_TCI

179
CLK100
144
BCLKIN
145
BCLKE

CLKBCLK

TM(2:0)
TLN(1:0)
UPA(1:0)

SIZ(1:0)
N16

R_WR

MA0R(10:0)

BUS

TT(1:0)

TMC

PST(3:0)

A(31:0)

TMC_CHIP

CLOCKS/STATUS
PCLK
BCLK
D(31:0)

TTR(1:0)

U18
MC68040_33MHZ

R9
R7

CLKPCLK
CLKBCLK

C117
3300PF
50V

C116
3300PF
50V

C106
3300PF
50V

C115
3300PF
50V

C109
3300PF
50V

_CONFIGRST
P1

CR13

P1

P2

NO_LOAD

P1

CR12

CR15

P1

ADBF

CR14
R102

MMBD201T1

MMBD201T1

MMBD201T1

P2

1
AD(31:0)

P2

ADBDRIVE

MMBD201T1

ADBDRVRES

U9
74ACT00

MMBT4401T1

P2

Q8

1.0K

RESETOUT

AD(31:0)

BITS 2:0 = CPU SPEED: 101 = 20MHZ


110 = 25MHZ
111 = 33MHZ

BITS 5:4 = MEM SPEED: 11 = 100NS


10 = 80NS
01 = 70NS

12
13

11

_CONFIGSPD

PN4643AA

CPU : TMC : EPROM : PLL : CONFIG : ADB


6

Sheet

of

17
Cube33-02.pdf 001

You might also like