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EXP4

The document describes the design and implementation of several digital circuits in VHDL including: 1. A 16-bit up/down counter built using 4-bit up/down counters chained together. 2. An 8-bit shift register with parallel loading and output capabilities. 3. An "1101" sequence detector circuit. 4. A "0101" sequence detector circuit that does not allow overlapping sequences. The VHDL code, RTL schematics, and simulations are provided for each circuit.

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Rohan__Makwana
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80 views

EXP4

The document describes the design and implementation of several digital circuits in VHDL including: 1. A 16-bit up/down counter built using 4-bit up/down counters chained together. 2. An 8-bit shift register with parallel loading and output capabilities. 3. An "1101" sequence detector circuit. 4. A "0101" sequence detector circuit that does not allow overlapping sequences. The VHDL code, RTL schematics, and simulations are provided for each circuit.

Uploaded by

Rohan__Makwana
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment : 4 Title:

Name : Rohan Makwana(12MECV16)

Design, Implement, simulate and synthesize the following circuits : A. 16 bit up and down counter B. 8 bit shift register with parallel loading, parallel output, serial in-out capacity C. 1101 Sequence Detector (overlapped) D. 0101 Sequence detector (non overlapped).

A. 16 bit up and down counter logic design :

for 16 bit there is 16 flip flops are required and the input of J and K is short so it is nothing but a T flip flop so, implementation is done with this circuit reference.

VHDL Codes :
T Flip flop :

4 bit Counter :

Note :

if we write Q as STD_LOGIC_VECTOR (3 downto 0) then code check correctly and also synthesize but it uses only one T FF (in RTL) so, it's output is undefined and the code not work properly.

16 bit Counter :
To implement the 16 bit counter we use the port map of 4 (4 bit UP/DOWN Counter) so, only code complexity get reduced.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity counter_16bit_up_down is port ( T : in STD_LOGIC; clk : in STD_LOGIC; Reset : in STD_LOGIC; up_down: in STD_LOGIC; Q : buffer STD_LOGIC_VECTOR(15 downto 0); NQ : buffer STD_LOGIC_VECTOR(15 downto 0) ); end counter_16bit_up_down; architecture Behavioral of counter_16bit_up_down is component counter_4bit_up_down is Port ( T_in : in STD_LOGIC; Clock : in STD_LOGIC; Clear : in STD_LOGIC; up : in STD_LOGIC; Q0 : buffer STD_LOGIC; NQ0 : buffer STD_LOGIC; Q1 : buffer STD_LOGIC; NQ1 : buffer STD_LOGIC; Q2 : buffer STD_LOGIC; NQ2 : buffer STD_LOGIC; Q3 : buffer STD_LOGIC; NQ3 : buffer STD_LOGIC ); end component; signal toggle1,toggle2,toggle3 : STD_LOGIC; begin Counter1 : counter_4bit_up_down port map('1',clk,reset,up_down,Q(0),NQ(0),Q(1),NQ(1),Q(2),NQ(2),Q(3),NQ(3)); toggle1 <= ((up_down)and(Q(3))and(Q(2))and(Q(1))and(Q(0)))or((not(up_down))and (NQ(3))and(NQ(2))and(NQ(1))and(NQ(0))); Counter2 : counter_4bit_up_down port map(toggle1,clk,reset,up_down,Q(4),NQ(4),Q(5),NQ(5),Q(6),NQ(6),Q(7),NQ(7)) ;

toggle2 <= ((up_down)and toggle1 and (Q(4))and(Q(5))and(Q(6))and(Q(7)) and (Q(7))and(Q(6))and(Q(5))and(Q(4)))or((not(up_down))and toggle1 and (NQ(4))and(NQ(5))and(NQ(6))and(NQ(7))); Counter3 : counter_4bit_up_down port map(toggle2,clk,reset,up_down,Q(8),NQ(8),Q(9),NQ(9),Q(10),NQ(10),Q(11),NQ( 11)); toggle3 <= ((up_down) and toggle2 and (Q(11))and(Q(10))and(Q(9))and(Q(8)))or((not(up_down)) and toggle2 and(NQ(11))and(NQ(10))and(NQ(9))and(NQ(8))); Counter4 : counter_4bit_up_down port map(toggle3,clk,reset,up_down,Q(12),NQ(12),Q(13),NQ(13),Q(14),NQ(14),Q(15) ,NQ(15)); end Behavioral;

SIMULATION :

Another very simple way to create Counter is :

It's RTL is perfectly create a counter from device CLB. Also, Simulate perfectly.

B. 8 bit shift register with parallel loading, parallel output, serial in-out capacity :
VHDL Code :

RTL :

Simulation :

C. 1101 Sequence Detector (overlapped) : VHDL Code :

RTL :

Simulation

D. 0101 Sequence detector (non overlapped):

RTL

Simulation :

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