Machine code or machine language is a system of impartible instructions executed

directly by a computer's central processing unit (CPU). Each instruction performs a very specific task, typically either an operation on a unit of data (in a register or in memory, e.g. add or move), or a jump operation (deciding which instruction executes next, often conditional on the results of a previous instruction). Every executable program is made up of a series of these atomic instructions. Machine code may be regarded as a primitive (and cumbersome) programming language or as the lowest-level representation of a compiled and/or assembled computer program. While it is possible to write programs in machine code, because of the tedious difficulty in managing CPU resources, it is rarely done any more, except for situations that require the most extreme optimization. Almost all executable programs are written in higher-level languages, and translated to executable machine code by a compiler and linker. Machine code is sometimes called native code when referring to platformdependent parts of language features or libraries. Programs in interpreted languages are not represented by machine code; however, their interpreter (which may be seen as a processor executing the higher-level program) often is. Machine code should not be confused with so-called "bytecode", which is executed by an interpreter. example Name Code Add Sub Mov 000000 001010 100010 Decimal (0d) (10d) (14d) (34d)

Cmp 001110

Addressing modes are the ways how architectures specify the address of an object they want to
access. In GPR machines, an addressing mode can specify a constant, a register or a location in memory.
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

The most common names for addressing modes (names may differ among architectures) Addressing Example Meaning When used modes Instruction Register Add R4,R3 R4 <- R4 + R3 When a value is in a register Immediate Displacement Register deffered Indexed Add R4, #3 Add R4, 100(R1) Add R4,(R1) Add R3, (R1 + R2) R4 <- R4 + 3 R4 <- R4 + M[100+R1] R4 <- R4 + M[R1] R3 <- R3 + M[R1+R2] For constants Accessing local variables Accessing using a pointer or a computed address Useful in array addressing: R1 - base of array R2 - index amount

Direct Memory deferred Autoincrement Autodecrement Scaled

Add R1, (1001)

R1 <- R1 + M[1001]

Useful in accessing static data If R3 is the address of a pointer p, then mode yields *p Useful for stepping through arrays in a loop. R2 - start of array d - size of an element Same as autoincrement. Both can also be used to implement a stack as push and pop Used to index arrays. May be applied to any base addressing mode in some machines.

Add R1, @(R3) R1 <- R1 + M[M[R3]] Add R1, (R2)+ R1 <- R1 +M[R2] R2 <- R2 + d R2 <-R2-d R1 <- R1 + M[R2] R1<R1+M[100+R2+R3*d]

Add R1,-(R2) Add R1, 100(R2)[R3]

Notation: <- - assignment M - the name for memory: M[R1] refers to contents of memory location whose address is given by the contents of R1

Instruction Formats
Six basic instruction formats shall support 16 and 32-bit instructions. The operation code (opcode) shall normally consist of the 8 most significant bits of the instruction.

1. Register-to-Register Format The register-to-register format is a 16-bit instruction consisting of an 8-bit opcode and two 4-bit general register (GR) fields that typically specify any of 16 general registers. In addition, these fields may contain a shift count, condition code, opcode extension, bit number, or the operand for immediate short instructions. 2. Instruction Counter Relative Format The Instruction Counter (IC) Relative Format is a 16-bit instruction consisting of an 8-bit opcode and an 8-bit displacement field. 3. Base Relative Format The base relative instruction format is a 16-bit instruction consisting of a 6-bit opcode, a 2-bit base register field and an 8-bit displacement field. The base register (BR) field allows the designation of one of four different registers. 4. Base Relative Indexed Format The base relative indexed instruction format is a 16-bit instruction consisting of a 6-bit opcode, a 2-bit base register field, a 4-bit opcode extension and a 4-bit index register field. The base register (BR) field allows the designation of one of four different base registers and the index register (RX) field allows the designation of one of fifteen different index registers 5. Long Instruction Format The Long Instruction Format is a 32-bit instruction consisting of an 8-bit opcode, a 4-bit general register field, a 4-bit index register field and a 16-bit address field. 6. Immediate Opcode Extension Format

The immediate opcode extension format is a 32-bit instruction consisting of an 8-bit opcode, a 4-bit general register field, a 4-bit opcode extension and a 16-bit data field. Typically, GR1 is one of the 16 general registers on which the instruction is performing the operation. Op.Ex. is an opcode extension. 7. Special Format The special instruction format is a 16-bit instruction consisting of an 8-bit opcode followed by an 8-bit opcode extension (Op.Ex.).

An instruction set, or instruction set architecture (ISA), is the part of the

computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor. Instruction set architecture is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Computers with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs. Some virtual machines that support bytecode for Smalltalk, the Java virtual machine, and Microsoft's Common Language Runtime virtual machine as their ISA implement it by translating the bytecode for commonly used code paths into native machine code, and executing less-frequently-used code paths by interpretation; Transmeta implemented the x86 instruction set atop VLIW processors in the same fashion.
Instruction types

Some operations available in most instruction sets include:

Data handling and Memory operations o set a register (a temporary "scratchpad" location in the CPU itself) to a fixed constant value o move data from a memory location to a register, or vice versa. This is done to obtain the data to perform a computation on it later, or to store the result of a computation. o read and write data from hardware devices Arithmetic and Logic o add, subtract, multiply, or divide the values of two registers, placing the result in a register, possibly setting one or more condition codes in a status register o perform bitwise operations, taking the conjunction and disjunction of corresponding bits in a pair of registers, or the negation of each bit in a register o compare two values in registers (for example, to see if one is less, or if they are equal) Control flow o branch to another location in the program and execute instructions there o conditionally branch to another location if a certain condition holds o indirectly branch to another location, while saving the location of the next instruction as a point to return to (a call)

interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution.

A hardware interrupt causes the processor to save its state of execution and begin execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt. Interrupts are a commonly used technique for computer multitasking, especially in real-time computing. Such a system is said to be interrupt-driven. An act of interrupting is referred to as an interrupt request (IRQ). The part of a program (usually firmware, driver or operating system service) that deals with the interrupt is referred to as an interrupt service routine (ISR) or interrupt handler.

Timing diagrams are used to explore the behaviors of objects throughout a given period of
time. A timing diagram is a special form of a sequence diagram. The differences between timing diagram and sequence diagram are the axes are reversed so that the time is increased from left to right and the lifelines are shown in separate compartments arranged vertically.

clock cycle
In a computer, the clock cycle is the time between two adjacent pulses of the oscillator that sets the tempo of the computer processor. The number of these pulses per second is known as the clock speed, which is generally measured in Mhz (megahertz, or millions of pulses per second) and lately even in Ghz (gigahertz, or billions of pulses per second). The clock speed is determined by a quartz-crystal circuit, similar to those used in radio communications equipment.

Some processors execute only one instruction per clock cycle. More advanced processors, described as superscalar, can perform more than one instruction per clock cycle. The latter type of processor gets more work done at a given clock speed than the former type. Similarly, a computer with a 32-bit bus will work faster at a given clock speed than a computer with a 16-bit bus. For these reasons, there is no simple, universal relation among clock speed, "bus speed," and millions of instructions per second (MIPS).

An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decodeexecute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from bootup to when the computer is shut down. The circuits used in the CPU during the cycle are:

Program Counter (PC) - an incrementing counter that keeps track of the memory address of which instruction is to be executed next... Memory Address Register (MAR) - holds the address of a memory block to be read from or written to Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory Instruction register (IR) - a temporary holding ground for the instruction that has just been fetched from memory Control Unit (CU) - decodes the program instruction in the IR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resources Arithmetic logic unit (ALU) - performs mathematical and logical operations

16Bit Microprocessor : 8086

Features of 8086 - 8086 is a 16bit processor. Its ALU, internal registers works with 16bit binary word - 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a time - 8086 has a 20bit address bus which means, it can address upto 2 20 = 1MB memory location - Frequency range of 8086 is 6-10 MHz
8086 MINIMUM AND MAXIMUM MODES of operation
Minimum

mode The 8086 processor works in a single processor environment. All control signals for memory and I/O are generated by the microprocessor. Maximum mode is designed to be used when a coprocessor exists in the system. 8086 works in a multiprocessor environment. Control signals for memory and I/O are generated by an external BUS Controller.

8 bit architecture

16 bit

De Morgan's Theorem
AB=A+B A+B=AB A B C = A + B + C + A + B + C + = A B C

KARNAUGH MAPS
Karnaugh maps allow us to convert a truth table to a simplified Boolean expression without using Boolean Algebra. The truth table in Figure 85 is an extension of the previous burglar alarm example, an alarm quiet input has been added.

NOT Gates (Inverters)

A third important logical element is the inverter. An inverter does pretty much what it says. If the input is 0, the output is 1. Conversely, if the input is 1, the output is 0. The symbol for an inverter is shown below. Again, you can putter with this inverter with the simulated LEDs. X is the input to the inverter. The output is NOT-X represented as ~1 or: