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8086

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AGENDA

BIRTH OF 8086 WHAT IS X86? ARCHITECTURE INTERRUPTS ADDRESSING MODES TIMING DIAGRAMS INSTRUCTIONS SUCCESSORS APPLICATIONS
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BIRTH OF 8086

It all started from Intel's iAPX 432, which was a very ambitious multi-chip microprocessor architecture started in 1975. The project was Intel's first 32-bit microprocessor design. It soon became clear that it would take several years and many engineers to design it , given the current technology at that time. So, the 8086 project was started in May 1976 and was originally intended as a temporary substitute for the delayed iAPX 432 project.

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BIRTH OF 8086

The architecture was defined by Stephen P. Morse with some help and assistance by Bruce Ravenel The 8086 gave rise to the x86 architecture of Intel's future processors. It was marketed as source compatible. The 8086 was implemented using depletion-load nMOS circuitry with approximately 20K active transistors It was soon moved to a new refined nMOS manufacturing process called HMOS. The original chip measured 33 mm and minimum feature size was 3.2 m.
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WHAT IS X86?

x86 is a series of computer microprocessor instruction set architectures based on the Intel 8086 CPU. The term x86 derived from the fact that early successors to the 8086 also had names ending with "86". Many additions and extensions have been added to the x86 instruction set over the years, almost consistently with full backward compatibility.

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WHAT IS X86?

The x86 architecture is a variable instruction length, primarily two-address "CISC" design with emphasis on backward compatibility. The instruction set is not typical CISC, however, but basically an extended version of the simple eight-bit 8008 and 8080 architectures.

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KEY FEATURES

It is a 16 bit microprocessor. 8086 has a 20 bit address bus can access upto 2^20 memory locations ( 1 MB) . It can support upto 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data bus AD0- AD15 and A16 A19

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KEY FEATURES

It requires single phase clock with 33% duty cycle to provide internal timing.

8086 is designed to operate in two modes, Minimum and Maximum.

It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction execution.

It requires +5V power supply. A 40 pin dual in line package.

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PIN DIAGRAM

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EU AND BIU

The 8086 CPU logic has been partitioned into two functional units namely Bus Interface Unit (BIU) and Execution Unit (EU) The major reason for this separation is to increase the processing speed of the processor The BIU has to interact with memory and input and output devices in fetching the instructions and data required by the EU EU is responsible for executing the instructions of the programs and to carry out the required processing

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ARCHITECTURE

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GENERAL PURPOSE REGISTERS

8086 CPU has 8 general purpose registers, each register has its own name:

AX - the accumulator register (divided into AH / AL):

Generates shortest machine code Arithmetic, logic and data transfer One number must be in AL or AX Multiplication & Division Input & Output

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GENERAL PURPOSE REGISTERS

BX - the base address register (divided into BH / BL). CX - the count register (divided into CH / CL): Iterative code segments using the LOOP instruction. Repetitive operations on strings with the REP command. Count (in CL) of bits to shift and rotate. DX - the data register (divided into DH / DL): DX:AX concatenated into 32-bit register for some MUL and DIV operations. Specifying ports in some IN and OUT operations.
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GENERAL PURPOSE REGISTERS

SI - source index register:

Can be used for pointer addressing of data Used as source in some string processing instructions Offset address relative to DS DI - destination index register: Can be used for pointer addressing of data Used as destination in some string processing instructions Offset address relative to ES

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GENERAL PURPOSE REGISTERS

BP - base pointer: Primarily used to access parameters passed via the stack Offset address relative to SS SP - stack pointer: Always points to top item on the stack Offset address relative to SS Always points to word (byte at even address) An empty stack will had SP = FFFEh

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EXECUTION UNIT- FLAGS

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MEMORY SEGMENTATION

In 8086, memory has four different types of segments.

Code Segment - It contains instructions of a program in memory. Data Segment -The processor can access data in any one out of 4 available segments. Stack Segment - A stack is a section of the memory set aside to store addresses and data while a subprogram executes. Extra Segment - This segment is also similar to data memory where additional data may be stored and maintained.

Reserved locations - 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment:offset. FFFF0h FFFFFh,after RESET the processor always starts program execution at the FFFF0h address.

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SEGMENT- OFFSET Notation

The total addressable memory size is 1MB Most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory A simple scheme would be to order the bytes in a serial fashion and number them from 0 (or 1) to the end of memory

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SEGMENT- OFFSET Notation

The scheme used in the 8086 is called segmentation Every address has two parts, a SEGMENT and an OFFSET (Segment:Offset ) The segment indicates the starting of a 64 kilobyte portion of memory, in multiples of 16 The offset indicates the position within the 64k portion Absolute address = (segment * 16) + offset

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SEGMENT REGISTERS

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SEGMENT REGISTERS

Each of these segments are addressed by an address stored in corresponding segment register. These registers are 16-bit in size. Each register stores the base address (starting address) of the corresponding segment. Because the segment registers cannot store 20 bits, they only store the upper 16 bits.

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SEGMENT REGISTERS How is a 20-bit address obtained if there are only 16-bit registers?

The answer lies in the next few slides. The 20-bit address of a byte is called its Physical Address. But, it is specified as a Logical Address. Logical address is in the form of:

Base Address : Offset Offset is the displacement of the memory location from the starting location of the segment.

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EXAMPLE
The value of Data Segment Register (DS) is 2222 H. To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs of the address. After appending, the starting address of the Data Segment becomes 22220H. If the data at any location has a logical address specified as: 2222 H : 0016 H Then, the number 0016 H is the offset. 2222 H is the value of DS. To calculate the effective address of the memory, BIU uses the following formula: Effective Address = Starting Address of Segment + Offset To find the starting address of the segment, BIU appends the contents of Segment Register with 0H. Then, it adds offset to it. Therefore: EA = 22220 H + 0016 H -----------22236 H
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EXAMPLE (Contd.)

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MAX. SIZE OF SEGMENT

All offsets are limited to 16-bits. It means that the maximum size possible for segment is 216 = 65,535 bytes (64 KB). The offset of the first location within the segment is 0000 H. The offset of the last location in the segment is FFFF H.

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WHERE TO LOOK FOR THE OFFSET

Segment CS

Offset registers IP

Function Address of the next instruction

DS SS ES

BX,DI,SI SP,BP BX,DI,SI

Address of data Address in the stack Address of destination data (for string operations)

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MODES OF OPERATION MINIMUM MODE

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MODES OF OPERATION

MAXIMUM MODE
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Interrupts in 8086
An 8086 Interrupt can come from any of three sources. Hardware Interrupt External interrupt applied to nonmaskable interrupt NMI. External interrupt applied to maskable interrupt INTR. Software Interrupt Execution of INT instruction.

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Interrupts in 8086

In the 8086 there are a total of 256 interrupts (or interrupt types) INT 00 INT 01 INT FF In 80x86, the memory location to which an interrupt goes is always four times the value of the interrupt number . INT 03h goes to 000Ch

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Interrupt Vector Table IVT

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Interrupts in 8086

The lowest five types are dedicated to specific interrupts. Interrupts 5 to 31 are reserved by INTEL for complex Processors Upper 224 interrupt types ( 32 to 255) available to use for hardware or software interrupts.

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Interrupts in 8086
Interrupt Type zero INT 0 Divide by zero interrupt. If the quotient is too large to fit into AL/AX Divide by zero interrupt invoked. Interrupt Type one INT 1 Single step Interrupt If trap flag is set 8086 will do a type 1 interrupt after every instruction execution.

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Interrupts in 8086
Non Maskable Interrupt Type 2 When 8086 receives a low to high transition on its NMI input. Type 2 interrupt response cannot be disabled ( masked) by any program instruction. Could be used for handling critical situations like power failure detection.

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Interrupts in 8086
Break Point Interrupt Type 3 INT 3 instruction to implement break point routines. The system execute instruction up to break point and then goes to break point routine. Used for debugging. Overflow Interrupt Type 4 INTO: Interrupt on overflow instruction used for invoking an interrupt after overflow in an arithmetic operation. If no overflow it will be a NOP instruction.

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Interrupt Priority

HIG H

1. Divide error, INT nn, INTO 2. NMI 3. INTR 4. Single Step

LOW

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Interrupts in 8086
What if 8086 receives INTR while executing DIV which produces divide-by-zero error? 8086 executes INT 00 (as it has higher priority) This clears the IF and thus disables INTR Complete routine of INT 00 is executed and in the end IRET is executed This enables the INTR again Now INTR will be processed

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Interrupts in 8086
What if 8086 receives NMI while executing DIV which produces divide-by-zero error? 8086 executes INT 00 (as it has higher priority) This clears the IF but does not disable NMI Branching to ISR0 and then again to ISR2 Return back to ISR0 and then to mainline program

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ADDRESSING MODES

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CLOCK CYCLES USED IN DIFF ADDRESSING MODES

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INSTRUCTIONS
GENERAL PURPOSE BYTE OR WORD TRANSFER INSTRUCTION: MOV,PUSH,POP,XCHG,XLAT SPECIAL ADDRESS TRANSFER INSTRUCTION: LEA,LDS,LES FLAG TRANSFER INSTRUCTIONS LAHF,SAHF,PUSHF,POPF I/O TRANSFER INSTRUCTIONS IN,OUT SIGN EXTENSION INSTRUCTION CBW,CWD PROCESSOR CONTROL INSTRUCTION STC,CLC,CMC,STD,CLD,STI,CLI EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTION: HLT,WAIT,ESC,LOCK,NOP INTERRUPT INSTRUCTIONS: INT,INTO,IRET

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TIMING DIAGRAM

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SUCCESSOR'S

80186 80286

It included features such as clock generator, interrupt controller, timers, wait state generator, DMA channels, and external chip select lines Released in1982. Clock frequency was increased, optimizing in instruction handling. ability to run in protected mode

80386

It was the first 32 bit CPU from 1985, it also introduced a new working mode called virtual besides the real and the protected modes of the 286 which opened for Multitasking The 486 from 1989 runs twice as fast as its predecessor, bus speed was increased, novelty in the 486 is the built in math co-processor

80486

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APPLICATIONS

The first commercial microcomputer built on the basis of the 8086 was the Mycron 2000. One of the most influential microcomputers of all, the IBM PC, used the Intel 8088, a version of the 8086 with an eight-bit data bus (as mentioned above). The first Compaq Deskpro used an 8086 running at 7.14 MHz, but was capable of running add-in cards designed for the 4.77 MHz IBM PC XT. An 8 MHz 8086 was used in the AT&T 6300 PC (built by Olivetti). The IBM PS/2 models 25 and 30 were built with an 8 MHz 8086. The Amstrad PC1512, PC1640, PC2086, PC3086 and PC5086 all used 8086 CPUs at 8 MHz. The NEC PC-9801 also used 8086 at 5 MHz. The Tandy 1000 SL-series machines used 8086 CPUs. The IBM Displaywriter word processing machine and the Wang Professional Computer also used the 8086. NASA used original 8086 CPUs on equipment for ground-based maintenance of the Space Shuttle Discovery until the end of the space shuttle program in 2011.

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INSTRUCTION TIMING

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THANK YOU

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