VLSI Signal Processing

Presented by Suriya T. Skariah Assistant Professor, Department of ECE VLSI DSP, M.TECH, VLSI&ES, SSET SSET

WHY VLSI SIGNAL PROCESSING ?????

Addresses the most important methodologies for designing custom or semi-custom VLSI systems for some typical digital signal processing applications. Learn how to map DSP algorithms into VLSI efficiently.

Several high-level algorithm and architecture design techniques will be introduced that enable joint optimization across the algorithmic, architectural, and circuit domains
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Computational Rates for FIR Filtering

Signal type Speech Music Video Phone Frequency 8 KHz 48 KHz 6.75 KHz Length of h(n) [No. of taps, N] 128 256 81 Performance 2 MOPS 24 MOPS 1090 MOPS

TV
HDTV

27 MHz
144 MHz

81
81

4370 MOPS
23300 MOPS

Processor CISC RISC Signal Processor Supercomputer

Type MC 68040 i 860 MC 56100 CRAY 2

Performance 1.5 MOPS 80 MFLOPS 80 MOPS 1200 MFLOPS

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Course Outline

Module 1

Introduction to VLSI implementations of DSP systems Pipelining & Parallel Processing Retiming, Unfolding & Folding Module 2 Systolic Architecture Design Module 3 Fast Convolution Algorithmic Strength Reduction in Filters & Transforms Pipelined & Parallel Recursive and Adaptive Filters Scaling & Round off Noise Module 4 Bit Level Arithmetic Architectures
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Module 1 Overview
Introduction to VLSI Signal Processing Representation of DSP Algorithms Iteration Bound & Loop Bound Pipelining Parallel Processing

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Typical DSP algorithms

speech recognition sound synthesis echo cancellation noise cancellation image (de-)compression image composition spectral estimation
x(n)

Convolution Correlation Digital Filters FIR IIR

h(n)

y(n) = x(n) * h(n)

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Typical DSP algorithms - FIR Filters

Finite Impulse Response (FIR) filters compute y(n) :

Where x is the input sequence y is the output sequence h is the impulse response (filter coefficients) N is the number of taps (coefficients) in the filter Output sequence depends only on input sequence and impulse response
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Typical DSP algorithms - IIR Filters

Infinite Impulse Response (FIR) filters compute y(n) :

feedback term Output sequence depends on input sequence, impulse response as well as previous outputs

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WHY DIGITAL.??????

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DSP Representations

DSP Algorithms are non-terminating and dataintensive Iteration period: the time for one iteration, one execution of
the loop within DSP algorithm

Sampling rate: number of samples processed / second Latency: time difference between output and corresponding
input (combinational logic = gate delays, sequential logic = number of clock cycles)

The clock rate (or frequency) of the DSP system is not the
same as its sampling rate

Critical path: longest path without delay

- sets bound on clock frequency, i.e. Tclk Tcritical
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DSP Algorithm

Mathematical Formulation

Graphical Representations Block Diagrams Signal Flow graphs

Behavioral Description Languages

Applicative languages eg. Silage Prescriptive languages eg. C, Pascal, Fortan Descriptive languages eg. VHDL , Verilog

Data Flow Graphs

Dependence Graphs

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Graphical DSP Representations

Exhibit all the parallelism (concurrence) and data driven properties (dependence) of the system, as well as provide insight into space and time tradeoffs. Consider a 3-tap FIR filter y(n) = a*x(n) +b*x(n-1) + c*x(n-2) Block Diagram Method Consists of functional blocks connected with
Delay element Multiplier directed edges, which represent data flow from its input block to its output block Data Broadcast Structure a y(n) Adder
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x(n) c

Signal-Flow Graph

A collection of nodes and directed edges Nodes: represent computations and/or task, sum all incoming signals Directed edge (j, k): denotes a linear transformation from the input signal at node j to the output signal at node k Usually used for Linear Time Invariant DSP systems representation Multiplication

z-k = k units delay edge labeled n means multiplication by n

Source node

Adder node
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Sink node

Flow Graph Reversal/ Transposition

Transposed SFG preserves functionality of the system Applicable to single input-single output systems

Steps: 1) Reverse direction of all edges 2) Interchange input and output ports 3) Keep edge gain or delay unchanged
Direct form FIR x(n) y(n) z-1 z-1 c a b c x(n) z-1
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a y(n) z-1 form FIR

Data Flow Graph

x(n)

Nodes represent computations, functions, or tasks & directed edges represents data flow with non-negative number of delays Consider the computation y(n)= a y(n-1) + x(n)
y(n) D
(2)

A - Addition B - Multiplication
(2) , (4) - Denotes execution time with each node

a Block diagram

B DFG
(4)

Iteration period of DFG = 6 units of time

Fine-grain/ atomic DFG : if the nodes in DFG can be as simple as elementary operations like addition, multiplication etc. Coarse-grain DFG : if nodes represent signal processing subtask like filtering etc.
FFT

Adaptive filtering

IFFT

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Data Flow Graph

DFG captures the data-driven property of the DSP algorithm (a node can execute whenever all its input data are available) Each edge describes a precedence constraint between two nodes in DFG a node can execute whenever all its input data are available
Intra-iteration precedence constraint: if no delay b/w nodes
B A A B
(2) 1 1 A

Inter-iteration precedence constraint: if existing one or more delays b/w nodes

Synchronous DFG (SFDG) the number of input and output samples are specified at each node in each execution Eg. Decimator, Expander
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D
1

B
1 (4)

Examples of DFGs
DFGs and Block Diagrams can be used to describe both linear single-rate and nonlinear multi-rate DSP systems Synchronous DFG examples Decimator(down
sampling)

Expander (up sampling)

SDFG for multirate systems

1 A 3 5 B 2 3 C 2

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Conversion of Multi rate DFG to Single rate DFG

3Fa = 5Fb 1 A 3 5 B 2 3 C 2 3Fa = 5Fb 2Fb = 3Fc Fc = 2/5Fa One execution of node A consumes 1 sample & produces 3 output samples
B0 A1 C0 B1

2Fb = 3Fc
A0

A2

A3
B2 A4
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C1

Dependence Graph

Directed graph which shows the dependence of computations in an algorithm Consider a 3 tap FIR filter y(n) = w0x(n) + w1 x(1) + w2 x(2)
x
w

y
w

y = bx + y

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