MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex noninverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC. The
VCC level sets the input signal levels while VDD selects the output
voltage levels.
[Link]
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
Features
UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
3 to 18 Vdc Operation for VDD and VCC
Diode Protected Inputs to VSS
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
These Devices are PbFree and are RoHS Compliant
Parameter
Value
Unit
VCC
DC Supply Voltage Range
0.5 to +18.0
VDD
DC Supply Voltage Range
0.5 to +18.0
Vin
Input Voltage Range
(DC or Transient)
0.5 to +18.0
Vout
Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
Input or Output Current
(DC or Transient) per Pin
10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
Iin, Iout
TA
Ambient Temperature Range
55 to +125
Tstg
Storage Temperature Range
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 7
MC14504BCP
AWLYYWWG
1
16
SOIC16
D SUFFIX
CASE 751B
14504BG
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
16
14
504B
ALYWG
G
1
16
SOEIAJ16
F SUFFIX
CASE 966
MC14504B
ALYWG
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC14504B/D
MC14504B
PIN ASSIGNMENT
VCC
16
VDD
Aout
15
Fout
Ain
14
Fin
Bout
13
MODE
Bin
12
Eout
Cout
11
Ein
Cin
10
Dout
VSS
Din
LOGIC DIAGRAM
VCC
VDD
LEVEL
SHIFTER
INPUT
OUTPUT
TTL/CMOS
MODE SELECT
MODE
Mode Select
Input Logic
Levels
Output Logic
Levels
1 (VCC)
TTL
CMOS
0 (VSS)
CMOS
CMOS
1/6 of package shown.
ORDERING INFORMATION
Package
Shipping
MC14504BCPG
PDIP16
(PbFree)
500 Units / Rail
MC14504BDG
SOIC16
(PbFree)
48 Units / Rail
MC14504BDR2G
SOIC16
(PbFree)
2500 Units / Tape & Reel
MC14504BDTG
TSSOP16*
96 Units / Rail
MC14504BDTR2G
TSSOP16*
2500 Units / Tape & Reel
MC14504BFG
SOEIAJ16
50 Units / Rail
MC14504BFELG
SOEIAJ16
2000 Units / Tape & Reel
Device
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
[Link]
2
MC14504B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
55_C
25_C
125_C
VCC
Vdc
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
5.0
5.0
5.0
10
10
15
10
15
15
0.8
0.8
1.5
1.5
3.0
1.3
1.3
2.25
2.25
4.5
0.8
0.8
1.5
1.5
3.0
0.8
0.8
1.4
1.5
2.9
5.0
5.0
5.0
5.0
10
10
15
10
15
15
2.0
2.0
3.6
3.6
7.1
2.0
2.0
3.5
3.5
7.0
1.5
1.5
2.75
2.75
5.5
2.0
2.0
3.5
3.5
7.0
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
mAdc
Input Capacitance (Vin = 0)
Cin
5.0
7.5
pF
IDD or
ICC
5.0
10
15
0.05
0.10
0.20
0.0005
0.0010
0.0015
0.05
0.10
0.20
1.5
3.0
6.0
mAdc
Quiescent Current
(Per Package)
TTLCMOS Mode
IDD
5.0
5.0
5.0
5.0
10
15
0.5
1.0
2.0
0.0005
0.0010
0.0015
0.5
1.0
2.0
3.8
7.5
15
mAdc
Quiescent Current
(Per Package)
TTLCMOS Mode
ICC
5.0
5.0
5.0
5.0
10
15
5.0
5.0
5.0
2.5
2.5
2.5
5.0
5.0
5.0
6.0
6.0
6.0
mAdc
Characteristic
Output Voltage
Vin = 0 V
Vin = VCC
Symbol
0 Level
1 Level
Input Voltage
0 Level
(VOL = 1.0 Vdc) TTLCMOS
(VOL = 1.5 Vdc) TTLCMOS
(VOL = 1.0 Vdc) CMOSCMOS
(VOL = 1.5 Vdc) CMOSCMOS
(VOL = 1.5 Vdc) CMOSCMOS
VIL
Input Voltage
1 Level
(VOH = 9.0 Vdc) TTLCMOS
(VOH = 13.5 Vdc) TTLCMOS
(VOH = 9.0 Vdc) CMOSCMOS
(VOH = 13.5 Vdc) CMOSCMOS
(VOH = 13.5 Vdc) CMOSCMOS
VIH
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Quiescent Current
(Per Package)
CMOSCMOS Mode
Source
Sink
2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
[Link]
3
Vdc
Vdc
mAdc
MC14504B
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
Propagation Delay, High to Low
Symbol
Shifting Mode
VCC
Vdc
VDD
Vdc
Min
Limits
Typ
(Note 3)
Max
Unit
tPHL
TTL CMOS
VDD > VCC
5.0
5.0
10
15
140
140
280
280
ns
CMOS CMOS
VDD > VCC
5.0
5.0
10
10
15
15
5.0
5.0
10
15
15
5.0
5.0
10
10
15
120
120
70
185
185
175
170
160
240
240
140
370
370
350
340
320
5.0
5.0
10
10
15
15
10
15
15
5.0
5.0
10
5.0
10
15
170
170
100
275
275
145
100
50
40
340
340
200
550
550
290
200
100
80
CMOS CMOS
VCC > VDD
Propagation Delay, Low to High
tPLH
TTL CMOS
VDD > VCC
CMOS CMOS
VDD > VCC
CMOS CMOS
VCC > VDD
Output Rise and Fall Time
tTLH, tTHL
ALL
ns
ns
3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
7
6
VCC = 10 V
5
4
3
VCC = 5 V
2
1
6
5
4
3
2
1
0
0
10
15
VDD, SUPPLY VOLTAGE (Vdc)
20
Figure 1. Input Switchpoint CMOS to CMOS Mode
20
20
15
10
10
15
VDD, SUPPLY VOLTAGE (Vdc)
20
Figure 2. Input Switchpoint TTL to CMOS Mode
VDD, SUPPLY VOLTAGE (Vdc)
VDD, SUPPLY VOLTAGE (Vdc)
VCC = 5 V
15
10
0
0
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
Figure 3. Operating Boundary CMOS to CMOS Mode
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
Figure 4. Operating Boundary TTL to CMOS Mode
[Link]
4
MC14504B
PACKAGE DIMENSIONS
PDIP16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
16
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
T
SEATING
PLANE
16 PL
0.25 (0.010)
T A
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOEIAJ16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96601
ISSUE A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
Q1
E HE
1
M_
L
DETAIL P
D
VIEW P
A1
b
0.13 (0.005)
0.10 (0.004)
[Link]
5
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.031
MC14504B
PACKAGE DIMENSIONS
TSSOP16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
K1
2X
L/2
16
J1
B
U
SECTION NN
J
PIN 1
IDENT.
0.25 (0.010)
M
0.15 (0.006) T U
A
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
N
F
DETAIL E
W
C
0.10 (0.004)
T SEATING
PLANE
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
[Link]
6
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC14504B
PACKAGE DIMENSIONS
SOIC16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE K
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
B
1
8 PL
0.25 (0.010)
X 45 _
C
T
SEATING
PLANE
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
T B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
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Phone: 81357733850
[Link]
7
ON Semiconductor Website: [Link]
Order Literature: [Link]
For additional information, please contact your local
Sales Representative
MC14504B/D
