http://www.anne-gert.nl/techcorner/asm/mnemonic.
txt
MNEMONICS 8086/8088/80186/80188/8087/V30/V20
assembly form : examples
opcode [type ptr] [register],[address/reg] MOV AX,1234 INC BYTE PTR [BP] MOV AH,AL
machine code : xxxxxxxx[xxxxxxxx]|[mdxxxr/m]|[xxxxxxxx[xxxxxxxx]]|[xxxxxxxx[xxxxxxxx]] opcode 1 / 2 bytes|mdr/m byte| disp 1 / 2 bytes |imm. data 1 / 2 bytes
ADDRESS MODES
(mdxxxr/m
byte)
effective address (EA) DS:[BX+SI] DS:[BX+DI] SS:[BP+SI] SS:[BP+DI] DS:[SI] DS:[DI] DS:disp16 DS:[BX] DS:[BX+SI+disp8] DS:[BX+DI+disp8] SS:[BP+SI+disp8] SS:[BP+DI+disp8] DS:[SI+disp8] DS:[DI+disp8] SS:[BP+disp8] DS:[BX+disp8] DS:[BX+SI+disp16] DS:[BX+DI+disp16] SS:[BP+SI+disp16] SS:[BP+DI+disp16] DS:[SI+disp16] DS:[DI+disp16] SS:[BP+disp16] DS:[BX+disp16] register
mdxxxr/m 00xxx000 00xxx001 00xxx010 00xxx011 00xxx100 00xxx101 00xxx110 00xxx111 01xxx000 01xxx001 01xxx010 01xxx011 01xxx100 01xxx101 01xxx110 01xxx111 10xxx000 10xxx001 10xxx010 10xxx011 10xxx100 10xxx101 10xxx110 10xxx111 11xxxreg
REGISTERS
(reg or sr bits)
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register
8bit AL CL DL BL AH CH DH BH
16bit AX CX DX BX SP BP SI DI
reg 000 001 010 011 100 101 110 111
segment register
16bit ES CS SS DS
sr 00 01 10 11
ADDRESSING MODES mode register immediate direct reg. indirect based in the instruction in a register in memory example ,BX ,FFH ,[FFH] ,[BX] ,[BX+FFH]
register address----operand operand memory address---------------------operand register address----mem. address---operand register address----mem. address-+-operand displacement---------------------^ register address----displacement-+-operand mem. address---------------------^ register address----mem. address-v register address----displacement-+-operand displacement---------------------^ mem. address---operand mem. address---destination port address port address
indexed
,[SI+FFH]
based indexed
,[BX+SI+FFH]
string operand
I/O port dir. I/O port indir.
,20H ,DX
DATA TRANSFER MOV move data register/mem. to/from register immediate to reg./mem. immediate to register mem. to accu (AX/AL) accu to mem. (AX/AL)
100010dw 1100011w 1011wreg 1010000w 1010001w
mdregr/m md000r/m data8/16bit data8/16bit address16bit address16bit
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XCHG
PUSH
PUSHA POP
POPA IN
OUT
XLAT LEA LDS LES LAHF SAHF PUSHF POPF
reg./mem. to segm. reg. segm. reg. to reg./mem. exchange register/memory with register register with accu (AX) push register/memory register segment register immediate push all AX,CX,DX,BX,SP,BP,SI,DI pop register/memory register segment register pop all, except SP, (skipping) DI,SI,BP,xx,BX,DX,CX,AX input from I/O port fixed port variable port in DX output to I/O port fixed port variable port in DX translate byte to AL (AL = [BX + AL]) load EA to register load pointer to DS load pointer to ES load AH with flags (O,D,I,S,Z,A,P,C) store AH into flags (O,D,I,S,Z,A,P,C) push flags pop flags
10001110 10001100 1000011w 10010reg 11111111 01010reg 000sr110 011010s0 01100000 10001111 01011reg 000sr111 01100001 1110010w 1110110w 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101
md0srr/m md0srr/m mdregr/m
md110r/m
data8/16bit
* *
md000r/m
* port8bit
port8bit
mdregr/m mdregr/m mdregr/m
ARITHMETIC ADD add reg./mem. with reg. to either imm. to reg./mem. imm. to accu. (AX/AL) add with carry reg./mem. with reg. to either imm. to reg./mem. imm. to accu. (AX/AL) increment register/memory
000000dw 100000sw 0000010w 000100dw 100000sw 0001010w 1111111w
mdregr/m md000r/m data8/16bit data8/16bit mdregr/m md010r/m data8/16bit data8/16bit md000r/m
ADC
INC
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AAA DAA SUB
SBB
DEC
AAS DAS MUL IMUL
AAM DIV IDIV AAD CBW CWD NEG CMP
register ASCII adjust for add decimal adjust for add subtract reg./mem. and reg. to either imm. from reg./mem. imm. from accu. (AX/AL) subtract with borrow reg./mem. and reg. to either imm. from reg./mem. imm. from accu. (AX/AL) decrement register/memory register ASCII adjust for subtract decimal adjust for subtract multiply (unsigned) integer multiply (signed) register/memory immediate ASCII adjust for multiply divide (unsigned) integer divide (signed) ASCII adjust for divide convert byte to word AL in AX convert word to double word (AX in DX : AX) change sign compare reg./mem. and register imm. with reg./mem. imm. with accu. (AX/AL)
01000reg 00110111 00100111 001010dw 100000sw 0010110w 000110dw 100000sw 0001110w 1111111w 01001reg 00111111 00101111 1111011w 1111011w 011010s1 11010100 1111011w 1111011w 11010101 10011000 10011001 1111011w 001110dw 100000sw 0011110w mdregr/m md101r/m data8/16bit data8/16bit mdregr/m md011r/m data8/16bit data8/16bit md001r/m
md100r/m md101r/m mdregr/m 00001010 md110r/m md111r/m 00001010
data8/16bit
md011r/m mdregr/m md111r/m data8/16bit data8/16bit
LOGIC AND and reg./mem. with reg. to either imm. to reg./mem. imm. to accu. (AX/AL) or reg./mem. with reg. to either imm. to reg./mem. imm. to accu. (AX/AL) exclusive or reg./mem. with reg. to either imm. to reg./mem. imm. to accu. (AX/AL) invert
001000dw 100000sw 0010010w 000010dw 100000sw 0000110w 001100dw 100000sw 0011010w 1111011w
mdregr/m md100r/m data8/16bit data8/16bit mdregr/m md001r/m data8/16bit data8/16bit mdregr/m md110r/m data8/16bit data8/16bit md010r/m
OR
XOR
NOT
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SHL
SHR
ROL
ROR
SAL
SAR
RCL
RCR
TEST
shift logical left (SAL) register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w shift logical right register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w rotate left register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w rotate right register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w shift arithmetic left (SHL) register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w shift arithmeric right register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w rotate through carry left register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w rotate through carry right register/memory by 1 1101000w register/memory by CX 1101001w register/memory by count 1100000w and function to flags (no result) reg./mem. and register 1000010w imm. data and reg./mem. 1111011w imm. data and accu. (AX/AL) 1010100w
md100r/m md100r/m md100r/m md101r/m md101r/m md101r/m md000r/m md000r/m md000r/m md001r/m md001r/m md001r/m md100r/m md100r/m md100r/m md111r/m md111r/m md111r/m md010r/m md010r/m md010r/m md011r/m md011r/m md011r/m
count8bit
count8bit
count8bit
count8bit
count8bit
count8bit
count8bit
count8bit
mdregr/m md000r/m data8/16bit data8/16bit
STRING MANIPULATION DS:SI = source, ES:DI = destination, CX = rep. count direction flag = direction set = decrement SI/DI clear = increment SI/DI REP REPZ REPNZ REPE REPNE MOVSB repeat next string oper. repeat for zero (REPE) repeat for not zero (REPNE) repeat for equal (REPZ) repeat for not equal (REPNZ) move byte(s) 1111001z 11110011 11110010 11110011 11110010 10100100
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MOVSW CMPSB CMPSW SCASB SCASW LODSB LODSW STOSB STOSW INSB INSW OUTSB OUTSW
move word(s) compare byte(s) compare word(s) scan byte(s) scan word(s) load byte(s) to AL load word(s) to AX store byte(s) from AL store word(s) from AX input byte(s) from DX port input word(s) from DX port output byte(s) to DX port output word(s) to DX port
10100101 10100110 10100111 10101110 10101111 10101100 10101101 10101010 10101011 01101100 01101101 01101110 01101111
* * * *
CONTROL TRANSFER CALL call to subroutine direct within segment indirect within segment direct intersegment indirect intersegment unconditional jump direct within segment direct within segment-short indirect within segment direct intersegment indirect intersegment return from call in segment adding immediate to SP (level) return intersegment adding immediate to SP (level) jump on not below or equal (JA) jump on above or equ. (JNB/JNC) jump on above (JNBE) jump on CX zero jump on not below (JAE/JNC) jump on below or equal (JNA) jump on below (JNAE/JC) jump on no carry (JNB/JAE) jump on carry (JB/JNAE) jump on not ab. or equ. (JB/JC) jump on not above (JBE) jump on zero (JE) jump on equal (JZ) jump on greater or equal (JNL) jump on greater (JNLE) jump on not less or equal (JG) jump on not less (JGE)
11101000 11111111 10011010 11111111 11101001 11101011 11111111 11101010 11111111 11000011 11000010 11001011 11001010 01110111 01110011 01110111 11100011 01110011 01110110 01110010 01110011 01110010 01110010 01110110 01110100 01110100 01111101 01111111 01111111 01111101
disp16bit md010r/m offset:seg32bit md011r/m disp16bit disp8bit md100r/m offset:seg32bit md101r/m data16bit data16bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit
JMP
RET RETF JNBE JAE JA JCXZ JNB JBE JB JNC JC JNAE JNA JZ JE JGE JG JNLE JNL
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JLE JL JNGE JNG JNZ JNE JPE JPO JNP JNS JNO JO JS JP LOOP LOOPNZ LOOPZ LOOPNE LOOPE ENTER LEAVE INT
INTO IRET
jump on less or equal (JNG) jump on less (JNGE) jump on not great. or equ. (JL) jump on not greater (JLE) jump on not zero (JNE) jump on not equal (JNZ) jump on parity even (JP) jump on parity odd (JNP) jump on not parity (JPO) jump on not sign jump on not overflow jomp on overflow jump on sign jump on parity (JPE) loop CX times loop while not zero (LOOPNE) loop while zero (LOOPE) loop while not equal (LOOPNZ) loop while equal (LOOPZ) enter procedure leave procedure interrupt type specified type 3 interrupt on overflow interrupt return
01111110 01111100 01111100 01111110 01110101 01110101 01111010 01111011 01111011 01111001 01110001 01110000 01111000 01111010 11100010 11100000 11100001 11100000 11100001 11001000 11001001 11001101 11001100 11001110 11001111
disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit disp8bit data16bit level8bit
* *
type8bit
PROCESSOR CONTROL CLC STC CMC CLD STD CLI STI ESC HLT LOCK NOP WAIT clear carry set carry complement carry clear direction set direction clear interrupt set interrupt escape (to external device) halt bus lock prefix (no external bus no operation wait till test pin is low 11111000 11111001 11110101 11111100 11111101 11111010 11111011 11011xxx mdxxxr/m 11110100 request allow. on next instr.) 11110000 10010000 10011011
SEGMENT CONTROL ES: CS: segment override prefix ES segment override prefix CS
001sr110 00100110 00101110
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SS: DS:
segment override prefix SS segment override prefix DS
00110110 00111110
SPECIAL BITS d direction from/to 0 from register 1 to register word/byte 0 8bit data/reg. instruction 1 16bit data/reg. instruction sign extended 8bit or 16bit, w = 1 0 16bit data 1 8bit sign extended to 16bit uses for string primitives for comparison with ZF flag (zero) is don't care, uses with external device (8087)
z x
SEGMENT REGISTERS sr segment register 00 ES 01 CS 10 SS 11 DS
POSTBYTE md
(mdregr/m)
r/m
reg
mode 00 if r/m = 110 then EA = disp16bit, else disp = 0 (no disp) 01 disp is 8bit, sign extended to 16bit 10 disp is 16bit 11 r/m is a reg field disp follows 2nd byte of instruction (before data if required) register/memory 000 EA = (BX)+(SI)+disp / AX / AL 001 EA = (BX)+(DI)+disp / CX / CL 010 EA = (BP)+(SI)+disp / DX / DL 011 EA = (BP)+(DI)+disp / BX / BL 100 EA = (SI)+disp / SP / AH 101 EA = (DI)+disp / BP / CH 110 EA = (BP)+disp / SI / DH when md = 00, EA = disp16bit 111 EA = (BX)+disp / DI / BH disp follows 2nd byte of instruction (before data if required) register 8/16bits 000 AL / AX 001 CL / CX
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010 011 100 101 110 111
DL BL AH CH DH BH
/ / / / / /
DX BX SP BP SI DI
* is extended opcodes, not available in 8086/8088 only on V20/V30/80188/80186 and upper
procedure protocol : ENTER data,level
: data is number of bytes to reserve on the stack level is nesting depth 1 = top, 0 = no nesting push BP on the stack, move SP in BP, look at level, if level is not zero then push level-1 words on the stack from old BP value address down, then push BP if level > 0. Finally subtract data from SP:
SP stack BP stack SP after->| | | | |------| | | : undef } data value | | |------| | | (SP/2)->|BP aft|>-when level > 0 | | |------| |------| :BP xxx:<-------------------<:BP xxx } level value -1 |------| |------| (SP/1)-BP after->|BP bef| BP before->|BP xxx| |------| |------| high mem. SP before->| | | | |------| | | low mem. SP/BP before is value before ENTER opcode SP/BP after is value after ENTER opcode SP/1 is SP after when level and data is 0 SP/2 is SP after when data is 0 and level > 0 BP xxx is stack pointers from prev. procedure(s) LEAVE : move BP to SP, pop BP ; MOV SP,BP POP BP
FLOATING POINT
(8087)
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DATA TRANSFER FLD load and push int./real mem. to ST(0) temp real mem to ST(0) (80bit) ST(i) to ST(0) load integer memory to ST(0) and short integer (32bit) long integer (64bit) load BCD memory to ST(0) (80b.) store ST(0) to int./real mem. ST(0) to ST(i) store in short integer (32bit) store and pop ST(0) to int./real mem. ST(0) to temp real mem (80bit) ST(0) to ST(i) store and pop ST(0) to int. mem. short integer (32bit) long integer (64bit) store and pop to BCD mem (80b.) exchange ST(i) and ST(0)
FILD
FBLD FST
11011mf1 11011011 11011001 push 11011101 11011111 11011111 11011mf1 11011101 11011011 11011mf1 11011011 11011101 11011011 11011111 11011111 11011001
md000r/m md101r/m 11000sti md000r/m md101r/m md100r/m md010r/m 11010sti md010r/m md011r/m md111r/m 11011sti md011r/m md111r/m md110r/m 11001sti
FIST FSTP
FISTP
FBSTP FXCH
COMPARISON FCOM compare int./real mem. to ST(0) ST(i) to ST(0) compare short int. to ST(0) compare and pop int./real mem. to ST(0) ST(i) to ST(0) compare and pop short integer comp.ST(1) to ST(0) pop twice test ST(0) examine ST(0)
FICOM FCOMP
11011mf0 11011000 11011010 11011mf0 11011000 11011010 11011110 11011001 11011001
md010r/m 11010sti md010r/m md011r/m 11011sti md011r/m 11011001 11100100 11100101
FICOMP FCOMPP FTST FXAM
CONSTANTS FLDZ FLD1 FLDPI FLDL2T FLDL2E FLDLG2 load load load load load load 0.0 into ST(0) 1.0 into ST(0) pi into ST(0) log2 10 into ST(0) log2 e into ST(0) log10 2 into ST(0) 11011001 11011001 11011001 11011001 11011001 11011001 11101110 11101000 11101011 11101001 11101010 11101100
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FLDLN2
load loge 2 into ST(0)
11011001
11101101
ARITHMETIC FADD addition int./real mem. with ST(0) ST(i) and ST(0) FIADD add short integer to ST(0) FADDP add and pop ST(0) ST(i) FSUB subtract ST(0) - [ST(i)/mem.] int./real mem. with ST(0) ST(i) and ST(0) FISUB subtract ST(0) - short integer FSUBP subtract ST(0) - ST(i) and pop FSUBR subtract [ST(i)/mem.] - ST(0) int./real mem. with ST(0) ST(i) and ST(0) FISUBR subtract short integer - ST(0) FSUBRP subtract ST(i) - ST(0) and pop FMUL multiplication int./real mem. with ST(0) ST(i) and ST(0) FIMUL mult. ST(0) * short integer FMULP mult. and pop ST(0) * ST(i) FDIV divide ST(0) / [ST(i)/mem.] int./real mem. with ST(0) ST(i) and ST(0) FIDIV div. ST(0) / short integer FDIVP divide ST(0) / ST(i) and pop FDIVR divide [ST(i)/mem.] / ST(0) int./real mem. with ST(0) ST(i) and ST(0) FIDIVR div. short integer / ST(0) FDIVRP divide ST(i) / ST(0) and pop FSQRT ST(0)=square root of ST(0) FSCALE scale ST(0) by ST(1) FPREM part. remainder of ST(0)/ST(1) FRNDINT round ST(0) to integer FXTRACT extract components of ST(0) FABS absolute value of ST(0) FCHS change sign of ST(0)
11011mf0 11011d00 11011010 11011d10 11011mf0 11011d00 11011010 11011d10 11011mf0 11011100 11011010 11011110 11011mf0 11011d00 11011010 11011d10 11011mf0 11011d00 11011010 11011d10 11011mf0 11011100 11011010 11011110 11011001 11011001 11011001 11011001 11011001 11011001 11011001
md000r/m 11000sti md000r/m 11000sti md101r/m 11101sti md101r/m 11101sti md100r/m 11100sti md100r/m 11100sti md001r/m 11001sti md001r/m 11001sti md111r/m 11111sti md111r/m 11111sti md110r/m 11110sti md110r/m 11110sti 11111010 11111101 11111000 11111100 11110100 11100001 11100000
TRANSCENDENTAL FPTAN FPATAN F2XM1 ST(0)=partial tangent of ST(0) partial tangent of ST(0)/ST(1) ST(0)=2^ST(0)-1 11011001 11011001 11011001 11110010 11110011 11110000
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FYL2X ST(0)=ST(1)*log2(|ST(0)|) FYL2XP1 ST(0)=ST(1)*log2(|ST(0)+1|)
11011001 11011001
11110001 11111001
PROCESSOR CONTROL FINIT FENI FDISI FLDCW FSTCW FSTSW FCLEX FSTENV FLDENV FSAVE FRSTOR FINCSTP FDECSTP FFREE FNOP FWAIT initialize 8087 enable interrupts from 8087 disable interrupts from 8087 load control word store control word store status word clear exeptions (int) store environment load environment save state restore state increment stackpointer decrement stackpointer free ST(i) no operation CPU wait for 8087 (WAIT) 11011011 11011011 11011011 11011001 11011001 11011101 11011011 11011001 11011001 11011101 11011101 11011001 11011001 11011101 11011001 10011011 11100011 11100000 11100001 md101r/m md111r/m md111r/m 11100010 md110r/m md100r/m md110r/m md100r/m 11110111 11110110 11000sti 11010000
SPECIAL BITS d destination 0 destination is ST(0) 1 destination is ST(i) memory format 00 32bit real (short real) 01 32bit integer (short integer) (FI) 10 64bit real (long real) 11 16bit integer (word integer) sti'th register below stack top
mf
sti
POSTBYTE md
(mdxxxr/m)
r/m
mode 00 if r/m = 110 then EA = disp16bit, else disp = 0 (no disp) 01 disp is 8bit, sign extended to 16bit 10 disp is 16bit 11 r/m is a reg field disp follows 2nd byte of instruction (before data if required) register/memory 000 EA = (BX)+(SI)+disp / ST(i) 001 EA = (BX)+(DI)+disp / ST(i) 010 EA = (BP)+(SI)+disp / ST(i)
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011 100 101 110 111
EA = EA = EA = EA = EA = disp
(BP)+(DI)+disp / ST(i) (SI)+disp / ST(i) (DI)+disp / ST(i) (BP)+disp / ST(i) when md = 00 EA = disp16bit (BX)+disp / ST(i) follows 2nd byte of instruction (before data if required)
ST(0) ST(i)
is current stack top is i'th register below stack top
ASSEMBLY PSEUDO OPCODES DB DW ; inline bytes 8bit inline words 16bit comment line
ASSEMBLER DATA TYPE PREFIX BYTE PTR WORD PTR DWORD PTR QWORD PTR TBYTE PTR
(after opcode mnem.)
byte (8bit) word / word integer (16bit) double word / short integer / short real (32bit) quad word / long integer / long real (64bit) ten byte / packed BCD / temporary real (80bit)
DATA TYPES
bits
|7 0| |15 8|7 0| |31 24|23 16|15 8|7 0| |63 56|55 48|47 40|39 32|31 |79 72|71 64|63 56|55 48|47 |7 0|7 0|7 0|7 0|7 byte | | | | | - MAG. | | | signed byte | | | | -S-MAG | | | word | | | | | - MAGNITUDE | | signed word / word integer | | -S-MAGNITUDE | | pointer | | | | - SELECTOR OFFSET short integer / double word | |
24|23 40|39 0|7 | | | | | | | | | | |
16|15 32|31 0|7 | | | | | | | | | | |
8|7 24|23 0|7 | | | | | | | | | | |
0| 16|15 0|7 | | | | | | | | | | |
8|7 0|7 | | | | | | | | | | |
0| 0| | | | | | | | | | | |
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-SMAGNITUDE | | short real 23|24 | | | | | -S- EXP - MAGNITUDE | | long integer / quad word | | | | -SMAGNITUDE long real | 52|53| | | | | -S-EXPONENTMAGNITUDE temporary real | | | | -S- EXPONENT -IMAGNITUDE packed BCD 18 digits | | | | -S--D17-D16/152 DIGITS PER BYTE string | | | | | | | -ASCII ANY NUMBER OF BYTES .........
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | | | | -D1/D0 | |
S is sign bit; I is int. bit of significant, implicit in short and long real packed BCD: (-1)^S (D17...D0) real: (-1)^S (2^(EXP-bias)) (F0F1...) exponent bias (normalized values): short real: 127 (7FH) long real: 1023 (3FFH) temporary real: 16383 (3FFFH)
REGISTERS 8086/8088/80186/80188/8087/V30/V20 bits accumulator base count data stack pointer base pointer source index destination index instruction pointer status flags code segment data segment stack segment extra segment 15 | - AH - BH - CH - DH | | | 8 7 | | -AX-BX-CX-DX| | SP BP SI DI | | IP F | | CS DS SS ES 0 | | | | -
AL BL CL DL
}--}---| | | | }-- | | | | | }-- | | }----
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real address is : segment |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| offset |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| _____________________________________________________________ sum + 20 bit addr |19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
FLAGS
|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -xx-xx-xx-xx-OF-DF-IF-TF-SF-ZF-xx-AF-xx-PF-xx-CFoverflow flag - set if result is too large direction flag for string instructions incr. when clear interrupt enable flag, when set int. transfer control to vector trace flag, when set a single step int. occurs after next instr. sign flag - set equal to high orderbit of result zero flag - set if result is zero aux. carry - set on carry or borrow to the low fourbits of AL parity flag - set if low 8bits of result is even num. of bits carry flag - set on highbit carry or borrow
OF DF IF TF SF ZF AF PF CF
FLOATING POINT REGISTERS bits storage
8087 |1 0| -tag field-
| 79 | 78 64 | 63 0| -sign- exponent - significand-
8 float registers ST(0) - ST(7) with stack access all values are internally stored as temp. real (80bits) + tag (2bits) converting is done when values are loaded/stored CONTROL control register status register tag word |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -xx-xx-xx-IC- RC - PC -M -xx-PM-UM-OM-ZM-DM-IM-B -C3- TOP -C2-C1-C0-IR-xx-PE-UE-OE-ZE-DE-IE-TAG7 -TAG6 -TAG5 -TAG4 -TAG3 -TAG2 -TAG1 -TAG0 -
control register IC infinity control RC rounding control
PC
M xM PM OM
0 - projective 1 - affine 00 - round to nearest or even 01 - round down (toward -inf.) 10 - round up (toward +inf.) 11 - chop (truncate toward zero) precision control 00 - 24 bits 10 - 53 bits 11 - 64 bits interrupt mask 1 - int. are masked exeption masks 1 - exeption is masked precision underflow
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ZM DM IM
zero divide denormalized operand invalid operation
status register B neu busy TOP top of stack pointer ST(0) is ST(TOP) C0-C3 condition code IR interrupt request xE exeption flags 1 - exeption has occurred PE precision UE underflow OE overflow ZE zero divide DE denormalized operand IE invalid operation tag word values TAGx 00 - valid 01 - zero 10 - special 11 - empty condition codes C3 C2 compare, test 0 0 0 0 1 0 1 1 remainder Q1 0 x 1 examine 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 INSTRUCTION POINTER C1 x x x x Q0 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 Q2 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ST > source or 0 (FTST) ST < source or 0 (FTST) ST = source or 0 (FTST) ST is not comparable complete reduc. with 3 low bits of quotient incomplete reduction valid, positive, unnormalized invalid, positive, exponent = 0 valid, negative, unnormalized invalid, negative, exponent = 0 valid, positive, normalized infinity, positive valid, negative, normalized infinity, negative zero, positive empty zero, negative empty invalid, positive, exponent = 0 empty invalid, negative, exponent = 0 empty last used or current IP (debug)
20bits
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DATA POINTER
20bits
last used or current DP (debug)
environment image in memory (FSTENV,FLDENV) (debug) offset 15 12|11 +0 CONTROL WORD +2 STATUS WORD +4 TAG WORD +6 INSTRUCTION POINTER (15-0) +8 -INSTRUCT POINT. (19-16) -0 - OPCODE (10-0) +10 DATA POINTER (15-0) +12 - DATA POINTER (19-16) 0
0 -
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