INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT165 8-bit parallel-in/serial-out shift register

Product specication File under Integrated Circuits, IC06 December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

FEATURES Asynchronous 8-bit parallel load Synchronous serial input Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously.

74HC/HCT165

When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated. APPLICATIONS Parallel-to-serial data conversion

QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Q7, Q7 PL to Q7, Q7 D7 to Q7, Q7 maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 16 15 11 56 3.5 35 14 17 11 48 3.5 35 ns ns ns MHz pF pF HCT UNIT

fmax CI CPD Notes

1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL VCC2 fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC 1.5 V ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

PIN DESCRIPTION PIN NO. 1 7 9 2 8 10 11, 12, 13, 14, 3, 4, 5, 6 15 16 SYMBOL PL Q7 Q7 CP GND Ds D0 to D7 CE VCC NAME AND FUNCTION asynchronous parallel load input (active LOW) complementary output from the last stage serial output from the last stage clock input (LOW-to-HIGH edge-triggered) ground (0 V) serial data input parallel data inputs clock enable input (active LOW) positive supply voltage

74HC/HCT165

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

74HC/HCT165

Fig.4 Functional diagram.

FUNCTION TABLE OPERATING MODES PL parallel load L L H H H X X L L H CE X X X INPUTS CP X X l h X DS L H X X X D0-D7 L H L H q0 Qn REGISTERS Q0 Q1-Q6 L-L H-H q0-q5 q0-q5 q1-q6 L H q6 q6 q7 OUTPUTS Q7 H L q6 q6 q7 Q7

serial shift hold do nothing Note

1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = dont care = LOW-to-HIGH clock transition

Fig.5 Logic diagram.

December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay CE, CP to Q7, Q7 propagation delay PL to Q7, Q7 propagation delay D7 to Q7, Q7 output transition time clock pulse width HIGH or LOW parallel load pulse width; LOW removal time PL to CP, CE set-up time Ds to CP, CE set-up time CE to CP; CP to CE set-up time Dn to PL 80 16 14 80 16 14 100 20 17 80 16 14 80 16 14 80 16 14 +25 typ. 52 19 15 50 18 14 36 13 10 19 7 6 17 6 5 14 5 4 22 8 6 11 4 3 17 6 5 22 8 6 max. 165 33 28 165 33 28 120 24 20 75 15 13 100 20 17 100 20 17 125 25 21 100 20 17 100 20 17 100 20 17 40 to +85 min. max. 205 41 35 205 41 35 150 30 26 95 19 16 120 24 20 120 24 20 150 30 26 120 24 20 120 24 20 120 24 20 40 to +125 min. max. 250 50 43 250 50 43 180 36 31 110 22 19 ns UNIT

74HC/HCT165

TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6

tPHL/ tPLH

ns

Fig.6

tPHL/ tPLH

ns

Fig.6

tTHL/ tTLH

ns

Fig.6

tW

ns

Fig.6

tW

ns

Fig.6

trem

ns

Fig.6

tsu

ns

Fig.6

tsu

ns

Fig.6

tsu

ns

Fig.6

December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

Tamb (C) 74HC SYMBOL PARAMETER min. th hold time Ds to CP, CE Dn to PL hold time CE to CP CP to CE maximum clock pulse frequency 5 5 5 5 5 5 6 30 35 +25 typ. 6 2 2 17 6 5 17 51 61 max. 40 to +85 min. 5 5 5 5 5 5 5 24 28 max. 40 to +125 min. 5 5 5 5 5 5 4 20 24 max. ns UNIT

74HC/HCT165

TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6

th

ns

Fig.6

fmax

MHz

Fig.6

December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: MSI Note to HCT types

74HC/HCT165

The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT Dn Ds CP CE PL

UNIT LOAD COEFFICIENT 0.35 0.35 0.65 0.65 0.65

December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tW trem tsu tsu tsu th th fmax propagation delay CE, CP to Q7, Q7 propagation delay PL to Q7, Q7 propagation delay D7 to Q7, Q7 output transition time clock pulse width HIGH or LOW parallel load pulse width; LOW removal time PL to CP, CE set-up time Ds to CP, CE set-up time CE to CP; CP to CE set-up time Dn to PL hold time Ds to CP, CE; Dn to PL hold time CE to CP, CP to CE maximum clock pulse frequency 16 20 20 20 20 20 7 0 26 +25 typ. 17 20 14 7 6 9 8 2 7 10 1 7 44 40 to +85 40 to +125

74HC/HCT165

TEST CONDITIONS WAVEFORMS UNIT V CC (V) ns ns ns ns ns ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6

max. min. max. min. max. 34 40 28 15 20 25 25 25 25 25 9 0 21 43 50 35 19 24 30 30 30 30 30 11 0 17 51 60 42 22

December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

AC WAVEFORMS

74HC/HCT165

The changing to output assumes internal Q6 opposite state from Q7. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.6

Waveforms showing the clock (CP) to output (Q7 or Q7) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.

The changing to output assumes internal Q6 opposite state from Q7. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.7

Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) removal time.

(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.8 Waveforms showing the data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW.

December 1990

Philips Semiconductors

Product specication

8-bit parallel-in/serial-out shift register

74HC/HCT165

CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.9

Waveforms showing the set-up and hold times from the serial data input (Ds) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE).

(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the set-up and hold times from the data inputs (Dn) to the parallel load input (PL).

PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines.

December 1990

10

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