LC-30HV4E: Service Manual
LC-30HV4E: Service Manual
LC-30HV4E
SERVICE MANUAL
LCD COLOUR TELEVISION
MODEL
LC-30HV4E
In the interests of user-safety (Required by safety regulations in some countries) the set should be restored to its original condition and only parts identical to those specified should be used.
CONTENTS
Page IMPORTANT SERVICE SAFETY PRECAUTION ..... 2 SPECIFICATIONS................................................ 3 OPERATION MANUAL ........................................ 4 DIMENSIONS .................................................... 10 REMOVING OF MAJOR PARTS ........................ 12 ADJUSTMENT PROCEDURES (AVC System) .. 19 UPGRADING INSTALLED PROGRAMS ........... 26 ADJUSTMENT PROCEDURES (Display) ......... 29 MAJOR IC INFORMATIONS .............................. 33 TROUBLE SHOOTING TABLE .......................... 52 CHASSIS LAYOUT ............................................. 62 SYSTEM BLOCK DIAGRAM (AVC System) ...... 66 SIGNAL FLOW BLOCK DIAGRAM (AVC System) ..................................................... 68 Page POWER SYSTEM BLOCK DIAGRAM (AVC System) ..................................................... 70 PC I/F BLOCK DIAGRAM (AVC System) .......... 72 SIGNAL BLOCK DIAGRAM (Display) ................ 74 POWER UNIT BLOCK DIAGRAM (Display) ...... 76 OVERALL WIRING DIAGRAM (AVC System) ... 78 OVERALL WIRING DIAGRAM (Display) ............ 82 DESCRIPTION OF SCHEMATIC DIAGRAM ..... 84 WAVEFORMS .................................................... 85 SCHEMATIC DIAGRAM ..................................... 86 PRINTED WIRING BOARD ASSEMBLIES...... 159 PARTS LIST ..................................................... 204 PACKING OF THE SET ................................... 246
SHARP CORPORATION
LC-30HV4E
Service work should be perfomed only by qualified service technicians who are thoroughly familiar with all safety checks and the servicing guidelines which follow:
Use an AC voltmeter having with 5000 ohm per volt, or higher, sensitivity or measure the AC voltage drop across the resisor. Connect the resistor connection to all exposed metal parts having a return to the chassis (antenna, metal cabinet, screw heads, knobs and control shafts, escutcheon, etc.) and measure the AC voltage drop across the resistor. All checks must be repeated with the AC cord plug connection reversed. (If necessary, a nonpolarized adaptor plug must be used only for the purpose of completing these checks.) Any reading of 35V peak (this corresponds to 0.7 milliamp. peak AC.) or more is excessive and indicates a potential shock hazard which must be corrected before returning the monitor to the owner.
WARNING
1. For continued safety, no modification of any circuit should be attempted. 2. Disconnect AC power before servicing. CAUTION: FOR CONTINUED PROTECTION AGAINST A RISK OF FIRE REPLACE ONLY WITH SAME TYPE FUSE. AVC SIDE: F701 (T2A, 250V), F702 (T2A, 250V), F1702 (T4AL, 250V) FUSE. LCD SIDE: F1(T3.15AL, 250V), F6551, F6552, F6553, F6554, F6555, F6556 (T2.5AL, 250V)
DVM AC SCALE
50k ohm 10W
SAFETY NOTICE
Many electrical and mechanical parts in Plasma Display television have special safety-related characteristics. These characteristics are often not evident from visual inspection, nor can protection afforded by them be necessarily increased by using replacement components rated for higher voltage, wattage, etc. Replacement parts which have these special safety characteristics are identified in this manual; electrical components having such features are identified by and shaded areas in the Replacement Parts List and Schematic Diagrams. For continued protection, replacement parts must be identical to those used in the original circuit. The use of a substitute replacement parts which do not have the same safety characteristics as the factory recommended replacement parts shown in this service manual, may create shock, fire or other hazards.
LC-30HV4E
SPECIFICATIONS
Item LCD panel Number of dots Video Colour System TV Function TV-standard (CCIR) Receiving Channel VHF/UHF CATV 30"LCD COLOUR TV, Model:LC-30HV4E 30"Advanced Super View & BLACK TFT LCD 2,949,120 dots (1280 768 3 dots) PAL/SECAM/NTSC 3.58/NTSC 4.43/PAL 60 B/G, D/K, I, L/L E2E69ch, F2F10ch, I21I69ch, IR AIR Jch Hyper-band, S1S41ch Auto Preset 99 ch, Auto Label, Auto Sort NICAM/IGR 430 cd/m2 60,000 hours (at Save1) H : 170 V : 170 10W 2 8 cm AVC Rear System INPUT 1 INPUT 2 INPUT 3 2pcs
TV-Tuning System STEREO/BILINGAL Brightness Backlight Viewing angles Audio amplifier Speakers Terminals
SCART (AV in, RGB in, TV out) SCART (AV in/out, S-VIDEO in, AV Link) SCART (AV in/out, S-VIDEO in, RGB in), Component
ANTENNA 75 Din Type AV OUTPUT DC OUTPUT Front INPUT 4 PC Headphones OSD language Power Requirement AVC System Power Consumption Display Weight AVC System Display Accessories Audio (Variable, Fixed), S-VIDEO out, AV out DC6.5V 7W MAX S-VIDEO, AV in 15 Pin mini D-Sub, Audio in ( 3.5mm jack) 3.5mm jack English/German/French/Italian/Spanish/Dutch/Swedish/Portuguese/Greek/ Finnish/Russian/Turkish AC 220240 V, 50/60 Hz 32 W (0.7 W Standby) 109 W (0.9 W Standby) (Method IEC60107) 5.4 kg (w/o stand), 5.5 kg (with stand) 15.7 kg (w/o stand), 19.5 kg (with stand) Operation manual, Remote control unit ( 1), System cable ( 1), AC cord ( 2), LR6 (AA size) Alkaline battery ( 2), Stand unit ( 1), Cable clamp ( 1)
Part names
AVC System
Front view
PC INPUT terminal (AUDIO) INPUT 4 terminal (VIDEO) Headphone (When connecting headphones, the sound from the speakers is muted.)
LC-30HV4E
Display
STANDBY/ON indicator
* If the AVC System is switched on but it does not appear to be operating correctly, it may need resetting. In this case, press CLEAR, shown in the diagram, lightly with the end of a ballpoint pen or other pointed object. This will reset the System as shown below.
AV MODE resets to STANDARD. TV channel resets to channel 1. Dual screen resets to normal. Audio setting initialises. SRS resets to OFF. Image position is initialised.
OPERATION MANUAL
4
Rear view
ANTENNA INPUT terminal Remote control sensor indicator OPC indicator* AV OUTPUT terminal (S-VIDEO) *OPC: Optical Picture Control (See Pages 36 and 38.) AV OUTPUT terminal (VIDEO)
NOTE Pressing CLEAR will not work if the System is in standby mode (indicator lights red). Pressing CLEAR will not delete channel preset or password. See page 60 for clearing the password when you know it. See page for initialising to the factor y preset values when you forget your password.
RS-232C terminal
OPC sensor
STANDBY/ON indicator AV OUTPUT terminals (AUDIO) INPUT 1 terminal (SCART) INPUT 2 terminal (SCART) DISPLAY OUTPUT2 terminal DC OUTPUT terminal (Terminal for expanded functionality in the near future.) AC INPUT terminal
1
Removing the terminal cover
Display (rear view)
13 14 15 16
(STANDBY/ON) To switch the power on and off. (FREEZE/HOLD for TELETEXT) TV/External input mode: Change the still image mode. TELETEXT mode: Freeze a multi-page on screen while other pages are automatically updated. Press again to return to the normal image. (DUAL screen) Set the dual picture mode. Press again to return to normal view. (See page 61.) (WIDE MODE/ T/B/F) TV/External input mode: Change the wide image mode.
17
Press down the two upper hooks to remove the cover toward you.
1 2 3 4 5 6 7 8 9
2
Connecting the system cable and the AC cord to the Display
18 19
TELETEXT mode: Set the area of magnification. (full/upper half/ lower half) AV MODE Select a video setting: AV MODE (STANDARD, DYNAMIC, MOVIE, GAME, USER), PC MODE (STANDARD, USER) (See page 51.) SOUND Select the sound multiplex mode. (SRS and FOCUS)* Select SRS and FOCUS sound system. (Flashback) Press to return to the previous channel in normal viewing mode. Press to return to the previous page in TELETEXT mode.
10 11 12
20 21 22 23 24
10
AC INPUT 110V240V
25
11
/ (VOLUME) Set the volume. (Reveal hidden for TELETEXT) TELETEXT mode: Display hidden characters. (SUBPAGE for TELETEXT) TELETEXT mode: Change the picture mode for sub-page selecting.
12
13
5
3
CAUTION
MENU Display the MENU screen. (CHANNEL INFORMATION) Display the channel information and time. (GREY) Connect the plug firmly until the hooks on both sides click.
DISPLAY INPUT2
DISPLAY INPUT1
AC cord (WHITE) Connect the plug into the terminal and secure it by tightening the thumb screws. System cable
14
15
16
17
Connecting the system cable and the AC cord to the AVC System
System cable
18
19
(GREY)
(WHITE)
NOTE When using the remote control unit, point it at the Display. * is a trademark of SRS Labs, Inc. FOCUS technology is incorporated under license from SRS Labs, Inc.
20
21
22
23
AC cord
24
25
(INPUT SOURCE) Select an input source. (TV, INPUT 1, INPUT 2, INPUT 3, INPUT 4, PC) SLEEP Set the Sleep timer. (MUTE) Mute the sound. 09 TV/External input mode: Set the channel. TELETEXT mode: Set the page. (Digit for channel select) Change the digits of the selected TV channel. Colour (RED/GREEN/YELLOW/BLUE) TELETEXT mode: Select a page. CH /CH ( / ) TV/External input mode: Select the channel. TELETEXT mode: Set the page. (TOP Overview for TELETEXT) TELETEXT mode: Display an index page for CEEFAX/FLOF information. TOP Overview for TOP programme. (TELETEXT) Select the TELETEXT mode. (all TV image, all TEXT image, TV/TEXT image) RETURN MENU mode: Return to the previous menu screen. ENTER Execute a command. Return to the initial image position after moving with / / / . / / / (Cursor) Select a desired item on the setting screen. Move the picture on the screen.
LC-30HV4E
TO PREVENT RISK OF ELECTRIC SHOCK, DO NOT TOUCH UN-INSULATED PARTS OF ANY CABLES WITH THE AC CORD CONNECTED.
Preparation
Setting the Display on the wall
Using an optional bracket to mount the Display You can ask a qualified service personnel about using an optional AN-37AG1 bracket to mount the Display to the wall. Carefully read the instructions that come with the bracket before beginning work.
Hanging on the wall AN-37AG1 wall mount bracket. (See the bracket instructions for details.)
LC-30HV4E
5
CAUTION
Vertical mounting
Angular mounting
Installing the LCD Colour TV requires special skill that should only be performed by qualified service personnel. Customers should not attempt to do the work themselves. SHARP bears no responsibility for improper mounting or mounting that results in accident or injury.
6
Peel each spacer away from the paper and attach to the four bulging areas on the stand. Stand spacer Bulge Bulge
3
Peel each cushion away from the paper and attach to the four areas at the bottom. Stand cushion Attaching point
Insert the stand into the AVC System, making sure that the thick and thin bulges of the stand align with the big and small holes on the AVC System. Thin bulge
Attaching point
Thick bulge
4
Cables come out from the small opening.
NOTE
When mounting the AVC System vertically, always use the supplied stand. Be careful not to block vent holes when standing up directly on the floor or a flat surface as this can result in equipment failure.
You can connect many types of external equipment to your System, like a decoder, VCR, DVD player, PC, game console and camcorder. To view external source images, select the input source from b on the remote control unit or INPUT on the Display.
Before performing work make sure to turn off the System. Before performing work spread cushioning over a flat surface to lay the Display on. This will prevent it from being damaged.
1 2
Speaker plug
7
Decoder AVC System (front view) Game console/Camcorder
VCR
CAUTION The speaker terminals on the Display is only for the attached speakers. Do not connect any third party plug or speaker to the terminal. Insert the speaker plug completely into the terminal. Do not handle or move the Display by the speakers.
NOTE Perform the same steps for both left and right speakers. To attach the speakers, perform the above steps in reverse order.
PC
CAUTION
To protect all equipment, always turn off the AVC System before connecting to a decoder, VCR, DVD player, PC, game console, camcorder or other external equipment. The S-video signal only outputs when INPUT2 or INPUT3 is selected for Y/C, or when from the INPUT 4 terminal (SVIDEO). Only the S-video signal can output from the INPUT 4 terminal (S-VIDEO).
NOTE
Please refer to the relevant operation manual (DVD player, PC, etc.) carefully before making connections.
LC-30HV4E
Appendix
Response code format Normal response
LC-30HV4E
When a program is set, the display can be controlled from the PC using the RS-232C terminal. The input signal (PC/video) can be selected, the volume can be adjusted and various other adjustments and settings can be made, enabling automatic programmed playing.
Attach an RS-232C cable cross-type (commercially available) to the supplied Din-D/sub RS-232C for the Problem response (communication error or incorrect command)
connections. E R R
Return code (0DH)
NOTE
This operation system should be used by a person who is accustomed to using PC.
Communication conditions Set the RS-232C communications settings on the PC to match the displays communications conditions. The display's communications settings are as follows: Commands
CONTROL ITEM CONTROL ITEM WIDE MODE W I W I W I W I W I W I W I W I W I W I W I W I SRS POWER SETTING INPUT SELECTION A I I I I I INPUT SELECTION B I I I I INPUT3 (CVBS) INPUT3 (Y/C) INPUT3 (RGB) INPUT3 (COMPONENT) TOGGLE STANDARD DYNAMIC MOVIE GAME USER _ * * * * * * V P O S C L C K P H S E * * * * * * * * * * * * * _ _ _ _ _ _ _ VOLUME (0 60) H-POSITION (AV) ( 10 H-POSITION (PC) ( 90 V-POSITION (AV) ( 30 V-POSITION (PC) ( 60 CLOCK ( 90 PHASE ( 20 90) 20) 10) 90) 30) 60) TEXT CHANNEL DUAL SCREEN I I I AV MODE SELECTION A V M D 0 A V M D 1 A V M D 2 A V M D 3 A V M D 4 A V M D 5 VOLUME POSITION H P O S V P O S H P O S V O L M * _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ N P 3 3 _ _ _ N P 3 2 _ _ _ N P 3 1 _ _ _ N P 3 0 _ _ _ N P 2 1 INPUT2 (Y/C) _ _ _ N P 2 0 INPUT2 (CVBS) _ _ _ N P 1 1 INPUT1 (RGB) _ _ _ I N P 1 0 INPUT1 (CVBS) _ _ _ P C D x PC A V D * INPUT1 4 (1 4) _ _ _ T V D * TV (CHANNEL SELCTION) (1 99) * _ _ T V D 0 TV (CHANNEL FIXED) _ _ _ T G D x INPUT SWITCHING (TOGGLE) P O W R 0 POWER OFF (STANDBY) _ _ _ COMMAND PARAMETER CONTROL CONTENTS COMMAND PARAMETER D E 0 D E 1 D E 2 D E 3 D E 4 D E 5 D E 6 D E 7 D E 8 D E 9 _ _ _ _ _ _ _ _ _ _ D E 1 0 D E 1 1 S R S S 0 S R S S 1 S R S S 2 S R S S 3 S R S S 4 T W I T W I N 0 N 1 D C C H * C H U P x C H D W x T E X T 0 T E X T 1 D C P G * _ _ * _ _ * _ _ _ _ _ _ _ _ _ _ * _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
CONTROL CONTENTS TOGGLE NORMAL FULL 14:9 ZOOM 14:9 PANORAMA FULL CINEMA 16:9 CINEMA 14:9 NORMAL FULL DOT BY DOT CINEMA TOGGLE OFF SRS FOCUS SRS FOCUS DUAL SCREEN OFF DUAL SCREEN ON DIRECT CHANNEL (1 99) CHANNEL UP CHANNEL DOWN TEXT OFF TEXT ON (TOGGLE) DIRECT PAGE JUMP (100 899)
Baud rate: Data length: Parity bit: Stop bit: Flow control:
Communication procedure Send the control commands from the PC via the RS-232C connector. The Display operates according to the received command and sends a response message to the PC. Do not send multiple commands at the same time. Wait until the PC receives the OK response before sending the next command.
Command format Eight ASCII codes e CR Command 4-digits: Command. The text of four characters. Parameter 4-digits: Parameter 0 9, x, blank, ? Return code
C1 C2 C3 C4 P1 P2 P3
P4
8
NOTE
Command 4-digits
Parameter 4-digits
Parameter
Input the parameter values, aligning left, and fill with blank(s) for the remainder. (Be sure that four values are input for the parameter.) When the input parameter is not within an adjustable range, ERR returns. (Refer to Response code format.) No problem to input any numerical value for x on the table.
If an underbar (_) appears in the parameter column, enter a space. If an asterisk (*) appears, enter a value in the range indicated in brackets under CONTROL CONTENTS.
When ? is input for some commands, the present setting value responds.
Appendix
Various audio and video devices may be connected via the SCART terminals.
1 3 5 7 9 111315171921
2 4 6 8 101214161820
SCART (INPUT 1)
15. Red input 16. Red/Green/Blue control 17. Earth for video 18. Earth for Red/Green/Blue control 19. Video output (TV Monitor out)
Audio
1.
8. Audio-video control
2.
3.
Contrast Brightness Colour Tint Sharpness Advanced C.M.S. Colour Temp Black Monochrome Film Mode I/P Setting DNR
5.
Audio
6.
7.
Blue input
SCART (INPUT 2)
15. Chroma S-Video input 16. Not used 17. Earth for video 18. Earth 19. TV Monitor output 20. Video input/S-video input 21. Plug shield
Setup
1.
8. Audio-video control
9
Power Save No Signal off No Operation off 15. Red input/Chroma S-Video input 16. Red/Green/Blue control 17. Earth for video 18. Earth 19. TV Monitor output 20. Video input/S-video input 21. Plug shield Auto Installation Programme Setup Child Lock Position WSS 4:3 Mode Full Mode Rotate Language Input Select Audio Out Cool Climate Colour System
2.
9. Earth
Power control
Power control
3.
4.
5.
Earth
6.
13. Earth
7.
Not used
Setup
SCART (INPUT 3)
1.
8. Audio-video control
2.
9. Earth
3.
4.
5.
Earth
6.
13. Earth
7.
Blue input
Option
Option
LC-30HV4E
LC-30HV4E
DIMENSIONS
AVC System
Unit: mm
250 183
95
365 430
180
10
LC-30HV4E
Display
Unit: mm
84.5
545
305
79
117.5
766
117.5
84.5
643
545
111
364
305
1002
11
LC-30HV4E
Main PWB 5
Front panel 3 4 4
12
LC-30HV4E
7. Remove the system/control terminal retaining: 7-1. Remove the four hex head screws securing the terminals of the system and control cables (white). 7-2. Remove the two screws securing the terminal of the system cable (gray). 7-3. Remove the rear chassis retaining screw. 8. Remove the PC I/F and SR units: 8-1. Remove the four PC I/F unit shield retaining screws and remove the shield. 8-2. Remove the six PC I/F unit retaining screws and remove the I/F unit. 8-3. Remove the two PC I/F unit angle retaining screws and remove the angle. 8-4. Remove the two SR unit retaining screws and remove the SR unit. 9. Remove the rear chassis: 9-1. Remove the two tuner nuts and washers. 9-1. Remove the 13 rear chassis retaining screws and remove the rear chassis. 10. Remove the three power supply board retaining screws and remove the power supply board.
8-1
SR unit 8-4
10
Power unit
13
LC-30HV4E
11. Remove the AV unit: 11-1. Remove the five AV unit retaining screws and remove the AV unit. 11-2. Remove the three AV unit angle retaining screws and remove the angle. 12. Remove the fan: 12-1. Remove the two cooling fan retaining screws and remove the cooling fan. 13. Remove unit from the front chassis: 13-1. Remove the two hex head screws and two screws securing the front shield to the front chassis and remove the front shield. 13-2. Remove the four screws securing the front unit and remove the unit.
11-1 AV unit
Cooling Fan
12-1
13-2
Front unit
14
LC-30HV4E
Display
1. 2. 3. 4. Take off bottom terminal cover. Take off the speaker by removing 4 screws and disconnecting speaker terminals. Take off the table stand by removing 6 screws. Take off the rear cabinet by removing 18 screws and releasing the front cabinet's 6 hooks.
4 4
Speaker Rear Cabinet
4 4 4 2 2 2 3 4 4 4 4 2
Speaker
Table Stand
Terminal Cover
5. Take off the operation cover assembly by removing 2 screws and detaching the connector. 6. Take off the center angle by removing 8 screws and disconnecting 1 lead wire from the fan.
5
Operation Cover Ass'y
P131
P130
Center Angle
P2103
15
LC-30HV4E
7. Take off the digital PWB by detaching 7 connectors and removing 4 screws. 8. Take off the LED PWB by detaching one connector and removing 2 screws. 9. Take off the speaker (L) PWB by detaching one connector and removing one screw. 10.Take off the speaker (R) PWB by detaching one connector and removing one screw.
7 7 7
SC4502 SC4551 SC491
7 7
Digital PWB
7
SC4503
7 13
Main PWB
9
P201
10
Speaker(R) PWB
Speaker(L) PWB
9 8
LED PWB
10
P202
11.Take off the main board by detaching 8 connectors and removing 4 screws. 12.Take off the SOUND PWB assembly by detaching 3 connectors and removing 4 screws. 13.Take off the 2 reinforcement angles by removing 3 screws from each angle. 14.Detach each connector.
Inverter 1PWB
12 14
CN5 P6901 P6907 CN4 P6565 P6551
14
CN7 P6553
14 14
P6555
14 14 14
Inverter GND PWB
P6902 P2106 P2101 SC2001 P6903 P3802 P6904 P6905 P2002 P2003 P2102 CN3
14
14
P6558 P6564
14
P6906
Audio PWB
P3804
12
P3801 P2104
11
Main PWB Power Unit
14 14 14
14
P6560
P6562
14 12
Reinforcement angle
15 11
13
13
16
LC-30HV4E
15.Take off the inverter GND PWB by removing 2 screws. 16.Take off the power PWB by removing 7 screws. Remove insulation sheet. 17.Take off the inverter 1 PWB by removing 3 screws. 18.Take off the inverter 2 PWB by removing 3 screws 19.Take off the 4 reinforcement angles by removing 2 screws from each angle. 20.Take off the 2 reinforcement angles by removing 3 screws from each angle. 21.Take off the chassis frame by removing 2 screws. 22.Take off the LCD panel assembly by removing 2 screws.
15
Inverter GND PWB
16 21 17
Inverter 1 PWB
18
20 20 19
19
19 19 22 22
17
LC-30HV4E
23.Take off the LCD panel with panel shield by removing 4 screws. 24.Take off D-BEF sheet, prism sheet and diffusion sheet. Take off ITO sheet and diffusion panel by removing 2 screws. 25.Take off the panel shield by removing 6 screws and 2 in the center.
23
LCD Panel
23
Lamp
25
24
25
Panel Shield
24 25 24
18
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19
LC-30HV4E
2. In-process adjustment screen layout
Page
Program version
Source of input
Color system
HDCP
Main unit
AV unit
NO SIG
HDCP:OFF EUROPE
EUROPE
6. Loading the backup data and setting HDCP when the PC I/F unit is replaced Nearly all data including factory settings, user settings, and channel setting is stored in the PC I/F unit. The product comes with EEPROM (IC1506) on the Main Unit in case the PC I/F unit is replaced; original data backed up on the EEPROM can be loaded to the new PC I/F unit. How to load the backup data Select EEPRON RECOVERT in the OSD menu (page 13/13) and turn the Volume key ON; then press ENTER. How to set HDCP After completion of adjustments, select KEY WRITE "ON" in the OSD menu (page 1/13) for manual adjustment and turn the Volume key ON; then press ENTER.
20
LC-30HV4E
Adjustment parameters 1) Analog adjustment (1) AVC System voltage adjustment Adjustment items
1 In-process adjustment mode (Check the destination.) AVC center 3.3V adjustment Connect a DC voltmeter to TP4 at the opening on the top of the PC I/F unit. Connect DC voltmeter to TP1701.
Adjustment conditions
Adjustment procedures
Using the In-process adjustment remote controller, enter the in-process adjustments mode. Check that the destination is EUROPE. Move the cursor to the [+Badj3.3V] line and adjust the TP4 voltage to 3.250.01V.
Move the cursor to the [+BAdj1.8V] line and press OK. Adjustment is complete if [+BAdj1.8V complete] appears. If ERR occurs, adjust pin 6 at CN9 on the PC I/F unit so that 1.8V is reached.
Adjustment conditions
Adjustment procedures
1. Set colour system to PAL. 2. Select PAL source. 100% colour bar signal including 100% white, such as split field colour bar
1. Adjust TP1101 so that the Y signal without the chroma component should be 1.00 0.05 Vp-p (between the bottom of sync signal and the white peak).
21
LC-30HV4E
(3) PAL signal adjustment Adjustment items
1 MAIN PAL Y CONTRAST adjustment MAIN PAL COLOR GAIN adjustment
Adjustment conditions
Adjustment procedures
1. Adjust pin (1) of P801 to 0.70 0.025 Vp-p.
Turn off the PEAK ACL control. Adjust the output (TP815) of IC810 to have 0.900.025 Vp-p from the pedestal level. Press the DUAL screen button. Select the special DUAL screen settings for adjustment (so that the same video source is reflected on MAIN/ SUB). 1. Adjust TB1274_SUB output (TP806) to 1.5 0.05 Vp-p. 1. Adjust TB1274_SUB output (TP805) to 1.5 0.05 Vp-p.
Adjustment conditions
Adjustment procedures
1. Set colour system to SECAM. 2. Select SECAM source. 100% colour bar signal including 100% white, such as split colour color bar 1. Adjust pin (1) of P801 to 0.70 0.025 Vp-p.
22
LC-30HV4E
(5) N358 signal adjustment Adjustment items
1 Setup
Adjustment conditions
Adjustment procedures
1. Set colour system to N358. 2. Select N358 source. 100% SMPTE colour bar or similar colour bar signal including 100% white. 1. Adjust pin (1) of P801 to 0.70 0.025 Vp-p.
0.70V
0.70V
Smoothed
Adjustment conditions
Adjustment procedures
1. Select component 15k Hz. 2. Select component source. 100% colour bar signal including 100% white, like split field colour bar Adjust pin (1) of P801 to 0.7 00.025 Vp-p.
MAIN COMP 15k Y Level adjustment MAIN COMP 15k COLOR GAIN adjustment
0.70V
23
LC-30HV4E
(7) Component HDTV signal adjustment Adjustment items
1 Setup
Adjustment conditions
Adjustment procedures
1. Input HDTV (1080i) component signal. 2. Select component source. 100% colour bar signal including 100% white, like split field colour bar Turn off the PEAK ACL control. Adjust the TP815 to have 0.90 0.25 Vp-p from the pedestal level.
Description
Adjustment procedure
* Then turn off the AC power supply of the AVC system. (Be careful not to use the power switches of the remote control unit and AVC system.)
24
LC-30HV4E
In-process adjustment items Do not change items, the adjustment procedure of which is not described in this manual. Inadvertent changes of such items may result in unexpected or unrecoverable errors. Page
Page 1
Item
Maker Select +BAdj3.3V +BAdj1.8V(Enter: Auto) KEY WRITE DATA COPY INDUSTRY INIT CENTER Version OSD Version CVIC Version TTXP Version MONITOR Version STANDBY TYPE HOTEL MODE SUB PAL Adjust SUB PAL Y SUB PAL COLOR GAIN TUNER DAC ADJ N358 Adjust N358 Y CONTRAST N358 COLOR GAIN MAIN CR GAIN N358 N358 TINT REFERENCE Adjust
Page
Page 2
Item
PAL Y CONTRAST PAL COLOR GAIN MAIN CR GAIN PAL MAIN CONTRAST 15K Center Acutime RESET Monitor Acutime RESET
Page 3
Page 4
SECAM Adjust SECAM Y CONTRAST SECAM COLOR GAIN MAIN CR GAIN SECAM COMP15K Adjust COMP15K Y CONTRAST COMP15K COLOR GAIN MAIN CR GAIN COMP15K COMP HDTV Adjust COMP HDTV CONTRAST COMP HDTV SUB BRIGHT PEAK ACL SW N358 White Balance N358 R CUTOFF N358 R DRIVE N358 G CUTOFF N358 G DRIVE N358 B CUTOFF N358 B DRIVE COMP33K White Balance COMPHDTV R CUTOFF COMPHDTV R DRIVE COMPHDTV G CUTOFF COMPHDTV G DRIVE COMPHDTV B CUTOFF COMPHDTV B DRIVE IPMODE PROGRESSIVE2 MDSW PROGRESSIVE2 PTGSW PROGRESSIVE2 IPMODE FMODEON2 MDSW FMODEON2 PTGSW FMODEON2 ILG LV MD LV VE LV IP MODE SEL
Page 5
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PAL White Balance PAL R CUTOFF PAL R DRIVE PAL G CUTOFF PAL G DRIVE PAL B CUTOFF PAL B DRIVE COMP15K White Balance COMP15K R CUTOFF COMP15K R DRIVE COMP15K G CUTOFF COMP15K G DRIVE COMP15K B CUTOFF COMP15K B DRIVE IPMODE INTERLACE MDSW INTERLACE PTGSW INTERLACE IPMODE PROGRESSIVE MDSW PROGRESSIVE PTGSW PROGRESSIVE IPMODE FMODEON MDSW FMODEON PTGSW FMODEON IPMODE SUB MDSW SUB PTGSW SUB IPMODE FMODEON PAL MDSW FMODEON PAL PTGSW FMODEON PAL DEBUG PRINT SW PIC ADJ MAKER SELECT PIC ADJ KOUTEI SELECT EEPROM SAVE EEPROM RECOVER DEBUG_SELECT_SW DEBUG COMPANY SELECT DEBUG PANELTYPE SELECT CENTER PROG UPDATE
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26
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Continued
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[Rewriting the monitor program] 1) Start terminal software in the in-process adjustment mode. (Terminal software is not supplied. Use a freeware program available on the Internet.) 2) Set as follows: Baud rate: 9600 Data length: 8 bits Parity: None Stop bit: 1 Flow control: None 3) If the settings are correct, pressing ENTER will cause ERR to appear on the screen. 4) Type "IPL_0002" and press ENTER. Characters on the screen will disappear and the screen blacks out. * After the above string is entered, unusual indication may appear on the screen. This is not abnormal. 5) Press ENTER. The following will appear on the screen: ERR SEND "MONITOR PROG UPDATE PROGRAM" from PC to MR 6) Change the baud rate of the terminal software to 115200. 7) Use the file transfer facility of the terminal software to transfer the file specified in the document accompanying with the rewriting software. 8) If the terminal software screen shows the following indication, the monitor program has been rewritten successfully. (The indication will vary depending on the terminal software and program versions.) 9) Enter the in-process adjustment mode and make sure the version information on the MONITOR line has been updated.
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3. Adjusting Mode
1. Overview The controller IC can be adjusted in this mode. Adjustment is done while controlling the setting of the resistor corresponding to the selected adjustment item. When monitor is used independently, it is adjusted using the OSD simple display function incorporated in LCD controller. The OSD function of panel link receiver (SIL861) is used for adjustment of the independent monitor. 2. Entry to the mode 1) When cable is not connected (independent mode), follow the steps below. a) When power switch is turned on, press the main unit INPUT and VOL DOWN keys simultaneously. b) Press the remote controller's process adjustment key (R/C code: 40h) / process adjustment mode 2 key (R/ C code: 31h). 2) When not in independent mode, follow the steps below. a) When power switch is turned on, press the main unit CH DOWN and VOL UP keys simultaneously. b) Press the remote controller's process adjustment mode 2 key. 3. Exit from the mode Turn off the power. Press the remote controller's process adjustment mode 2 key. 4. Display 1) First layer display The third line shows the title. The 5th line and below show the items. Microprocessor's version number appears in the 16th line. Example) 1.00 1 00
1 2 3 4 5 6 1 S E R V I C 2 O M O D E 3 L C D 4 S I L 8 6 5 T E S T 6 V 7 8 9 10 11 12 13 14 E M O D E 5 0 H Z 1 E R X X X
2) Second layer display (Adjustment item display) A single page shows up to 10 adjustment items (or 14 lines). The third line shows the title and the screen mode selected in MODE items (only when LCD is selected). The 5th line shows the item. Microprocessor's version number appears in the 16th line. Example) 1.00 1 00 Setting is shown in decimal number. a) Adjustment on the LCD items
1 2 3 4 5 6 7 8 9 10 11 12 13 1 L C D 5 0 H Z 2 O V L 0 2 2 3 R E F 0 2 0 4 V L 6 4 9 5 R E F 6 4 1 7 6 V L 9 6 9 7 R E F 9 6 1 8 8 V L 1 2 8 8 9 R E F 1 2 8 1 8 10 V L 1 6 0 7 11 R E F 1 6 0 1 9 14 1 9 8 0 2 4 5 8 1 9
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b) Adjustment on the TEST items
1 2 3 4 5 1 T E S T 2 O L E R 3 L C D 4 5 C L R 6 7 C N F G 8 6 7 8 9 10 11 12 13 14 R R E D A T A M O D E E E P 0 0 0 0 0 W A I T 0 W A I T 0 0 0 0 W A I T
5. Changing data In "adjustment item display", the items pointed by cursor can be changed using VOL UP/DOWN key.(Holding down the key is effective.) For the items in "LCD DATA", select the item and hit ENTER key. The ten's digit (leftmost digit) in the address changes to red (others in green). Data change using VOL UP/DOWN key is enabled. To move to the next digit, press CH UP key (or rightward cursor key). To go back to the previous digit, press CH DOWN key (or leftward cursor key). Thus, 4 digits data can be entered. When CH UP key is pressed while in rightmost digit, the cursor moves to the leftmost digit. When CH DOWN key is pressed while in leftmost digit, the cursor moves to the rightmost digit. After address data adjustment, press ENTER key to exit from 4-digit adjustment and change the entire "LCD DATA" line to red letters. (Same status as item selection) 6. Key operation 1) Basic behaviors Basic key behaviors are as follows.
Behavior Keys Remote controller Upward cursor movement Cursor up Downward cursor movement Cursor down Rightward cursor movement Cursor right Leftward cursor movement Cursor left Data UP VOL UP Data DOWN VOL DOWN Set ENTER Back to previous layer RETURN Back (In bottom layer only) ENTER Main unit CH UP CH DOWN
2) Data UP/DOWN For the item for which OSD display is available, switch the display. Adjust the data with UP/DOWN operation. (Any value beyond the limit is replaced by the limit value.) Output data processing Data transmission for every UP/DOWN operation (Data related to peripheral controller IC) Execution of the last memory data when key is off While the key is held down, the second step is performed approx. 500ms after the key operation and, after this, every single step of UP/DOWN is carried out sequentially at 135ms interval. 3) Cursor UP/DOWN Select the adjustment item by pointing it with the cursor. When upward cursor movement is done while the cursor is at the top item, the cursor goes to the bottom item. (In the case of multiple pages, the cursor goes to the bottom item on the previous page.) When downward cursor movement is done while the cursor is at the bottom item, the cursor goes to the top item. (In the case of multiple pages, the cursor goes to the top item on the next page.) While the key is held down, the second step is performed approx. 500ms after the key operation and, after this, every single step of UP/DOWN is carried out sequentially at 135ms interval.
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SIL861
TEST
32
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IC1901 (IXA392WJ) FPGA for synchronous processing This IC selects synchronization signals and creates horizontal blanking signals. IC604 (TA1318AF) IC for synchronous processing of TV component signals and measurement of frequency. This IC incorporates an input signal frequency measurement feature and synchronous regeneration features. It supports synchronous horizontal regeneration (15.75 KHz, 31.5 KHZ, 33.75 KHz and 45 KHz) and synchronous vertical regeneration (525I, 525P, 625I and 750P). PC I/F board side IC4 (CX3506R) 3-channel, 8-bit, 120 MSPS A/D converter incorporating AMP and PLL. This IC is for video signals inputted to the IF board and used for one-screen and two-screen applications, and for PC signals inputted to the front panel. It provides A/D conversion of video signals (analog RGB) inputted to IN1 from CN6 and PC signals (analog RGB) inputted to IN2 from CN8. Converted digital signals are sent to IC25. IC310 (TLC5733A) 3-channel, 8-bit, 20 MSPS A/D converter. This IC is for video signals inputted to the IF board and used for two-screen application. It provides A/D conversion of video signals (analog YcbCr) inputted to IC310 from CN6. Converted digital signals are sent to IC25. IC25 (IXA091WJ) IC for I/P conversion and scaling of digital image according to the output resolution, and for data conversion. There are two input channel: V0 and V1. V1 is for sub 480i/580i input processing for two-screen application. V0 is for processing all signals for main used for one and two-screen applications. The IC generates clamp signals based on input synchronization signals. It also performs data matrix conversion, and creates OSD signals. Processed signals are sent to IC413. IC413 (SiI170) Panel link transmitter. This IC converts 8-bit RGB image data received from IC25 into TMDS differential signals and sends to the monitor. IC1 (IX8270CE) One-chip RISC microprocessor. This IC communicates with the monitor and controls the system operation. It controls all the ICs located in the media receiver. IC405 (UPD4721G) RS-232 line driver/receiver conforming to EIA/TIA-232-E. This IC enables the system to be controlled from a PC connected to the system. It also allows IC1 to be upgraded using the PC.
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RH-iXA385WJZZ (ASSY:IC2510) Pin mapping
Pin No. 1, 19, 32, 33 44, 64 2 3 4 5 6 7 8, 9, 10, 18, 31 41, 42, 43, 62 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 28 29 30 34 35 36 37 38 39 40 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 63 Pin Name VDD PLLVDC VCOIN TEST CPOUT PLLEN PLLGND GND PLLENO SPDIFO SPDIFI IO0 IO1 IO2 IO3 IO4 UTEST NANDTO RESET MEMTEST BISTOUT RWCLK RSTRW FEW FRE FD07 FD06 FD05 FD04 FD03 FD02 FD01 FD00 FD17 FD16 FD15 FD14 FD13 FD12 FD11 FD10 SDA SCS SCK I2SCLO I2SDAO I2SWSO I2SWSI I2SDAI I2SCLI REFCLK Type I I O I O O I I/O I/O I/O I/O I/O I O I I O O O O O O O O O O O O O I I I I I I I I I/O I I O O O I I I I Power supply PLL power supply VCO IN (used to construct external loop filter) Input for testing Charge pump out (used to construct external loop filter) PLL enable signal input Description
PLL enable signal output S/PDIF output (3.072 Mbps) S/PDIF input (3.072 Mbps) Expanded I/O, bit 0 Expanded I/O, bit 1 Expanded I/O, bit 2 Expanded I/O, bit 3 Expanded I/O, bit 4 Input for testing Output for testing Asynchronous reset signal input Input for testing Output for testing Expanded FIFO R/W clock Expanded FIFO master reset Expanded FIFO write enable Expanded FIFO read enable Expanded FIFO data output, bit 7 Expanded FIFO data output, bit 6 Expanded FIFO data output, bit 5 Expanded FIFO data output, bit 4 Expanded FIFO data output, bit 3 Expanded FIFO data output, bit 2 Expanded FIFO data output, bit 1 Expanded FIFO data output, bit 0 Expanded FIFO data input, bit 7 Expanded FIFO data input, bit 6 Expanded FIFO data input, bit 5 Expanded FIFO data input, bit 4 Expanded FIFO data input, bit 3 Expanded FIFO data input, bit 2 Expanded FIFO data input, bit 1 Expanded FIFO data input, bit 0 Serial communication data Serial communication chip select Serial communication chip select 12S CL output 12S CL output 12S WS output 12S WS input 12S DA input 12S CL input PLL REF CLK (same input as 12SCLI)
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Pin mapping
Pin No. 1 2 3 4 5 6 7 8 9 10 11, 12, 13 14, 15, 16 17 18 19 20 21 22 23 24 25 26 27 28 29, 30, 31, 32 33 34 35 36 37 38 39 40 41,42 43,44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61, 62 63, 64 65, 66 67 68 69 70 71 72 73 74 75, 76 77 78 79 80 Pin Name NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 NC I2S_CL3 I2S_WS3 RESETQ I2S_DA_IN3 NC DACA_R DACA_L VREF2 DACM_R DACM_L NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M NC AHVSS AGNDC NC SC4_IN_L SC4_IN_R ASG SC3_IN_L SC3_IN_R ASG SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R VREFTOP NC MONO_IN AVSS NC AVSUP ANA_IN1+ ANA_INANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ Type I/O I/O I/O I/O O I O O O I I I I I O O O O O O O O I I I I I I I I I I I I I I O O I/O I/O I I Description Not connected I2C clock I2C data I2S clock I2S word strobe I2S data output I2S1 data input ADR data output ADR word strobe ADR clock Digital power supply 5V Digital ground I2S2-data input Not connected I2S3 clock I2S3 word strobs Power-on-reset I2S3-data input Not connected Headphone out, right Headphone out, left Reference ground 2 Loudspeaker out, right Loudspeaker out, left Not connected SCART 2 output, right SCART 2 output, left Reference ground 1 SCART 1 output, right SCART 1 output, left Volume capacitor AUX Analog power supply 8V Volume capacitor MAIN Not connected Analog ground Analog reference voltage Not connected SCART 4 input, left SCART 4 input, right Analog Shield Ground SCART 3 input, left SCART 3 input, right Analog Shield Ground SCART 2 input, left SCART 2 input, right Analog Shield Ground SCART 1 input, left SCART 1 input, right Reference voltage IF A/D converter Not connected Mono input Analog ground Not connected Analog power supply 5V IF input 1 IF common(can be left vacant, only if IF input 1 is also not in use) IF input 2(can be left vacant, only if IF input 1 is also not in use) Test pin Crystal oscillator Test pin Audio clock output(18.432MHz) Not connected D_CTR_I/O_1 D_CTR_I/O_0 I2C Bus address select Stand-by(low-active)
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VHiCXA2069Q-1 (ASSY:FIC1301) S2-compatible 7-input, 3-output AV switch Block diagram
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Pin mapping
Pin No. 63 1 8 15 22 30 60 3 10 17 24 49 5 12 19 26 51 62, 2 9, 16 23, 29 59, 64 4, 11 18, 25 31, 61 53 41 44 56 39 58 47 37 52 43 38 54 45 40 6 13 20 27 7 14 21 28 32 Pin Name TV V1 V2 V3 V4 V4 V4 Y1 Y2 Y3 Y4 YIN1 C1 C2 C3 C4 CIN1 LTV, LV1 LV2, LV3 LV4, LV5 LV6, RTV RV1, RV2 RV3, RV4 RV5, RV6 VOUT1 VOUT3 V/YOUT2 YOUT1 YOUT3 COUT1 COUT2 COUT3 LOUT1 LOUT2 LOUT3 ROUT1 ROUT2 ROUT3 S2-1 S2-2 S2-3 S2-4 S-1 S-2 S-3 S-4 ADR Type I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O I I I I I I I I I Video signal input Composite video signal input Description
Y/C separation signal input, used for luminance signal input YIN1: Input for signal created by Y/C separation of VOUT1 output
Y/C separation signal input, used for chrominance signal input CIN1: Input for signal created by Y/C separation of VOUT1 output
Video signal output, used for composite vide signal output Video signal output, controlled via 12C bus and used for composite video signal output Power or luminance signal output is selected. Video signal output, used for luminance signal output Video signal output, used for chrominance signal output
33 34 36
I I O
55 46 48
I I I
Used for detection of S2-compatible DC that is superimposed to C signal. 4:3 image signal is selected when voltage ? 1.3V, 4:3 letterbox signal when 1.3V < voltage ? 2.5V, and 16:9 squeeze signal when voltage > 2.5V. 4:3 image signal is selected when the pins are open because they are pulled down to GND via 100K?. Used for selection between composite video signal and S signal. Detection result is written to the status register. S signal is selected when voltage ? 3.5V, and composite video signal when voltage > 3.5V. Composite video signal is selected when the pins are open because they are pulled down to 5V via 100K?. Used for selection of slave address for 12C bus. 90H is selected when voltage ? 1.5V, and 92H when ? 2.5V. 90H is selected when the pin are open. 12C bus signal input 12C bus signal input Used for output of S2-compatible DC that is superimposed to COUT3. DC superimposition is done by connecting to COUT3 via capacitor. The pin is controlled via 12C bus. Connection of 4.7k? external resistor provides output impedance of 10?3K? that conforms to S2. Connected to trap circuit for sub carrier. Mute for audio signal output. Mute is on when voltage ? 1.3V and off when voltage ? 2.5V. Mute is off when the pin is open. Internal reference bias input. Connected to GND via capacitor.
50
BIAS
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LC-30HV4E
VHiMM1519XQ-1 (IC1401) Component Input Video Switch Block diagram
40
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Pin mapping
Pin No. 1 2 3 11 12 13 21 22 23 4, 14, 39,45, 52, 58 51 5 15 53 59 24 6, 8, 16, 18, 33,35, 37, 41, 43, 47, 49, 54, 58, 60, 62 7 9 17 19 55 57 61 63 10 20 32 64 25 26 27 28 29 30 31 34 36 38 40 42 44 46 48 50 Pin Name VIDEO 1-L1 VIDEO 1-L2 VIDEO 1-L3 VIDEO 2-L1 VIDEO 2-L2 VIDEO 2-L3 VIDEO 3-L1 VIDEO 3-L2 VIDEO 3-L3 VCC AVCC VIDEO 2-Y VIDEO 3-Y TUNER-Y VIDEO 1-Y DGND GND Type I I I I I I I I I I I I I D-pin connection line input Description
VIDEO 2-Pb VIDEO 2-Pr VIDEO 3-Pb VIDEO 3-Pr TUNER-Pb TUNER-Pr VIDEO 1-Pb VIDEO 1-Pr VIDEO 2-SW VIDEO 3-SW MONO-SW VIDEO 1-SW ADDRESS SDA SCL DVCC L3 OUT L2 OUT L1 OUT Pr OUT 3 Pb OUT 3 Y OUT 3 Pr OUT 2 Pb OUT 2 Y OUT 2 Pr OUT 1 Pb OUT 1 Y OUT 1
I I I I I I I I I I I I I I/O I O O O O O O O O O O O O
Chrominance input
Slave address input 12C bus data input/output 12C bus clock input Digital power supply (5V) Monitor output line output
Image output
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VHiTB1274AF-1Q (ASSY:IC801, IC802) VIDEO/CHROMA Processor Block diagram
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Pin mapping
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name CVBS1/Y1-IN SYNC-IN CVBS-OUT VS COMB Y-IN D-VDD COMB C-IN D-GND HS SCP Yvi-IN SYNC-VCC SCL SDA YS3 (iRGB1-in) SYNC-GND Cr1-IN Cb1-IN Y1-IN CLP-FIL Y-OUT Cb-OUT Cr-OUT YS1 (YVbC2-IN) B1-IN G1-IN R1-IN Y/C-GND Cr2-IN Cb2-IN Y2-IN Y/C-VCC B2-IN G2-IN R2-IN YS2/YM (RGB2-IN) FIL. X'TAL C3-IN APC-FIL CVBS3/Y3-IN ADDRESS C2-IN CVBS2/Y2-IN COMB SYS Fsc-OUT AFC-FIL C1-IN Type I I O O I I O O O I I/O I I I I O O O I I I I I I I I I I I I I I I I O O I Description CVBS1 or Y1-IN signal input Synchronization signal input CVBS or Y+C signal output Output of counted-down vertical synchronization signal Input of Y signal outputted from comb filter. Open when not used 5 VDC power supply to DDS/BUS/V-CD/H-CD block (standard) Input of C signal outputted from comb filter. Open when not used GND for DDS/BUS/V-CD/H-CD block Output of horizontal synchronization signal under AFC Sand castle pulse output. Clamp pulse and horizontal blanking pulse are outputted. Output of synchronous input Y signal selected using video SW 5VDC power supply to SYNC/HVCO block (standard) 12C bus SCL input 12C bus SDA output Switch for selection between main signal and RGB1 input signal. This input is operative only when RGB1-ENB is enabled during bus setting. GND for SYCN/HVOC block Y1/Cb/Cr1 signal input
Switch for selection between main signal and input signal RGB1 signal input. YS3 or 12C bus is used to select signal.
GND for Y/C/Text/Video-SW/1HDL block Y2/Cb2/Cr2 signal input. YS1 is used to select signal. Open when the pin is not used. 5VDC Power supply to Y/C/Text/Video-SW/1HDI block. (standard) RGB2 signal input. YS is used to select signal. Open when not used. Switch for selection between main signal and RGB2 input signal Connected to Y/C-VCC pin Connect to 16.2 MHz crystal oscillator Chroma signal input. Open when not used. Connected to chroma modulation filter CVBS33 or Y3 signal input. Open when not used. Slave address input Chroma signal input. Open when not used. CVBS2 or Y2 signal input. Open when not used. Current color system discrimination result output. Pin 46 is also used for this output. Sub carrier output Connected to AFC detection filter Chroma signal input. Open when not used.
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VHiCXA2101Q-1 (ASSY:IC803) Baseband image signal processing Block diagram
44
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Pin mapping
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 39 36 38 40 41 42 43 44 45 Pin Name IN2-H IN2-V IN2-1 IN2-2 IN2-3 Vcc-MAT IN3-H IN3-V IN3-1 IN3-2 IN3-3 GND-MAT IN4-H IN4-V IN4-1 IN4-2 IN4-3 V-PH IN5-H IN5-V IN5-1 IN5-2 IN5-3 H-PH YG-OUT YG-IN IREF-SYNC VS-OUT HS-OUT Vcc-OUT SCP-IN VTIM-IN HP-IN GND-OUT R-OUT G-OUT B-OUT R-SH G-SH B-SH IK-IN PABL-FIL ABL-FIL ABL-IN ABL-IN Type I I I I I I I I I I I I I I I I I I I I O I O O O I I I O O O O Description IN2-H: Independent H periodic signal input IN2-V: Independent V periodic signal input IN2 system signal input
Power supply to selector or synchronous processing modules IN3-H: Independent H periodic signal input IN3-V: Independent V periodic signal input IN3 system signal input
GND for selector or synchronous processing modules IN4-H: Independent H periodic signal input IN4-V: Independent V periodic signal input IN4 system signal input
Connected to capacitor for holding Vsync peak IN5-H: Independent H periodic signal input IN5-V: Independent V periodic signal input IN5 system signal input
Connected to capacitor for holding Hsync peak Output of composite video signal for synchronous separation Input of composite video signal for synchronous separation Pin for reference current setting (approx. 4.6V) Output of HV of either IN1 system or IN2 ? IN5 system selector signals. Signal is selected by 12C bus "YCBCR/MAT". Power supply to RGB system Sand-castle-pulse input V timing pulse input H pulse input GND for RGB system RGB signal output. When 100IRE white is inputted, signal is outputted at 2.6Vp-p. RGB AKB sample & hold
46 47 48 49
I I I I
Input of returned reference pulse Peak ABL peak-hold Creates LPF when ABL control signal is received. ABL control signal input YM1/YS1 control signal input. Input level is judged on the three-value logic. This pin enables VM to turn off when YM or YS reaches its specified value. Analog RGB1 signal input
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
LR2-IN LG2-IN LB2-IN ADDRESS DPIC-C SCL SCL DPIC-MUTE CLP-C VM-OUT VM/SHP/COL-OFF YCBCR-SW ECR-IN ECB-IN EY-IN
I I I I I I I I O I I I I
YM2/YS2 control signal input. Input level is judged on the three-value logic. This pin enables VM to turn off when YM or YS reaches its specified value. Analog RGB2 signal input
12C bus slave address input Used to connect capacitor to GND pair for detection of dynamic picture (black expansion) 12C bus SCl (serial clock) input 12C bus SDA (serial data) input Used to provide mute control to dynamic picture (black expansion) Connected to Y system clamp capacitor VM output. Differential waveform of Y signal is outputted with positive polarity. Used to turn off VM, sharpness and color. Input level is judged on the three-value logic. Input for switching signal inputted to INT/EXT SW. External input pin is selected when this input is High. External Y/Cb/Cr signal input
45
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RH-iXA385WJZZ (ASSY:IC2510) Pin mapping
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name NC SP_CP2 SP_VD GND SP_HD VD3 HD3 SP_CP1 TDI TMS TCK TEXT_HD US_HD TEXT_VD Vcc3.3V US_VD GND MODEA MODEB MODEC SELA SELO SELC TDO GND Vcc3.3V VD1 HD1 PL_VD PL_HD PL_CP PL_BLK MODED NC Vcc3.3V NC CC_HD ow_vblk HDS VDS HD2 VD2 clk NC Type I I I O O I I I I O I O I I I I I I I O I I O O O O I O I O O I I I Description Non-connection Input of clamp signal from synchronous separation IC (for 15K system) Input of vertical synchronization signal from synchronous separation IC Ground Input of horizontal synchronization signal from synchronous separation IC Output of vertical synchronization signal to synchronous separation IC Output of horizontal synchronization signal to synchronous separation IC Input of clamp signal from synchronous separation IC (normal) SP data input SP mode input SP clock input TEXT_HD output RCA/TEXT horizontal synchronization signal input TEXT_VD output TEXT_VD output RCA/TEXT vertical synchronization signal input Ground Mode selection signal A Mode selection signal B Mode selection signal C Input of HD switching control signal for main video chroma/RCA Input of control signal for TEXT synchronization signal output Input of control signal for TEXT synchronization signal output ISP data output Ground Power supply Input of vertical synchronization signal from main video chroma IC Input of horizontal synchronization signal from main video chroma IC Vertical synchronization signal output Horizontal synchronization signal output Clamp signal output H blank signal output Mode selection signal D Mode selection signal D Power supply Non-connection Horizontal synchronization signal for closed caption Auto wide V blank signal input Output of horizontal synchronization signal for PC board Output of vertical synchronization signal for PC board Input of horizontal synchronization signal from sub video chroma IC Input of vertical synchronization signal from sub video chroma IC Clock input Non-connection
46
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VHiTC90A69++1Y (ASSY:IC402) Pin mapping
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name BIAS VRT VDD1 TESTI1 VSS2 VRB YCIN TEST KILLER TESTI2 VDD3 VSS3 VDD2 TESTI3 SCL SDA MODE1 TESTOUT FSC VDD4 VSS4 FIL PD VB2 YOUT VSS1 COUT VB1 Type I I O I I I I I O I I I O O O Description ADC bias ADC upper limit bias ADC and DAC power supply (analog system) Input for testing ADC GND (analog system) Video signal input ADC lower limit bias Reset control and test control before shipping Y/C separation and vertical enhancer OFF Input for testing Power supply to logic (digital system) Logic and DRAM GND (digital system) DRAM power supply (digital system) Input for testing IIC BUS clock input IIC BUS data input MODE1 output Input for testing Clock input PLL power supply (analog system) PLL GND (analog system) VCO control PLL detection output DAC bias 2 Luminance signal output DAC GND (analog system) DAC GND (analog system) DAC bias 1
47
LC-30HV4E
RH-iX3270CEZZ (ASSY:IC1) Pin mapping
Pin No. 34, 36-44, 46, 48-52 23-26, 28, 30-32 13-18, 20, 22 86, 84, 82, 78-72, 70-68-60, 56-53 96 98 99 100 101 102 87 118 106 119 107 108 110 112 113 116 117 89 90 91 92 93 88 105 123 11-8 12 7 160 182 159 191 114 192 115 189 190 171 164 165 172 166 167 174 168 169 170 176 104 126 103 146, 149 156 155 162 5 4 Pin Name D[15:0] D[23:16/PTA[7:0] D[31:24/PTB[7:0] A[25:0] CS0 CS2/PTK[0] CS3/PTK[1] CS4/PTK[2] CS5/CE1E/PTK[3] CS6/CE1B BS/PTK[4] RAS3U/PTE[2] RAS3L/PTJ[0] RAS2U/PTE[1] RAS2L/PTJ[1] CASLL/CAS/PTJ[2] CASLH/PTJ[3] CASHL/PTJ[4] CASHH/PTJ[5] CAS2L/PTE[6] CAS2H/PTE[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] WE3/DQMUU/ ICIOWR/PTK[7] RD/WR RD CKE/PTK[5] WAIT IRL[3:0]/IRQ[3:0]/ PTH[3:0] IRQ4/PTH[4] NMI IRQOUT WAKEUP/PTD[3] TCLK/PTH[7] DREQ0/PTD[4] DACK0/PTD[5] DREQ1/PTD[6] DACK1/PTD[7] DRAK0/PTD[1] DRAK1/PTD[0] RxD0/SCPT[0] TxD0/SCPT[0] SCK0/SCPT[1] RxD1/SCPT[2] TxD1/SCPT[2] SCK1/SCPT[1] RxD2/SCPT[4] TxD2/SCPT[4] SCK2/SCPT[5] RTS2/SCPT[6] CTS2/IRQ5/SCPT[7] CE2B/PTE[5] IOIS16/PTG[7] CE2A/PTE[[4] CAP[1:2] EXTAL XTAL CKIO EXTAL2 XTAL Type I/O I/O I/O O O O/(I/O) O/(I/O) O/(I/O) O/(I/O) O O/(I/O) O/(I/O) O/(I/O) O/(I/O) O/(I/O) O/(I/O) O/(I/O) O/(I/O) O/(I/O) O/(I/O) O/(I/O) O O O/(I/O) O/(I/O) O O O/(I/O) I I I I O O/(I/O) I/O I O/(I/O) I O/(I/O) O/(I/O) O/(I/O) I O I/O I O I/O I O I/O O/(I/O) I O/(I/O) I O/(I/O) I O I/O I O Data bus D [15:0] Data bus D [23:16] / I/O port A [7:0] Data bus D [31:24] / I/O port B [7:0] Address bus A [15:0] Chip select 0/ Chip select 2 / I/O port K [0] Chip select 3 / I/O port K [1] Chip select 4 / I/O port K [2] Chip select 5 / CE1 (area 5SPCMIA)/O port K [3] Chip select 6 / CE1 (area 6SPCMIA) Bus cycle start signal / I/O port K [4] RAS (area 3DRAM, SDRAM upper 32MB address) / I/O port E [2] RAS (area 3DRAM, SDRAM upper 32MB address) / I/O port J [0] RAS (area 2DRAM, SDRAM upper 32MB address) / I/O port E [1] RAS (area 2DRAM, SDRAM upper 32MB address) / I/O port JE [1] D7-D0 CAS (DRAM)/CAS (SDRAM) / I/O port J [2] D15-D18 CAS (DRAM) / I/O port J [3] D23-D16 CAS (DRAM) / I/O port J [4] D31-D24 CAS (DRAM) / I/O port J [5] D31-D24 CAS (DRAM) / I/O port J [5] D31-D24 CAS (DRAM) / I/O port J [5] D7-D0 selection signal/DQM (SDRAM) D7-D0 selection signal/DQM (SDRAM) D23-D16 selection signal/DQM (SDRAM)/PCMCIA I/O port K [6] D31-D24 selection signal/DQM (SDRAM)/PCMCIA I/O write I/O port K [7] Read/Write switch signal Read strobe CK enable (for SDRAM only) / I/O port K [5] Hardware wait request Hardware wait request External interrupt request / I/O port H [4] Non-maskable interrupt request Interrupt request output Standby mode interrupt request output / I/O ports D [3] TMU/RTC clock I/O / I/O port H [7] DMA request 0 / I/O port D [4] DMA ACK 0 / I/O port D [5] DMA request 0 / I/O port D [6] DMA ACK 1 / I/O port D [7] DMA ACK 1 / I/O port D [7] DMA ACK 0 / I/O port D [0] Receive data 0/SCI input port [0] Send data 0/SCI output port [0] Serial clock 0/SCI I/O port [1] Receive data 0/SCI input port [2] Send data 0/SCI output port [2] Serial clock 1/SCI I/O port [3] Receive data 0/SCI input port [4] Send data 2/SCI output port [4] Serial clock 2/SCI I/O port [5] Send request 2/SCI I/O port [6] Send clear 2/enternal interrupt request/SCI input port [7] PC card 0 chip enable 2 / I/O port E [5] Write protect/input port G [7] PC card 1 chip enable 2 / I/O port E [4] PLL external capacitor pin [1:2] External clock/crystal oscillator input Crystal oscillator output System clock I/O RTC crystal oscillator input RTC crystal oscillator output Description
48
LC-30HV4E
Pin mapping
Pin No. 193 124 122 121 2, 1, 144 196, 195 197 194 158, 157 204-199 206, 207 177-180, 185-188 184 120, 94 136-143 127-131, 135 125 151 21, 29, 35, 47, 59, 71, 81, 85, 97, 111, 134, 154, 163, 175, 183 145, 150 3 205 19, 27, 33, 45, 57, 69, 79, 83, 95, 109, 132, 152, 153, 161, 173, 181 147, 148 6 198, 208 Pin Name RESETP RESETM BREQ BACK MD[2:0] MD[4:3] MD5 CA STATUS[1:0]/ PTJ[7:6] AN[5:0]/PTL[6:7] AN[6:7]/DA[1:0]/ PTL[6:7] PTC[7:0]/PINT[7:0] PTD[2]/RESETOUT PTE[0]/PTE[7] PTF[7:0]/PINT[15:8] PTG[6:0] PTH[5]/ADTRG PTH[6] Vcc Type I I I O I I I O I/O I I/O I/O I/O I/O I I I I Description Power-on reset request Manual reset request Bus request Bus ACK Clock mode select Area 0 bus width select Endian select Chip active Processor status [1:0] / I/O port J [7:6] A/D converter input [5:0]/input port L [5:0] A/D converter input [6:7] / D/A converter output [1:0] / input port L [6:7] I/O port C [7:0]/port interrupt [7:0] I/O port D [2]/reset output I/O port E [0]/I/O port E [7] I/O port E [7:0]/port interrupt [15:8] I/O port G [6:0] I/O port H [5]/analog trigger I/O port H [6] Power supply (3.3V)
Power supply (3.3V) Power supply (3.3V) Analog power supply (3.3V) Power supply (0V)
Power supply (0V) Power supply (0V) Analog power supply (0V)
49
LC-30HV4E
9DK001-15079 (CXA3506R) (ASSY:IC4) 3-channel, 8-bit, 120MSPS A/D converter amplifier PLL Pin mapping
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16, 94 17 18, 92 19, 32, 42, 54, 65,76,90 20, 33, 44, 55, 67, 77, 89 21, 22, 24-28, 31 23, 30, 43, 50, 59, 66,7 9, 86 29, 80 34-41 45-49, 51-53 56-58, 60-64 68-75 78, 81-85, 87,88 91 93 95 96 97 98 99 100 101 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 123 124 125 126 127 128 129 130 132 133 134 135 136 137 Pin Name B/CbOUT ADDRESS R/CrOUT NC NC XPOWERSAVE DGNDREG DVCCREG SDA SCL XSENABLE SEROUT 3WIRE/I2C AVCCADREF AVCCAD3 VRT DVCCAD3 DVCCADTTL DGNDADTTL RA0~RA7 DGNDAD3 AGNDAD3 RB0~RB7 BA0~`BA7 BB0~BB7 GA0~GA7 GB0~GB7 DVCCAD VRB AGNDADREF DVCCPLLTTL DGNDPLLTTL XCLKCLK 1/2XCLK 1/2CLK DSYNC/ DIVOUT UNLOCK SOGOUT HOLD XTLOAD EVEN/ODD XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVCCPLL DGNDPLL AVCCVCO AGNDVCO RC1 RC2 AVCCIR IREF AGNDIR G/YIN1 AVCCAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP SOGIN1 B/CbIN1 AVCCAMPB SOGIN2 B/CbIN2 AGNDAMPB Type O I O I I I I O I O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I Description Amplifier output signal monitor I2C slave addressing Amplifier output signal monitor Not used Not used Power saving Resistor GND Resistor power supply Control resistor data input Control resistor clock signal input 3-wire control resistor enable signal input 3-wire control resistor data read 12V bus mode and 3-wire bus mode select ADC reference voltage power supply ADC analog power supply ADC top reference voltage output ADC digital power supply ADC TTL output power supply ADC TLL output GND R channel port A data output ADC digital GND ADC analog GND R channel port B data output B channel port A data output B channel port B data output G channel port A data output G channel port B data output ADC digital power supply ADC bottom reference voltage output ADC reference voltage GND PLL TTL output power supply PLL TTL output GND CLK reverse output CLK output I2CLK reverse output I2CLK output DSYNC signal outut/DIVOUT signal output UNLOCK signal output Input of sink signal of Sink-On-Green signal Phase comparison disable signal input Programmable counter reset ADC sampling clock inverse pulse input Negative test clock input Positive test clock input Sink signal input 1 Sink signal input 2 Clamp pulse input PLL digital power supply PLL digital GND PLL VCO analog power supply PLL VCO analog GND External PLL loop filter External PLL loop filter IREF analog power supply Current input IREF analog GND G/Y signal input 1 G/Y amplifier power supply G/Y signal input 2 G/Y amplifier power supply Brightness clamp capacitor connection Brightness clamp capacitor connection Brightness clamp capacitor connection Sink-On-Green signal input 1 B/Cb signal input 1 B/Cb amplifier power supply Sink-On-Green signal input 2 B/Cb signal input 2 B/Cb amplifier GND
50
LC-30HV4E
Pin No. 139 140 141 142 143 144 14, 102, 122, 131, 138
Type I I O O
Description R/Cr signal input 1 R/Cr amplifier power supply R/Cr signal input 2 R/Cr amplifier GND Amplifier output signal monitor Input for testing amplifier control resistor DAC
51
LC-30HV4E
Is the power cable connected properly? YES Is fuse (F701) in order? YES Is the BU+5V line (pin 1 of P1703) in order? YES Are the wire harness and FFC connected properly? YES
NO
NO
Check connections of the wire harness and FFC and reconnect if necessary. Check power supply internal devices (IC701, IC72, PC702, Q702, D708 and D705). Check DC/DC converter output lines and MOS-FET (Q1707 and Q1708) and replace if necessary.
Does the voltage of the OVP line (pin 8 of P1702) fluctuate after power-on? YES Are DC/DC converter outputs and MOS-FET (Q1707 and Q1708) in order? YES Replace IC1703.
NO
NO
The power does not turn on even through the power button is pressed. (The red power LED on the front panel does not turn green or is blinking red). Is the system cable connected properly between the Display and the AVC System (between DISPLAY OUTPUT(1)s)? YES Are the power switches of the Display and AVC System on? YES Are the UR+6V, UR+10V and UR+13V lines (pins 1, 2, 7 and 9 of P1702) in order? YES NO Is PS_ON (pin 3 of P1702) pulled high (3.5V)? YES NO Check the PS_ON line. YES Is the impedance of the UR+6V, UR+10V and UR+13V lines correct? (Measure the resistance between pins 1/2/7/9 of P1072) and GND). NO Check the UR+6V, UR+10V and UR+13V lines and devices on the lines. NO Are the D+1.8VCV line (pins 5 and 6 of P1701), D+3.3V line (pin 8 of P1701), D+5V line (pin 1 of P1701) and A+5V line (pin 3 of P1701) in order? YES Is D_POW (pins 32 and 34 of IC1703, pin 2 of IC1704 and pin 2 of IC1705) pulled high? YES NO Check the D_POW line (pin 6 of IC1503). Are MOS-FET (Q1707 and Q1708) and REG. IC (IC1704 and IC1705) in order? NO YES Replace IC1703. Check each output line and replace MOS-FET (Q1707 and Q1708) and REG. IC (IC1704 and IC1705). NO Turn on the power switches of the Display and AVC System. NO
52
AVC System
No sound (1) The speaker generates no sound when audio signals are inputted from an external device or a PC. YES Set the monitor audio output to "Fixed". Remove the headphone. NO NO Check IC2501 (multi-sound processor) and its peripheral circuits. Are the audio outputs of IC1301 (AV switch) in order? Pins 52 and 54 of IC1301 (TV MAIN OUT L/R) YES Are the audio inputs of IC2501 (multi-sound processor) in order? Pins 56 and 57 of IC2501 (SCI IN1 L/R)
NO
Are the audio outputs of IC2501 (multi-sound processor) in order? Pins 36 and 37 of IC2501 (SC1 OUT L/R).
Are audio signals applied to the AV unit connectors (pins 1 and 3 of P2502)? YES Check IC1301 (A switch) and its peripherals.
NO
Check lines and devices between pins 36/37 of IC2501 and pins 1/3 of the AV unit connector (P2502). (Q2504-5, Q2509-10 and Q2513-4)
Are the audio inputs of IC1301 (AV switch) in order? Input 1: Between pins 2 and 4 of IC1301 Input 2: Between pins 9 and 11 of IC1301 Input 3: Between pins 16 and 18 of IC1301 Input 4: Between pins 23 and 25 of IC1301 PC input: Between pins 29 and 31 of IC1301
YES
Are the audio input circuits of IC1301 (AV switch) in order? YES Input 1: Between pins 6/2 and pins 2/4 of IC1301 Input 2: Between pins 6/2 and pins 9/11 of IC1301 Input 3: Between pins 6/2 and pins 16/18 of IC1301 Front panel input: Between J2404 and pins 23/25 of IC1301 PC input: Between J2403 and pins 29/31 of IC1301
53
No sound (3) No audio output <INPUT2/3> YES NO Are the audio outputs of IC1301 (AV switch) in order? Pins 43 and 45 of IC1301 (SC1 TV SUB OUT L/R) YES Check lines and devices between pins 43/45 of IC1301 and pins 3/1 of INPUT2/3. Also check the audio mute circuits. (IC1301, Q1104-7 and Q1109-12)
Are the tuner audio inputs of IC2501 (multi-sound YES Check IC2501 (multi-sound processor) and its processor) in order? peripheral circuits. Pin 67 (sound IF1) of IC2501 Pin 69 (sound IF2) of IC2501 NO YES Check B.P.F. of SIF1 and SIF2. Is the audio signal applied to tuner output pin 21? (Q1119-20 and Q1121-2)
NO
Has the input mode been selected on the Input Select screen?
YES Are the audio outputs of IC2501 (multi-sound processor) in order? Pins 27 and 28 of IC2501 (DRCM L/R)
YES Check lines and devices between pins 27/28 of IC2501 and pins 3/1 of INPUT1. Also check the audio mute circuits. (IC2504, Q1101-2)
The audio level is abnormal: Is the monitor audio output set correctly? "Variable" or "Fixed" YES No sound at all: Are the audio outputs of IC2501 (Multi-sound processor) in order? Pins 34 and 33 (SC2 OUT L/R) of IC2501 YES Check lines and devices between pins 34/33 of IC2501 and the monitor output (J1101). Also check the audio mute circuit. (Q2502-3, Q1114-5 and Q1106-7)
LC-30HV4E
LC-30HV4E
No video image on INPUT1 YES Has "INPUT1" been selected on the Input Select screen? YES NO Select INPUT1 CVBS on the Input Select screen. Check lines and devices between pin 20 of INPUT1 (SC1101) and pin 1 of IC1301. Is the video signal applied to pin 8 of IC1301 NO (AV switch)? YES (B) No image (2) NO
NO video image on INPUT2 YES Has "INPUT2" been selected on the Input Select screen? YES
Select INPUT2 CVBS on the Input Select screen. Check lines and devices between pin 20 of INPUT2 (SC1102 1/2) and pin 8 of IC1301.
Is the video signal applied to pin 1 of IC1301 NO (AV switch)? YES (A)
NO video image on INPUT3 YES Has "INPUT3" been selected on the Input Select screen? YES NO Select INPUT3 CVBS on the Input Select screen. Check lines and devices between pin 20 of INPUT3 (SC1102 1/2) and pin 15 of IC1301. Is the video signal applied to pin 22 of IC1301 (AV switch)? YES (D) NO NO
NO video image on INPUT4 YES Has "INPUT4" been selected on the Input Select screen? YES
Select INPUT4 CVBS on the Input Select screen. Check lines and devices between pin 3 of INPUT4 (J2404) and pin 22 of IC1301.
Is the video signal applied to pin 1 of IC1301 NO (AV switch)? YES (C) No image (3)
54
NO Select INPUT2 Y/C on the Input Select screen. Check lines and devices between pins20/15 of INPUT1 (SC1101) and pins 10/12 of IC1301. NO YES (F) No image (4) NO Select INPUT4 Y/C on the Input Select screen. Check lines and devices between pins3/4 of INPUT1 (J2401) and pins 24/26 of IC1301. NO
No Y/C image on INPUT2 YES Has "INPUT2" been selected on the Input Select screen? YES
No Y/C image on INPUT3 YES Has "INPUT3" been selected on the Input Select screen? YES Is the Y/C signal applied to pins 17 and 19 of IC1301 (AV switch)?
NO
Select INPUT3 Y/C on the Input Select screen. NO Check lines and devices between pins20/15 of INPUT2 (SC1102 1/2) and pins 17/19 of IC1301.
YES
(E)
No Y/C image on INPUT4 YES Has "INPUT4" been selected on the Input Select screen? YES
Is the Y/C signal applied to pins 24 and 262 of IC1301 (AV switch)? YES (G)
(A),(C),(E),(G) (B),(D),(F)
<When video signal is received> Are the main video signal and sub video signal sent from pin 56 and pin 44 of IC1301 respectively? <When Y/C signal is received> Are the main Y signal, main C signal, sub Y signal and sub C signal sent from pin 56, pin 58, pin 44 and pin 47 of IC1301 respectively?
<When video signal is received> Is the video signal applied to pin 7 of IC401 (main comb filter) and pin 7 of IC402 (sub comb filter)? <When Y/C signal is received> Are the main signal and sub signal applied to pins 44 and 43 of IC801 (main video chroma) and pins 5 and 7 of IC802 (sub video chroma) respectively? <Sub system> NO NO <When video signal is received> Check lines and devices between IC4001 and IC801. (IC403, Q415, etc.) <When video signal is received> Are the sub Y signal and sub C signal applied to pin 1 and pin 7 of IC802 (sub video chroma) respectively? YES
NO
<Main system>
YES
<When video signal is received> Are the main Y signal and main C signal applied to pin 1 (TP812) and pin 48 of IC801 (main video chroma) respectively?
<When video signal is received> Check lines and devices between IC402 and IC802. (IC404, Q416-8, etc.)
<When Y/C signal is received> Are the main Y signal and main C signal applied to pin 44 and pin 43 of IC801 (main video chroma) respectively? NO <When Y/C signal is received> Check lines and devices between IC1301 and IC801. (Q827, Q403, Q404, etc.) <When Y/C signal is received> Are the sub Y signal and sub C signal applied to pin 5 and pin 7 of IC802 (sub video chroma) respectively? YES NO Check IC801 (main video chroma) and its peripheral circuits. Are the sub Y, Cb and Cr signals sent from pins 21, 22 and 23 of IC802 respectively? YES Check lines and devices between IC801 and IC803. (IC814, Q814, Q815, etc.)
NO
<When Y/C signal is received> Check lines and devices between IC1301 and IC802. (IC828, Q409, Q410, etc.)
YES
Are the main Y, Cb and Cr signals sent from pins 21, 22 and 23 of IC801
NO
55
NO Check IC803 (RGB decoder) and its peripheral circuits. NO Check lines and devices between IC803 and FL810.(Q801-3 etc.) NO YES Check FL810 (6.7/30 MHz L.P.F.) and its peripheral circuits. Is cutoff frequency setting pin 17 of FL810 (6.7/30 MHz L.P.F.) pulled high? Check the PC I/F unit.
YES
Are the main Y, Cb and Cr signals applied to NO pins 69, 68 and 67 of IC803 (RGB decoder)
Are the sub Y, Cb and Cr signals applied to Q901-2, Q903-4 and Q905-6 (6.7 MHz L.P.F.) respectively? YES Are the sub R, G and B signals sent from Q901-2, Q903-4 and Q905-6 (6.7 MHz L.P.F.) respectively? YES
NO
YES
Check lines and devices between IC802 and Q901-2/Q903-4/Q 905-6 (6.7 MHz L.P.F.).
Are the main R, G and B signals sent from pins 35, 37 and 39 of IC803 respectively?
NO
YES
Are the main R, G and B signals applied to pins 3, 7 and 10 of FL810 (6.7/30 MHz L.P.F.) respectively?
YES
Are the main R, G and B signals sent from pins 19, 15 and 12 of FL810 respectively?
YES
LC-30HV4E
AVC System No image (5) No RGB image on INPUT3 No component image on INPUT3
LC-30HV4E
Has "INPUT1" been selected NO on the Input Select screen? Select INPUT3 RGB on the Input Select screen. YES NO Check lines and devices between pins 15/11/7 of INPUT3 (SC1102) and pins 9/5/7 of IC1301. YES NO YES <Sub system> NO Are RGB signals applied to NO pins 5, 17 and 19 of IC1401 (AV switch)? YES Are RGB signals applied to pins 9, 5 and 7 of IC1401 (AV switch)? YES
YES
Are RGB signals applied to NO pins 63, 59 and 61 of IC1401 (AV switch)?
YES
Check lines and devices between pins 15/11/7 of INPUT1 (SC1101) and pins 63/59/61 of IC1301.
Check lines and devices between pins 8/26/17 of INPUT3 (J1101) and pins 15/17/19 of IC1301.
Are the main video signal, pass signal and sub video signal sent from pins 34, 38 and 36 of IC1401 respectively? YES <Pass 525P/1125i/750P system> Check lines and devices between pins34/38/36 of IC1401 and pins 5/4/3 of IC803. Are Y, Cb and Cr signals applied to pins 5, 4 and 3 of IC803 (RGB decoder) respectively?
Check IC1401 (AV switch) and its peripheral circuits. Check lines and devices between pins 40/44/42 of IC 1401 and pins 19/18/17 of IC802. NO Check IC802 (sub video chroma) and its peripheral circuits.
Are Y, Cb and Cr signals applied NO to pins 19, 18 and 17 of IC801 (main video chroma) respectively?
Check lines and devices between pins 46/50/48 of IC1401 and pins 19/18/17 of IC801.
YES
NO
Are Y, Cb and Cr signals applied to pins 19, 18 and 17 of IC802 (sub video chroma) respectively? YES Are the sub Y, Cb and Cr signals sent from pins 21, 22 and 23 of IC802 respectively? YES
56
Status of pin 17 for setting the cutoff frequency of FL810 (6.7/30 MHz L.P.F.) <525i system>: High <525P/1125i/750P system>: Low Check the PC I/F unit.
Are the main Y, Cb and Cr signals sent from pins 21, 22 and 23 of IC801 respectively? YES Are the main Y, Cb and Cr signals applied to pins 69, 68 and 67 of IC803 respectively? YES
NO
Check lines and devices between IC801 and IC803. (IC814, Q814-5, etc.)
Are the sub Y, Cb and Cr signals applied to Q901-2, Q903-4 and NO Q905-6 (6.7 MHz L.P.F.) respectively? YES Are the sub R, G and B signals sent from Q901-2, Q903-4 and Q905-6 (6.7 MHz L.P.F.) respectively? NO
Check lines and devices between IC802 and Q901-2/Q903-4/Q9056 (6.7 MHz L.P.F.).
Are the main R, G and Br NO signals sent from pins 35, 37 and 39 of IC803 respectively? YES Are the main R, G and Br NO signals applied to pins 3, 7 and 10 of IC810 (6.7/30 MHz L.P.F.) respectively? YES Are the main R, G and Br signals sent from pins 19, 15 NO and 12 of IC810 respectively?
Check lines and devices between IC803 and FL810. (Q801-3 etc.)
The cutoff frequency of FL810 (L.P.F.) is switched as follows depending on the input signals:
YES
YES Check FL810 (6.7/30 MHZ L.P.F.) and its peripheral circuits.
AVC System No image (6) No teletext screen appears. Select TELETEXT in an appropriate manner. NO NO Check peripherals of the tuner (TU1101) and replace if necessary. Is the teletext signal received (is a teletext-supporting receiver connected to the video input terminal) and TELETEXT selected on the remote controller? YES Is the video signal applied to pin 21 of IC1601 (teletext CPU)? NO NO Check IC1601 and its peripheral circuits. YES Is the text signal sent from pins 57, 58 and 59 of IC1601? YES Is the text signal applied to pins 57, 53 and NO 55 of IC1401 (AV switch)? Check lines and devices between pin 56 of IC1301 (AV switch) and pin 21 of IC1601. Is the level control signal sent from pin 1 of IC1108 to pin 8 of IC1103 (AV switch)? Check lines and devices between pin 5 of IC1106 and pin 63 of IC1301. Check IC1301 (AV switch) and its peripheral circuits.
YES Are the main video signal and sub video signal sent from pin 30 of IC1301 and pin 44 of IC1301 respectively? NO YES NO
Check lines and devices between pins 57/58/59 of IC1601 and pins 57/53/55 of IC1301.
YES
Is the video signal applied to pin 7 of IC401 (main comb filter) and pin 7 of IC402 (sub comb filter)? <Sub system> NO Check lines and devices between IC4001 and IC801. (IC403, Q415, etc.) YES Check IC801 (main video chroma) and its peripheral circuits. YES Check lines and devices between IC801 and IC803. (IC814, Q814, Q815, etc.) YES NO Check IC803 (RGB decoder) and its peripheral circuits. Are the sub R, G and B signals sent from Q901-2, Q903-4 and Q905-6 (6.7 MHz L.P.F.) respectively? YES Check lines and devices between IC803 and FL810.(Q801-3 etc.) Check the PC I/F unit. NO Are the sub Y, Cb and Cr signals applied to Q901-2, Q903-4 and Q905-6 (6.7 MHz L.P.F.) respectively? NO Are the sub Y, Cb and Cr signals sent from pins 21, 22 and 23 of IC802 respectively? NO Are the sub Y and C signals applied to pin 1 (TP813) and pin 48 (TP407) of IC802 (sub video chroma) respectively?
<Main system>
YES
Check lines and devices between IC1301 and IC401/402. Check lines and devices between IC402 and IC802. (IC404, Q416-8, etc.)
Are the main Y and C signals applied to pin 1 (TP812) and pin 48 of IC801 (main video chroma) respectively?
YES
Are the main Y, Cb and Cr signals sent from pins NO 21, 22 and 23 of IC801 respectively?
57
NO Is cutoff frequency setting pin 17 of FL810 (6.7/30 MHz L.P.F.) pulled high? Check FL810 (6.7/30 MHz L.P.F.) and its peripheral circuits. No image (7) No monitor image <S-OUT> NO Check IC1301 and its peripheral circuits.
YES Are the main Y, Cb and Cr signals applied to pins NO 69, 68 and 67 of IC803 (RGB decoder) respectively?
Check lines and devices between IC802 and Q901-2/Q903-4/Q905-6 (6.7 MHz L.P.F.).
YES
Are the main R, G and B signals sent from pins 35, 37 and 39 of IC803 respectively?
Check Q901-2, Q903-4 and Q905-6 (6.7 MHz L.P.F.) and their peripheral circuits.
YES Are the main R, G and B signals applied to NO pins 3, 7 and 10 of FL810 (6.7/30 MHz L.P.F.) respectively?
YES
Are the main R, G and B signals sent from pins 19, 15 and 12 of FL810 respectively?
YES
YES Is the video signal sent from pin 4 of IC1301 (AV switch)?
YES Are Y and C signals sent from pins 39 and 37 of IC1301 (AV switch) respectively?
NO
LC-30HV4E
YES Check lines and devices between pin 41 of IC1301 and monitor image output pin 20 (J1101). (Q1403 and Q1113)
YES Check lines and devices between pins 39/37 of IC1301 and monitor S-OUT pins 3/4 (SC1102). (Q1401-2)
NO
Synchronization failure <MAIN system; D2/D3/D4> <MAIN system; 1080i/625P> Is HD_50/VD_50 outputted to pins (79) and (80) of IC803, respectively? NO Check IC803 and its peripheral circuits. YES Check the circuit between pins (9)/(4) of IC801 and pins (44)/(2) of IC1901. Is HD_50/VD_50 inputted to pins (3) and (4) of IC803, respectively? NO YES Check IC1901 and its peripheral circuits. YES Check the circuit between pins (8)/(10) of IC1901 and pins (14)/(13) of IC604. Is SP-HD/SP-VD outputted to pins (40) and (5) of IC1901, respectively? NO YES Check the circuit between pins (16)/(28) of IC604 and pins (40)/(5) of IC1901. Is SP-HD/SP-VD outputted to pins (16) and (28) of IC604, respectively? NO Check IC604 and its peripheral circuits. Check the circuit between pins (79)/(80) of IC803 and pins (3)/(4) of IC604. Check IC801 and its peripheral circuits.
LC-30HV4E
NO
YES
NO
YES
NO
YES
NO
YES
Is SP-HD/SP-VD/SP-CP outputted to pins (16) , (28) and (15) of IC604, respectively? Check IC604 and its peripheral circuits.
NO
(AVC System)
58
Check the circuit between pins (16)/(28)/(15) of IC604 and pins (40)/(5)/(6) of IC1901. Check IC1901 and its peripheral circuits. Check the circuit between pins (34)/(35)/(33)/(31) of IC1901 and pins (1)/(2)/(31) of IC803. Check IC803 and its peripheral circuits. Check PC I/F Unit.
YES <SUB system> Is HD2/VD2 outputted to pins (9) and (4) of IC802, respectively? YES Is HD2/VD2 inputted to pins (19) and (20) of IC1901, respectively? YES Is HDS/VDS inputted to NO pins (21) and (22) of IC1901, respectively? YES Check IC1901 and its peripheral circuits. NO Check the circuit between pins (9)/(4) of IC1901 and pins NO Check IC802 and its peripheral circuits.
NO
YES
Is PL-HD/PL-VD/PL-CP/PL-HBLK outputted to pins (34) , (35), (33) and (31) of IC1901, respectively?
NO
YES
NO
YES
NO
YES
No picture
NO NO Check CN6 and its peripheral circuits. Is digital output section of IC4 normal? YES Check IC310 and its peripheral circuits. Is digital output of IC25 normal? YES NO NO Are TL207, TL208 and TL211 normal? YES Is digital output section of IC310 normal? YES NO
YES
NO
YES
NO
YES
(AVC System)
59
Is signal at pins (21), (22), (24), (25), (27), (28), (30) and (31) of IC413? (The signal is of high frequency (a little less than 1GHz). Pay due attention to it during observation.) YES NO Connecting cable or monitor is problem. PC I/F Unit (CPCi0056CE) internal problem is likely.
LC-30HV4E
LC-30HV4E
No Power
LCD LED: ON AVC-C LED: OFF LCD LED: OFF AVC-C LED: ON Check power switch, AC power cable and power unit of LCD.
LCD LED: BLINKING (Once per second) Check system cable, power switch, AC power cable and power unit of AVC-C.
LCD LED: BLINKING (4 times per second) Check cooling fan, IC2102 and peripheral circuits. LCD LED: ON IN RED AVC-C LED: ON IN RED
(Display)
60
LCD LED never turns to green. Check power switch, AC power cable and power unit of LCD. AVC-C LED never turns to green. Check power switch, AC power cable and power unit of AVC-C. LCD panel backlight never lights up. Reset the lamp error count. (See adjustment procedure.) Check Q6551, Q6554, Q6557, Q6560, Q6563, and Q6566 as well as peripheral circuits. Initialize EEPROM. (See adjustment procedure.) If not successful: Check power switch, AC power cable and power unit of LCD.
1No Picture
No 800-MHz signal input at pins (186), (187), (191), (192), (196) and (197) of IC2201.
Disconnect system cable and operate LCD independently. (Blue screen appears.) Check system cable, connector and peripheral circuits.
Faulty: Check IC4901 and peripheral circuits. Faulty: Check IC4551 and peripheral circuits.
2No Sound
(Display)
61
LC-30HV4E
LC-30HV4E
CHASSIS LAYOUT
H
(AVC System)
10
11
12
62
63
LC-30HV4E
CHASSIS LAYOUT
H
(Display)
10
11
12
64
65
LC-30HV4E
10
11
12
66
67
LC-30HV4E
10
11
12
68
69
LC-30HV4E
10
11
12
70
71
LC-30HV4E
10
11
12
72
73
LC-30HV4E
IC2202 HDCP( KEY) EEP -ROM KEY IIC DDC -IIC TMDS IC2201 TMDS RE CEIV ER
IC4901 O S DR IV E ( ODD)
IC4701 O S DR IV E( EV EN)
IC2002 RE SET
OFL CONTROL SC2202 DISPLAY IN P UT 2 IC2001 MICRO PROCESSOR Q6551 Q6554 Q6557 DC/AC IN VERTER DRIV E T6551 T6552 T6553 T6554 T6555 T6556 DC/AC TRANS BACK LIGH T Q6560 Q6563 Q6566 DC/ AC IN VERTER DRIV E T6557 T6558 T6559 T6560 T6551 T6562 DC/ AC TRANS
CONTROL KEY
IC3809 S-OUT A MP
IC3810 HE AD-PHONE A MP
10
11
12
74
75
LC-30HV4E
B+3. 3V CONT
B+2. 5V CONT
F
INVERTER GND MAIN ( TMDS/ MICOM) P2103 MB +9V FAN VCC IC2102 9V REG POWER CN5 PC +13V @ INVERTER1
FAN
E
+5V
P6907 MD AUDIO
P2106 MD
INV.VCC P6557 PG +2. 5V IC2105 2. 5V REG CN7 PE INVERTER2 P6564 PH +13V P2101 PB CN4 PB +13V INV.VCC
+10V
IC2103 5V REG
+3. 3V
IC2104 3. 3V REG
+13V
IC3801 9V REG
+9V
CN3 PA CN2 AA
STB+6V
+5V _STB
STB+6V
CN1 AC IN
P101 RM
10
11
12
76
77
LC-30HV4E
10
11
12
78
79
LC-30HV4E
10
11
12
80
81
LC-30HV4E
10
11
12
82
83
LC-30HV4E
CAUTION:
This circuit diagram is original one, therefore there may be a slight difference from yours.
84
LC-30HV4E
WAVEFORMS
1 2 3 4
85
LC-30HV4E
10
11
12
86
87
LC-30HV4E
10
11
12
88
89
LC-30HV4E
10
11
12
90
91
LC-30HV4E
10
11
12
92
93
LC-30HV4E
10
11
12
94
95
LC-30HV4E
10
11
12
96
97
LC-30HV4E
10
11
12
98
99
LC-30HV4E
10
11
12
100
101
LC-30HV4E
10
11
12
102
103
LC-30HV4E
10
11
12
104
105
LC-30HV4E
10
11
12
106
107
LC-30HV4E
10
11
12
108
109
LC-30HV4E
10
11
12
110
111
LC-30HV4E
10
11
12
112
113
LC-30HV4E
10
11
12
114
115
LC-30HV4E
H
D50 MA157A
R877 2 D51 MA157A R920 100 R921 100 C2 0.1uF C1 0.1uF HOTPLUG3 4 7 FLASHWP CLR_SW CCK CLR_SW CCK
10K SDA2O SCL2 TXD2 CTS2 TV_COL1 RXD0 TV_COL2 RXD2 RTS2 XPWR_SV 3 3 2 2 3 3 2 2 3 1.8432MH RXD1 TXD1 2 R1106 10K
K2 K1A2 A1
K2 K1A2 A1
TXD0
1.8432MH
SDA4O
SH_ON
3 VD+3.3
0.01uF
R1202 VD+3.3 15pF 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 R652 EXBV8V103J TL89 1 X1 6MHz 8 7 6 5 3 2 C12
R650
C9
10K
C7
C8
CKIO
AVSS AN7 AN6 AVCC AN5 AN4 AN3 AN2 AN1 AN0 AVSS MD5 MD4 MD3 CA RESETP DREQ1 DREQ0 PTD0 PTD1 PTC0 PTC1 PTC2 PTC3 PTD2 VCC PTD3 VSS PTC4 PTC5 PTC6 PTC7 SCPT7 VCC RXD2 VSS RXD1 RXD0 RTS2 SCK2 TXD2 SCK1 TXD1 SCK0 TXD0 VCC CKIO VSS IRQOUT PTH7 PTJ7 PTJ6
15pF
C13 VD+3.3
1 2 3 4
C14 0.01uF
5 6 7 8
7 8 9 10 11 12 13
NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 VSS PTB1 VCC PTB0 PTA7 PTA6 PTA5 PTA4 VSS PTA3 VCC PTA2 PTA1 PTA0 VSS D15 VCC D14 D13 D12 D11 D10 D9 D8 D7 D6 VSS D5 VCC D4 D3 D2 D1 D0 VCC VSS VSS PTH6 VCC CAP2 VSS VSS CAP1 VCC MD0 PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 PTF7 PTG0 VCC PTG1 VSS PTG2 PTG3 PTG4 PTG5 PTG6 PTG7 PTH5 RESETM WAIT BREQ BACK PTE0 PTE1 PTE2 PTE3 PTE6 DACK1 DACK0 PTJ5 PTJ4 VCC CASLH VSS CASLL RAS2L RAS3L CKE
IC1
SH-7709 RH-IX3270CEZZ
SCL1_A SDA1O
0.01uF C22 3 LMUTE SDA3O 3 AWCS_R 3 AWCS_W 7 -RST_PL 4 HVSEL D15 0.01uF C27 SCL4A 0.01uF C25 SCL3O
D
VD+1.8
14
R16
R17 33K
R18 2.2K(1%)
-RESET
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
R10 EXBV8V103J 4 3 2 1
R11 EXBV8V103J VD+3.3 MON_DET CLR_SW R340 10K R22 10K -ROMCS 4 3 2 1
470pF C19
0.01uF C21 C20 470pF CHECKER SDA2I FSTATUS 2 TL92 1 1 0.01uF C23 AWDATA KOUTEI SDA4I SDA_1 SDA3I 3 3 TL96 1 TL97 TXD0 14 IC400B 4 5 TC74LVX86FT 1 7 C908 TL94 1 TL95 TL93
5 6 7 8
1 2 3 4 5 6
EXTAL XTAL
156 155
R654 150
4 1
-CS0
TXD0_M
BREQ
-WAIT_C1
TL232 PAD2.0
RXD0
*
0.01uF C28
-DEBUG
3 3 3 3 6 3 3 2 2 2 2 6
TXD1_T
CASH CASL
RXD1
11 RXD1_T 3
A0 A1 A2 A3 VSS A4 VCC A5 A6 A7 A8 A9 A10 A11 A12 A13 VSS A14 VCC A15 A16 A17 A18 A19 A20 A21 VSS A22 VCC A23 VSS A24 VCC A25 PTK4 RD WE0 WE1 PTK6 PTK7 RD/WR PTE7 VSS CS0 VCC CS2 CS3 CS4 CS5 CS6 CE2A CE2B
VD+3.3 VD+3.3 R19 EXBV8V103J C800 0.1uF IC402 R924 4.7K R1058 4.7K 5 6 7 8 4 3 2 1
VD+3.3
0.01uF C34
0.01uF C35
0.01uF C36
0.01uF C37
0.01uF C38
2,5
D[15..0]
C532 0.01uF
2 5 9 12 1 4 10 13 14
1Y 2Y 3Y 4Y
3 6 8 11
SDA2I HOTPLUG3
SDA_1 SCL1
7 7
A24
A14
A22
A0 A1 A2 A3
A4
A23
A25
-WR/RD
-CS2
8 7 6 5
74LVX125MTC VD+3.3
R29 EXBV8V103J -CS6 -CS5 -CS4 -CS3 -CS2 -CS0 5 SCL4A 2 5 9 12 1 4 10 13 14 -WEH -WEL 2,5 2,5 2,5 C802 0.1uF IC404 1A 2A 3A 4A 1OE 2OE 3OE 4OE VCC 74LVX125MTC 1Y 2Y 3Y 4Y 3 6 8 11 SCL4 SDA4I SCL3 SDA3I R1059 4.7K R1062 4.7K R289 4.7K 1 2 3 4 TL230 1 SDA4O SCL3O SDA3O
VD+3.3
B
+ IC3 1 2 3 4 VD+3.3 C24 10uF/16V C26 0.01uF
REF.1XXXX
8 7 6 5
3 2
AT24C128N-10SI-2.7
A
SDA3I 1 2 3
-RD TL100
NDC7002N
10
11
12
116
117
LC-30HV4E
1.8432MH
3 2
4 C42 0.01uF
DSO751SV(1.8432M)
VD+3.3 VD+3.3
TL128 PAD3.5
1
R27 27K 4 5 6
1 FLWP
F
1,5 A[25..0] IC53C 8
8 7 6 5
IC53D 13 12 TC74LVX86FT 9
8 7 6 5
TC74LVX86FT 11
10
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
IC27
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CE# OE# WE# RST# WP# VPP RY/BY# NC
29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 26
D0 D1 D2 D3 D4 D5 D6 D7
8 7 6 5 8 7 6 5 5 6 7 8 4 3 2 1 5 6 7 8 1 2 3 4
R35 R36 EXBV8V103J EXBV8V103J D8 D9 D10 D11 D12 D13 D14 D15
1 2 3 4
28 11 12 14 13 15 47
VD+3.3DR
C43 C350 0.01uF
37 46 27
D
1 1 1,5 1 FSTATUS -RESET -RD -CS0
0.01uF
LH28F320BFE-PTTL80
R43 R44 EXBV8V103J EXBV8V103J
4 3 2 1 5 6 7 8
A1 A2 A3 A4 A5 A6 A7 A8
5 6 7 8
C
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
FL6 BLM31PG121SN1
G
VD+3.3
21 22 23 24 27 28 29 30 31 32
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
IC28
5 6 7 8
5 6 7 8
VD+3.3DR
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 WE RAS LCAS UCAS OE VSS VSS VSS
2 3 4 5 7 8 9 10 41 42 43 44 46 47 48 49 17 18 35 34 33 26 45 50
1 2 3 4
VD+3.3
4 3 2 1
4 3 2 1
C804 2.2uF/50V
+
IC405 uPD4721G 1 2 3 4 5 6 7 8 9 10 VDD C1+ VCC C1C5+ C5Din1 Din2 Rout1 Rout2 C4+ GND C4VSS STBY VCHA Dout1 Dout2 Rin1 Rin2 20 19 18 17 16 15 14 13 12 11
+
CN5
100 R928 100 R929 100 R930 100 1 FB50 2 BLM21BB201SN1 1 FB51 2 BLM21BB201SN1 1 FB52 2 BLM21BB201SN1 1 FB53 2 1 6 2 7 3 8 4 9 5
C807 2.2uF/50V
100uF/4V
NC NC NC NC NC NC NC MSM51V18165F
R62 EXBV8V100J
1 2 3 4
8 7 6 5
1 1 1 1
A
1,5 -WEL 1,5 -WEH
10
0.01uF
11
10
+ C361
C51
1 1 1 1
BLM21BB201SN1
11
JEY-9P-1A3F
12
118
119
LC-30HV4E
2
R1129 10K R1130 10K D79 MA157A
K2 K1A2 A1
H
CN6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FH12-30S-0.5SH SUB_Cr
TL207
SADC_OE5 5 6 7 8 R934 EXBV8V680J OVG0 5 4 4 OVG1 6 3 3 OVG2 7 2 2 OVG3 8 1 1 R936 EXBV8V680J OVG4 5 4 4 OVG5 6 3 3 OVG6 7 2 2 OVG7 1 8 1 R937 EXBV8V680J OVB0 5 4 4 OVB1 6 3 3 OVB2 7 2 2 OVB3 8 1 1 R939 EXBV8V680J OVB4 5 4 4 OVB5 6 3 3 OVB6 7 2 2 OVB7 1 8 1 R940 EXBV8V680J OVR0 5 4 4 OVR1 6 3 3 OVR2 7 2 2 OVR3 8 1 1 R941 EXBV8V680J OVR4 5 4 4 OVR5 6 3 3 OVR6 7 2 2 OVR7 1 8 1 OVR[7..0] 6 OVB[7..0] 6 OVG[7..0] 6
C698 0.47uF R883 0 Y_A_IN C538 3.27_RT 0.1uF 61 60 1 59 RT A CLPV A RB A CLP OUT A
63
A IN
IC310
VA+5_VDO
K2 K1A2 A1
SUB_Cb
D80 MA157A
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 -OE A BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 -OE B CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 -OE C
13 12 11 10 9 8 7 6 2 24 23 22 21 20 19 18 17 47 43 42 41 40 39 38 37 36 34 57 56 55 3 58
C537 10uF/16V
5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8
TL208
SUB_Y R885 0
C700 0.47uF
TL209
TL211
100K 0.1uF
MAIN_B
K2 K1A2 A1
MAIN_B
D81 MA157A
31 0.1uF 29 28 33 27
MAIN_G
MAIN_G
C544 0.1uF
C545 0.1uF
C546 0.1uF
C766
MAIN_R
MAIN_R
4 VD+5BK
TL212
VA+3_VDO TV_CL2CN TV_CL1CN SRESETCN KOUTEI ACL_SWCN IO_STB D_DATACN SH_ONCN CSEN2 SENCE 1 7 7 R1077 150(1%) +
45 46 4 26
CN7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE1 MODE0 TEST DVDD A AVCC B AVCC C AVCC QA DVDD QB DVDD QC DVDD CLPEN CLK EXTCLP NT/PAL INIT
R1099
OV1_VCKO OV1_CLP
6 6
C542 10uF/16V
10(1/10W)
VA+5_VDO
10uF/16V
62 51 30
0.1uF C551
0.1uF C552
0.1uF C553
C550
0.1uF C558
R911
0.1uF C557
10(1/10W)
8 7 6 5 CSEN1_I
EXBV8V560J
R677
470
64 49 32
+ C554 10uF/16V
15 5 25 44
GND_VDO
IC327A 1 NJM4560M 2
3.5V_SET
LMUTECN RESO3CN HPMUT1CN R1131 10K SCL3_5 SCL3_5 SDA3_5 1 1 R1132 100 1 2 3 4 IC316 K NC NC NC REF NC A NC 8 7 6 5 R678 1.2K(1%)
3 2
+ -
Q13 2SC2412KQ
R912
TLC5733A
VA+5 BMK351 FL10 1 I O 3
CSEN1_SH
3.5V_FB
SCL2_5 SDA2_5 SMPOW SCL1_5 SDA1_5 R1080 R1081 0 0 7 1 1 1 1 1,4 7 7 7 RXD1_T TXD1_T 1 1
TL431CPS
5 6
+ -
7 NJM4560M
2 2SA1037AKQ
IC327B
Q15
ACL_SIG R947
R682 1.2K(1%)
TL213 TL214
8 7 6 5
EXBV8V560J
1 2 3 4
VD+5
FH12-50S-0.5SH
VD+3.3 VA2933_1 FB18 0(1/10W) VA2933_2 FB19 1 2 3 4 5 6 7 IC328 LVDD VCOVDD TEST RBIAS VCOOUT VCOIN FINA VCOGND FINB VCOINH PFDOUT PFDINH LGND NC TLC2933IPW R730 680 C705 0.1uF(PF) 14 13 12 11 10 9 8 C715 0.01uF R743 1.8K
OV1_HSNR OV1_HSNF
6 6
IC408 1 1 1 1 1 1 AWCS_R AWCS_W HPMUTE1 RES_OUT3 LMUTE SADC_OE 2 4 6 8 11 13 15 17 1 19 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G
20
C813 0.1uF
74VHCT244AMTC 18 16 14 12 9 7 5 3 AWCS_RCN AWCS_WCN HPMUT1CN RESO3CN LMUTECN SADC_OE5 TV_CL1CN VD+5BK D88 1 RB521S-30 2 + C741 47uF/6.3V
Vcc
1 TV_COL1
22
C706 0.022uF
R731 620
R1083 1K C904 0.1uF IC419 IO_STB R1085 10K 1 2 3 4 A Vcc B RX/CX CLR CX GND Q 8 7 6 5
R1084 10K
C717 0.01uF
TL215
OV1_PDEN
GND
1
C913 C905 0.1uF(K) 1 2 3 4 G1 A1 Y2 GND
10
8 7 6 5
8 7 6 5
TC7WH123FK
CSEN2
1 2 3 4
1 2 3 4
CSEN2 PC_V
7 4 OV1_VCLK 6
B
IC410 1 1 1 1 1 1 1 TV_COL2 ACL_SW SRESET XPWR_SV SM_RST FLS_W SH_ON 2 4 6 8 11 13 15 17 1 19 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G
20
C814 0.1uF
74VHCT244AMTC TV_CL2CN ACL_SWCN SRESETCN SRST SH_ONCN XPWR_SVO SRST FLASH_W CSEN1 4 7 7 7 1 SDA2O 1 SCL2 IC422 1 DAC_CLK 1 DAC_DATA 2 5 9 12 VD+5 1 4 10 13 14 C916 0.1uF 1A 2A 3A 4A 1OE 2OE 3OE 4OE VCC HD74HCT125T 1Y 2Y 3Y 4Y 3 6 8 11 D_CLKCN D_DATACN SDA2_5 SDA2_5 SCL2_5 1,4 4 R1110 4.7K R925 4.7K
CSEN1_I
18 16 14 12 9 7 5 3
Vcc
R955 EXBV8V682J
1 2 3 4
10
GND
8 7 6 5
10
11
12
120
121
LC-30HV4E
VA-5-AMP
VA-5-AMP
C144 47uF/10V(PXA-5)
C757 4.7uF/10V(2125)
GND
C84 33uF/10V
K2 K1A2 A1
D82 MA157A
TL225 1 6 OV0_HSNR
K2 K1A2 A1
D84 MA157A
R869 0 C62 0.1uF 3 VA+5-AMP 2 1 2 1 2 D87 MA157A 3 1 K2 K1A2 A1 K2 K1A2 A1 D85 MA157A D86 MA157A
CN8
S12B-PH-SM3-TB 1 2 3 4 5 6 7 8 9 10 11 12 PC_G PC_B PC_R PC_H PC_V PC_C C921 100uF/6.3V(PXA) C907 0.1uF 2 3 5 6 11 10 14 13 1 15 1A 1B 2A 2B 3A 3B 4A 4B +
K2 K1A2 A1
0 0 0
C562 0.1uF C563 0.1uF C565 0.1uF D78 2 1SS380 1 C128 0.33uF(PF) 330pF(CH) C127 100pF C126 1uF(K) C131 0.1uF VA+5-PLL
OV0_PDEN
VD+3.3 TL218 1 TL219 1 TL220 1 C136 0.1uF C135 0.1uF C134 0.1uF R132 3.3K(1%) C566 C130 100pF R133 3K(1%) C132 1uF(K)
16
1 3 D9 1SS187 1
CLR_SW PC_V
R1089
100
3 3
MAIN_HD MAIN_VD
VCC
A/B G
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND
VI VC
VO VADJ
VA+3.3AD
C564 100uF/6.3V(PXA)
3
VD+5 L4
IC8 PQ20VZ11
XPWR_SVO
C133 0.1uF
GND
TL83 1
BOUT0 ROUT0
C110 0.1uF 1,3 3 SDA2_5 SCL2_5 C112 0.1uF C111 0.1uF C115 0.1uF C113 1uF(K) C114 0.1uF
C
7 ROUT0 ROUT0
6 7 OGOUT0 OGOUT0
7 BOUT0
BOUT0
RB3 RB4 RB5 RB6 RB7 DVCCADTTL DGNDAD3 DGNDADTTL BA0 BA1 BA2 BA3 BA4 DGNDAD3 BA5 BA6 BA7 DVCCADTTL DGNDADTTL BB0 BB1 BB2 DGNDAD3 BB3 BB4 BB5 BB6 BB7 DVCCADTTL DGNDAD3 DGNDADTTL GA0 GA1 GA2 GA3 GA4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DAC TEST OUT G/YOUT AGNDAMPR R/CrIN2 AVCCAMPR R/CrIN1 DPGND AGNDAMPB B/CbIN2 SOGIN2 AVCCAMPB B/CbIN1 SOGIN1 DPGND R/CrCLP B/CbCLP G/YCLP AGNDAMPG G/YIN2 AVCCAMPG G/YIN1 AGNDIR DPGND IREF AVCCIR RC2 RC1 AGNDVCO AVCCVCO DGNDPLL DVCCPLL CLPIN SYNCIN2 SYNCIN1 CLKIN XCLKIN
B/CbOUT ADDRESS R/CrOUT NC NC XPOWER SAVE DGNDREG DVCCREG SDA SCL XSENABLE SEROUT 3WIRE/IIC DPGND AVCCADREF AVCCAD3 VRT DVCCAD3 DVCCADTTL DGNDADTTL RA0 RA1 DGNDAD3 RA2 RA3 RA4 RA5 RA6 AGNDAD3 DGNDAD3 RA7 DVCCADTTL DGNDADTTL RB0 RB1 RB2
IC4 CXA3506R
EVEN/ODD XTLOAD HOLD SOGOUT XUNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK CLK XCLK DGNDPLLTTL DVCCPLLTTL AGNDADREF AVCCAD3 VRB DVCCAD3 DVCCAD DVCCADTTL DGNDADTTL GB7 GB6 DGNDAD3 GB5 GB4 GB3 GB2 GB1 AGNDAD3 DGNDAD3 GB0 DGNDADTTL DVCCADTTL GA7 GA6 GA5
EVENODD
6 6
VD+5-ADC C122 1uF(K) 0.1uF C123 C121 0.1uF LC0GI1B7 LC0GI1B6 LC0GI1B5 LC0GI1B4 LC0GI1B3 LC0GI1B2 LC0GI1B1 LC0GI1B0 C120 0.1uF LC0GI1A7 LC0GI1A6 LC0GI1A5 LC0GI1B3 LC0GI1B2 LC0GI1B1 LC0GI1B0 5 6 7 8 R960 LC0GI1B7 LC0GI1B6 LC0GI1B5 LC0GI1B4 5 6 7 8 5 6 7 8 4 3 2 1 4 3 2 1 OGI1B7 OGI1B6 OGI1B5 OGI1B4 LC0GI1A7 LC0GI1A6 LC0GI1A5 LC0GI1A4 5 6 7 8 R961 5 6 7 8 4 3 2 1 4 3 2 1 OGI1A7 OGI1A6 OGI1A5 OGI1A4 OGI1A[7..0] 6 0.1uF C124 OGI1B[7..0] 6 VA+3.3AD
EXBV8V680J R963 5 6 7 8 4 3 2 1 4 3 2 1 OGI1B3 OGI1B2 OGI1B1 OGI1B0 LC0GI1A3 LC0GI1A2 LC0GI1A1 LC0GI1A0
EXBV8V680J R966 LCBI1B7 LCBI1B6 LCBI1B5 LCBI1B4 5 6 7 8 5 6 7 8 4 3 2 1 4 3 2 1 BI1B7 BI1B6 BI1B5 BI1B4
EXBV8V680J BI1B[7..0] 6
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
R965 EXBV8V680J
BI1A[7..0]
0.1uF
0.1uF
0.1uF
VD+5-ADC
EXBV8V680J R969 LCBI1B3 LCBI1B2 LCBI1B1 LCBI1B0 BI1B3 BI1B2 BI1B1 BI1B0
C117
C118
C119
EXBV8V680J R970 LC0GI1A0 LC0GI1A1 LC0GI1A2 LC0GI1A3 LC0GI1A4 LCBI1A3 LCBI1A2 LCBI1A1 LCBI1A0 5 6 7 8 5 6 7 8 4 3 2 1 4 3 2 1 BI1A3 BI1A2 BI1A1 BI1A0 5 6 7 8
5 6 7 8
4 3 2 1
4 3 2 1
EXBV8V680J
EXBV8V680J
10
11
12
122
123
LC-30HV4E
IC25A
MCLK
179
R688
MCLK
R692 R694
0 R693 0 R695 0 0
XCS XRAS XCAS XWE R689 DQM[7..0] DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 470 VD+3.3CV
SDA[10..0]
SDA_0 SDA_1 SDA_2 SDA_3 SDA_4 SDA_5 SDA_6 SDA_7 SDA_8 SDA_9 SDA_10 SDA_11 SDA_12 SDA_13 SDD_0 SDD_1 SDD_2 SDD_3 SDD_4 SDD_5 SDD_6 SDD_7 SDD_8 SDD_9 SDD_10 SDD_11 SDD_12 SDD_13 SDD_14 SDD_15 SDD_16 SDD_17 SDD_18 SDD_19 SDD_20 SDD_21 SDD_22 SDD_23 SDD_24 SDD_25 SDD_26 SDD_27 SDD_28 SDD_29 SDD_30 SDD_31 SDD_32 SDD_33 SDD_34 SDD_35 SDD_36 SDD_37 SDD_38 SDD_39 SDD_40 SDD_41 SDD_42 SDD_43 SDD_44 SDD_45 SDD_46 SDD_47 SDD_48 SDD_49 SDD_50 SDD_51 SDD_52 SDD_53 SDD_54 SDD_55 SDD_56 SDD_57 SDD_58 SDD_59 SDD_60 SDD_61 SDD_62 SDD_63
51 164 269 367 270 165 52 271 166 53 368 457 54 167 61 63 64 65 66 67 178 68 376 463 375 279 278 277 173 275 69 70 181 71 72 73 74 75 383 288 287 286 285 379 378 377 276 459 372 373 460 374 461 541 281 280 177 176 175 174 62 172 464 466 380 467 381 382 469 470 186 185 184 183 182 284 180 282
SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10
SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SD_BA0 SD_BA1 R696 10K
25 26 27 60 61 62 63 64 65 66 24 22 23 68 67 20 19 18 17
IC319
1 -RST_C1 1 -WAIT_C1 1 -C1_INT 1 CKIO 1 1,2 1,2 1,2 -CS2 -RD -WEL -WEH
VD+3.3 SD_BA0 SD_BA1 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDD16 SDD17 SDD18 SDD19 SDD20 SDD21 SDD22 SDD23 SDD24 SDD25 SDD26 SDD27 SDD28 SDD29 SDD30 SDD31 SDD32 SDD33 SDD34 SDD35 SDD36 SDD37 SDD38 SDD39 SDD40 SDD41 SDD42 SDD43 3
FL94 BMK351 O I
G
C573 100uF/4V
V_DRAM1 +
3 9 35 41 49 55 75 81 6 12 32 38 46 52 78 84 1 15 29 43 44 58 72 86
VccQ VccQ VccQ VccQ VccQ VccQ VccQ VccQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ Vcc Vcc Vcc Vcc Vss Vss Vss Vss
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3
C574 100uF/4V
2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59
SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDD16 SDD17 SDD18 SDD19 SDD20 SDD21 SDD22 SDD23 SDD24 SDD25 SDD26 SDD27 SDD28 SDD29 SDD30 SDD31 DQM0
SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SD_BA0 SD_BA1 R697 10K
25 26 27 60 61 62 63 64 65 66 24 22 23 68 67 20 19 18 17
IC320 DQ1
DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3
DQ0
VD+3.3 3
FL95 BMK351 O I 1 + V_DRAM1 3 9 35 41 49 55 75 81 6 12 32 38 46 52 78 84 1 15 29 43 44 58 72 86 VccQ VccQ VccQ VccQ VccQ VccQ VccQ VccQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ Vcc Vcc Vcc Vcc Vss Vss Vss Vss
2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59
SDD64 SDD65 SDD66 SDD67 SDD68 SDD69 SDD70 SDD71 SDD72 SDD73 SDD74 SDD75 SDD76 SDD77 SDD78 SDD79 SDD80 SDD81 SDD82 SDD83 SDD84 SDD85 SDD86 SDD87 SDD88 SDD89 SDD90 SDD91 SDD92 SDD93 SDD94 SDD95 DQM4 DQM5
0.1uF C575
0.1uF C576
0.1uF C577
DQM1
NC NC NC NC NC NC NC
14 21 30 57 69 70 73
0.1uF C583 0.1uF C584 0.1uF C585 0.1uF C586
0.1uF C578
NC NC NC NC NC NC NC
14 21 30 57 69 70 73
0.1uF C579
0.1uF C580
0.1uF C581
0.1uF C582
D
SDD84 SDD85 SDD86 SDD87 SDD88 SDD89 SDD90 SDD91 SDD92 SDD93 SDD94 SDD95 SDD96 SDD97 SDD98 SDD99 SDD100 SDD101 SDD102 SDD103 SDD104 SDD105 SDD106 SDD107 SDD108 SDD109 SDD110 SDD111 SDD112 SDD113 SDD114 SDD115 SDD116 SDD117 SDD118 SDD119 SDD120 SDD121 SDD122 SDD123
HY57V653220BTC-7
HY57V653220BTC-7
SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SD_BA0 SD_BA1 R698 10K
25 26 27 60 61 62 63 64 65 66 24 22 23 68 67 20 19 18 17
IC321 DQ0
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3
V_DRAM1
3 9 35 41 49 55 75 81 6 12 32 38 46 52 78 84 1 15 29 43 44 58 72 86
VccQ VccQ VccQ VccQ VccQ VccQ VccQ VccQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ Vcc Vcc Vcc Vcc Vss Vss Vss Vss
2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59
SDD32 SDD33 SDD34 SDD35 SDD36 SDD37 SDD38 SDD39 SDD40 SDD41 SDD42 SDD43 SDD44 SDD45 SDD46 SDD47 SDD48 SDD49 SDD50 SDD51 SDD52 SDD53 SDD54 SDD55 SDD56 SDD57 SDD58 SDD59 SDD60 SDD61 SDD62 SDD63 DQM2
SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SD_BA0 SD_BA1 R699 10K
25 26 27 60 61 62 63 64 65 66 24 22 23 68 67 20 19 18 17
IC322 DQ1
DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3
DQ0
V_DRAM1
3 9 35 41 49 55 75 81 6 12 32 38 46 52 78 84 1 15 29 43 44 58 72 86
VccQ VccQ VccQ VccQ VccQ VccQ VccQ VccQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ Vcc Vcc Vcc Vcc Vss Vss Vss Vss
2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59
SDD96 SDD97 SDD98 SDD99 SDD100 SDD101 SDD102 SDD103 SDD104 SDD105 SDD106 SDD107 SDD108 SDD109 SDD110 SDD111 SDD112 SDD113 SDD114 SDD115 SDD116 SDD117 SDD118 SDD119 SDD120 SDD121 SDD122 SDD123 SDD124 SDD125 SDD126 SDD127 DQM6 DQM7
0.1uF C589
0.1uF C590
0.1uF C591
SDD44 SDD45 SDD46 SDD47 SDD48 SDD49 SDD50 SDD51 SDD52 SDD53 SDD54 SDD55 SDD56 SDD57 SDD58 SDD59 SDD60 SDD61 SDD62 SDD63
DQM3
NC NC NC NC NC NC NC
14 21 30 57 69 70 73
0.1uF C597 0.1uF C598 0.1uF C599 0.1uF C600
0.1uF C592
NC NC NC NC NC NC NC
14 21 30 57 69 70 73
0.1uF C593
0.1uF C594
0.1uF C595
0.1uF C596
HY57V653220BTC-7
HY57V653220BTC-7
CVIC2
SDD[127..0]
10
11
12
124
125
LC-30HV4E
RI1A0 RI1A1 RI1A2 RI1A3 RI1A4 RI1A5 RI1A6 RI1A7 OGI1A0 OGI1A1 OGI1A2 OGI1A3 OGI1A4 OGI1A5 OGI1A6 OGI1A7 BI1A0 BI1A1 BI1A2 BI1A3 BI1A4 BI1A5 BI1A6 BI1A7 RI1B0 RI1B1 RI1B2 RI1B3 RI1B4 RI1B5 RI1B6 RI1B7 OGI1B0 OGI1B1 OGI1B2 OGI1B3 OGI1B4 OGI1B5 OGI1B6 OGI1B7 BI1B0 BI1B1 BI1B2 BI1B3 BI1B4 BI1B5 BI1B6 BI1B7
104 213 214 315 408 493 317 318 485 400 307 206 96 399 306 205 404 311 488 403 310 209 100 99 103 314 407 405 312 102 210 101 398 305 204 95 304 203 94 93 402 309 208 401 308 207 98 97 320 412 494 216 105 106 215 316 107 409 113 221
V0_RA0 V0_RA1 V0_RA2 V0_RA3 V0_RA4 V0_RA5 V0_RA6 V0_RA7 V0_GA0 V0_GA1 V0_GA2 V0_GA3 V0_GA4 V0_GA5 V0_GA6 V0_GA7 V0_BA0 V0_BA1 V0_BA2 V0_BA3 V0_BA4 V0_BA5 V0_BA6 V0_BA7 V0_RB0 V0_RB1 V0_RB2 V0_RB3 V0_RB4 V0_RB5 V0_RB6 V0_RB7 V0_GB0 V0_GB1 V0_GB2 V0_GB3 V0_GB4 V0_GB5 V0_GB6 V0_GB7 V0_BB0 V0_BB1 V0_BB2 V0_BB3 V0_BB4 V0_BB5 V0_BB6 V0_BB7
IC25B
4 OGI1A[7..0]
DO_RA0 DO_RA1 DO_RA2 DO_RA3 DO_RA4 DO_RA5 DO_RA6 DO_RA7 DO_RA8 DO_RA9 DO_GA0 DO_GA1 DO_GA2 DO_GA3 DO_GA4 DO_GA5 DO_GA6 DO_GA7 DO_GA8 DO_GA9 DO_BA0 DO_BA1 DO_BA2 DO_BA3 DO_BA4 DO_BA5 DO_BA6 DO_BA7 DO_BA8 DO_BA9 DO_RB0 DO_RB1 DO_RB2 DO_RB3 DO_RB4 DO_RB5 DO_RB6 DO_RB7 DO_RB8 DO_RB9 DO_GB0 DO_GB1 DO_GB2 DO_GB3 DO_GB4 DO_GB5 DO_GB6 DO_GB7 DO_GB8 DO_GB9 DO_BB0 DO_BB1 DO_BB2 DO_BB3 DO_BB4 DO_BB5 DO_BB6 DO_BB7 DO_BB8 DO_BB9
355 354 257 152 39 256 151 38 150 37 446 357 445 356 259 154 41 258 153 40 448 359 262 358 261 156 43 260 155 42 361 264 159 449 360 263 158 45 157 44 452 363 266 161 451 362 265 160 47 46 366 365 268 163 50 364 267 162 49 48 36 35 149 254 148 225 114 222 322 414 218 406 313 410 227 224 324 415 499 110 6 7 122 323 575 253 351 146 255 33 147 236 129 15 16 427 336 130 131 497 212 487 397 303 418 500 518 34 17 335 132 239 238 237 19 18 DCLKIN R978 R979 R980 0 0 0
5 6 7 8 5 6 7 8
R971 EXBV8V330J RSI2 5 4 4 RSI3 6 3 3 RSI4 7 2 2 RSI5 8 1 1 R972 EXBV8V330J RSI6 5 4 4 RSI7 6 3 3 RSI8 7 2 2 RSI9 8 1 1 R973 EXBV8V330J OGSI2 8 1 1 OGSI3 7 2 2 OGSI4 6 3 3 OGSI5 4 5 4 R974 EXBV8V330J OGSI6 5 4 4 OGSI7 6 3 3 OGSI8 7 2 2 OGSI9 8 1 1 R975 EXBV8V330J BSI2 8 1 1 BSI3 7 2 2 BSI4 6 3 3 BSI5 4 5 4 R976 EXBV8V330J BSI6 8 1 1 BSI7 7 2 2 BSI8 6 3 3 BSI9 5 4 4
RSI[9..2]
OGSI[9..2]
8 7 6 5 5 6 7 8 8 7 6 5 8 7 6 5
4 BI1A[7..0]
G
4 RI1B[7..0]
BSI[9..2]
4 OGI1B[7..0]
F
4 BI1B[7..0]
R977
10K
V0_PVDCLK V0_NVDCLK V0_VDCLK_I V0_VAL V0_HSYNC V0_VSYNC V0_CSYNC V0_GSYNC V0_HSYNC2 V0_ACT V0_PVCLK V0_NVCLK
TL222
TL112
TL113
3 OVR[7..0]
CVIC2
OVR0 OVR1 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 OVG0 OVG1 OVG2 OVG3 OVG4 OVG5 OVG6 OVG7 OVB0 OVB1 OVB2 OVB3 OVB4 OVB5 OVB6 OVB7 108 217 411 496 109 319 219 220 10 11 126 233 332 234 333 424 5 121 229 8 123 230 329 421 321 413 118 112 228 327 328 419 120 111 115 223 117 3 4 119 226 325 326 417 V1_RA0 V1_RA1 V1_RA2 V1_RA3 V1_RA4 V1_RA5 V1_RA6 V1_RA7 V1_GA0 V1_GA1 V1_GA2 V1_GA3 V1_GA4 V1_GA5 V1_GA6 V1_GA7 V1_BA0 V1_BA1 V1_BA2 V1_BA3 V1_BA4 V1_BA5 V1_BA6 V1_BA7 V1_PVDCLK V1_NVDCLK V1_VDCLK_I V1_VAL V1_HSYNC V1_VSYNC V1_CSYNC V1_GSYNC V1_HSYNC2 V1_ACT V1_PVCLK V1_NVCLK V1_RB0 V1_RB1 V1_RB2 V1_RB3 V1_RB4 V1_RB5 V1_RB6 V1_RB7 V1_GB0 V1_GB1 V1_GB2 V1_GB3 V1_GB4 V1_GB5 V1_GB6 V1_GB7 V1_BB0 V1_BB1 V1_BB2 V1_BB3 V1_BB4 V1_BB5 V1_BB6 V1_BB7
DO_HSYNC DO_VSYNC DO_HDISP DO_VDISP DO_FEILD V0_VDCLK_O V0_PADCLK V0_NADCLK V0_PADRST V0_NADRST V0_CLP V0_HSYNR V0_HSYNF V0_PDEN V1_VDCLK_O V1_PADCLK V1_NADCLK V1_PADRST V1_NADRST V1_CLP V1_HSYNR V1_HSYNF V1_PDEN BIASIN_VI BIASOUT_VI BIASIN_DO BIASOUT_DO DCLK LCLK LCLKP LCLKN S0_D0 S0_D1 S0_D2 S0_D3 S1_D0 S1_D1 S1_D2 S1_D3 IPD MCK_REF PLL_S PLL_TEST MST XTST SMCK XSM IMODE INITO INITI CPUS_0 CPUS_1 CPUS_2 CPUS_3 CCS_0 CCS_1
7 1,7 1,7
1 2 29 30 31 32 58 59 60 87 88 89 116 283 338 344 352 353 433 443 455 482 484 501 502 503 506 507 510 511 514 515 519 520 521 522 525 526 529 530 533 534 538 539 540 544 545 548 549 552 553 557 558 559 563 564 567 568 571 572 576
IC25C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH
504 505 508 509 512 513 516 517 523 524 527 528 531 532 535 536 542 543 546 547 550 551 554 555 561 562 565 566 569 570 573 574 171 337 343 420 423 426 428 429 432 434 435 438 439 441 442 444 447 450 453 454 456 458 462 465 468 471 474 477 483 486 489 492 495 498 560
C815 0.1uF C816 0.1uF C817 0.1uF C818 0.1uF C819 0.1uF C820 0.1uF C821 0.1uF C822 0.1uF C823 0.1uF C824 0.1uF C825 0.1uF C826 0.1uF C827 0.1uF C828 0.1uF C829 0.1uF C830 0.1uF TP10 PAD1.6 C831 0.1uF C832 0.1uF C833 0.1uF C834 0.1uF C835 0.1uF C836 0.1uF C837 0.1uF C838 0.1uF C839 0.1uF C840 0.1uF C841 0.1uF C842 0.1uF C843 0.1uF C844 0.1uF VD+5 C845 0.1uF FL205 NFM21PC105B1A3D VD+5IN 3 O I 1 + C847 100uF/6.3V VA+5 FL206 NFM21PC105B1A3D VA+5IN 3 O I 1 TP11 PAD1.6 TP12 PAD1.6 TP13 PAD1.6
TL122
CVIC2
PCVICPLL OV0_CLP OV0_HSNR OV0_PDEN OV1_VCKO 4,7 4 4 3 VD+3.3 OV1_CLP OV1_HSNR OV1_HSNF OV1_PDEN 3 3 3 3 C846 R1134 47 1uF 490 A_VSS 491 A_VDD
D
3 OVB[7..0]
3 OVG[7..0]
C848 0.1uF
CN9
S13B-PH-SM3-TB 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13
2 G
VD+3.3IN
TL114
+ C366 100uF/6.3V(PXA)
3 OV1_VCLK
FL98 33(1/10W) 1 3
C851 100uF/6.3V(PXA)
+ V-5
3 OV1_H 3 OV1_V
LCLK
7 VGA_OE VD+3.3 X6 3 2 OUT VDC GND Cntl 4 1 + C919 0.01uF VD+1.8 FL31 BMK351 3 O I 1 3 FL32 O BMK351 C759 0.01uF I VD+2.5CV C854 47uF/16V C853 0.01uF C15 10uF(3225) VD+5BK 1 C852 47uF/6.3V + VA+12
DSO751SV(25.175M)
X5
3 2
4 1
VD+3.3
12 127 13 128 235 334 425 14 9 124 231 330 125 232 331 422
+ C367 100uF/6.3V(PXA)
C10 10uF(3225)
91.3M
WXGA_OE
VD+3.3
R1201 100
DSO751SV(25.000M)
10
11
3 FL30 O BMK351
C850 100uF/6.3V(PXA)
12
126
127
LC-30HV4E
FL201
G
BLM31PG121SN1
2
C855 82pF
10uF/16V
VD+5BK R1101 3 3 3 3 CSEN1 CSEN2 SRST FLASH_W 5 6 7 8 4 3 2 1 CSEN1CN CSEN2CN SRSTCN FLASHWCN CCKM TXD0CN RXD0CN SMPOWCN SENCECN
CN1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SM15B-SRSS-TB
VD+5
BLM31PG121SN1
O
1 1 3 3
2 R1009 2.2K
C858
FWMODEN
82pF
6 6
RSI[9..2]
RSI2 RSI3 RSI4 RSI5 RSI6 RSI7 RSI8 RSI9
V_SII_VA
OGSI[9..2]
CN3
HOOK1
H1
BSI[9..2]
F
VD+3.3 IC412 1 2 3 VC GND NR PQ1R33 C868 0.1uF VIN GND1 VO 6 5 4
VD+5
D75 1SS187 DV_TXD11 3 2 V_SII OGSI5 OGSI4 OGSI3 OGSI2 BSI9 BSI8 BSI7 BSI6 BSI5 BSI4 BSI3 BSI2 6 LCLK 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PVCC2 D11 D10 D9 D8 D7 D6 IDCKIDCK+ D5 D4 D3 D2 D1 D0 GND C872 0.1uF C864 82pF
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PGND2 D12/DUAL D13/MASI D14/SYNCO D15 D16 D17 D18 D19 D20 D21 D22 D23 GND RESERVED VCC
DV_TXD0DV_TXDC+ 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C865 82pF DV_TXD2+ DV_TXD2DV_TXD1+ DV_TXD1C870 82pF DV_TXD0+ DV_TXD0DV_TXDC+ DV_TXDCR999 C875 82pF 510 C876
+ C867 10uF/16V
C869 0.1uF
H2
IC413
SiI170
VCC DE VREF HSYNC/SYNC1 VSYNC DK3 DK2/MDA DK1/MCL EDGE/CHG PD MSEN VCC ISEL/RST DSEL/SDA BSEL/SCL GND
AGND TX2+ TX2AVCC TX1+ TX1AGND TX0+ TX0AVCC TXC+ TXCAGND EXT_SWING PVCCI PGND1
HOOK2
D2D2+ D2/4SH D4D4+ DDC_CLK DDC_DATA AVSYN D1D1+ D1/3SH D3D3+ +5V GND HOTPD D0D0+ D0/5SH D5D5+ CLKSH CLK+ CLKRED GREEN BLUE AHSYNC AGND AGND
2 4 6 8 10 12 14 16 18 20 22 24 C2 C4 C6
DV_TXD2+
HOTPLUG
VD+5 FL204
G 2
VD+5DVI
74320-1007
BMK351
VD+5BK 0.1uF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R1002 R1003
D
TL223 PAD1.6 TL224 PAD1.6
1 1
TL231 PAD1.6
1
1,6 6 1,6 1 1 1 1
100 100
NDC7002N
R1007 1K
C879 82pF
ROUT0
OGOUT0
B
BOUT0 4
R1042 1K
R1043 1K
R1044 1K
10
11
12
128
129
LC-30HV4E
10
11
12
130
131
LC-30HV4E
10
11
12
132
133
LC-30HV4E
10
11
12
134
135
LC-30HV4E
10
11
12
136
137
LC-30HV4E
10
11
12
138
139
LC-30HV4E
10
11
12
140
141
LC-30HV4E
10
11
12
142
143
LC-30HV4E
10
11
12
144
145
LC-30HV4E
10
11
12
146
147
LC-30HV4E
10
11
12
148
149
LC-30HV4E
150
LC-30HV4E
151
LC-30HV4E
10
11
12
152
153
LC-30HV4E
154
LC-30HV4E
155
LC-30HV4E
10
11
12
156
157
LC-30HV4E
158