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Embedded Software Design 25

The document is a past exam paper for a microcontroller course. It contains two questions regarding the PIC16F84 microcontroller. Question 1 asks about various components of the microcontroller including the Function Select Register (FSR), EEPROM, Return from Subroutine (RPO) instruction, and instruction pipeline. Question 2 discusses dividing the crystal oscillator frequency to calculate the instruction cycle rate, writing a program to set memory locations to zero using indirect addressing, explaining the difference between Special Purpose Registers (SPRs) and General Purpose Registers (GPRs), and listing advantages of mirrored registers. Tables are provided defining the instruction set and special function registers of the PIC16F84.

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Gamindu Udayanga
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56 views

Embedded Software Design 25

The document is a past exam paper for a microcontroller course. It contains two questions regarding the PIC16F84 microcontroller. Question 1 asks about various components of the microcontroller including the Function Select Register (FSR), EEPROM, Return from Subroutine (RPO) instruction, and instruction pipeline. Question 2 discusses dividing the crystal oscillator frequency to calculate the instruction cycle rate, writing a program to set memory locations to zero using indirect addressing, explaining the difference between Special Purpose Registers (SPRs) and General Purpose Registers (GPRs), and listing advantages of mirrored registers. Tables are provided defining the instruction set and special function registers of the PIC16F84.

Uploaded by

Gamindu Udayanga
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Sri Lanka Institute of Information Technology

B.Sc. Special Honours Degree


In

Information Technology
(Computer Systems & Networking)

Mid-term Examination Year 2, Semester 2 (2009)

Embedded Software Design (252)


Duration: 1 Hour Thursday, 6th August 2009 (Time 11.00 a.m. - 12.00 noon)
Instructions to Candidates: This paper has 2 questions. Answer All Questions. Total Marks: 20. This paper contains 2 pages with cover page. PIC] 6F84 Instruction set and the SPR summary is provided separately. Retain these for subsequent lectures. Calculators are not allowed.

Page 1

1.

[Total:8 marks]

Write concise notes on the following to show your understanding of the function and operation in respect of the PIC 16F84 microcontroller. You may use a diagram to support your description. Hint: You may indicate - What is it? Where is it located? What is its function? a) FSR b) EEPROM c) RPO d) Instruction Pipeline

2.

[Total:12 marks] (a) In a PIC Microcontroller crystal oscillator frequency Jose is divided by 4 in order to calculate the instruction cycle rate. Explain using a diagram, why this is done. [Total:4 marks] (b) Write a program, which will set the memory area from h'20' to h'2f to 0 using indirect addressing. [Total:4 marks]
(c) Explain the difference between SPRs and GPRs.

[Total:2 marks] (d) What are the advantages of mirrored registers? Give at least 2 examples. [Total:2 marks] - End of paper-

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TABLE 21:

SPECIAL FUNCTION

REGISTER

FILE SUMMARY
Value on

Aclclr
Bank 0 00r01tit\OF

Name

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

Power-On
RESET

Details on paae

Uses cooten.s of FSR 10 acorsss Data Mel'1ory (no: a physical reQister) 8-bit Real-Time ClocklCounter Low Order 8 brts of the Program Counter (PC) IRP RP1 R?O TO RA4lTOCKI RB4 PO

- - -- - - -xxxx xxxx
0000 0000

11 20 11

TMRO PCL STATUS(2) FSR PORTAI"I PORTS(61

021'
03h

Z
RA2 RS2

DC
RA1

04h Ol)h 0511

Indirect Data Mem~ry Address Pointer 0

RB7

RB6

RB5

RA3

RB3

RB1

lxxx xxxx xxxx RAO ---x xxxx RBDIINT XXXX xxxx


0001

,... '-,

e
11 16 18

OTh

EDATA EEADR PCL.l..TI-I INTCON INDF OPTION_REG PCl


STATUS
(2)

Unimptsmanted

location. read as '0'

xxx.x
XXX):

13.14 13.14 11 10 11

OBr
Otm
OA.h aSh

EEPROM Da1a Register =:::PROM Address Register

xxxx xxxx
Wrtte Buffer for upper 5 bits of the INTE RBIE TGIF

GIE

EEIE

TOlE

ce

Ci) RsrF

- --0 OCi00

0000

INTF regIster) PS1

'JOOx
- -- 1111 0000

Bank 1

801'
81r 82n

Uses Contents of FSR to address Dat;] Memory (not RBPU INTEDG TaCS TOSE PSA

a physical
PS2

- --PSO
1111 0000

9
11

low order 8 bits or Program Counter (PC}


IRP RP1 ROO TO PD Z DC C Indirect da:a memory address poi!':er 0

8.2or~,4r

occi
>:XXX - --1 1111

FSR -RISA 7RISB

lXX>: xxxx
1111 1111

e
11 16 18

8:~
85r
87h SSt'

EEIE

PO"T.,), Data Direction Regl$;sr

PORTB Data Direc.ion Register Unimplemented focation. read as '0'

WRERR 'NREN \'VR RD


---0

13 14 11 10

E:::CON1 EECON2 PClATH INTCON

GIE

TOlE

EEIF

xecc
.. ......
01)(,0

89"
OAll aSh

:::EPROM Control Register 2 (not a physical iaglster) Wnte buffer for upper 51lilS of !he PCP) JNTE RBIE TGIF INTF RBfF
..

.. _ .....
- --0 0(1)1)

'JO('X

Legend: x unknown. u uncoanceo. - = unlrnpternented, read as G'. q = value depends on condition Note 1: The oper by~eof the oroqrari counter Is not directly accessible. PCLA.TH is a slave register for PC<-12:8:o, The contents o PCLAJH can be transferred :0 the upper I)yte otthe oroora counter, but the contents of PC<12:8> are never transferred to ::>CLATH. 2: The TO and PO status bits in t ,e STATUS register are not affected b)' a MCLR Reset. 3: Other ( .on POW6Htp) RESETS include: extemal RESET through MC R and the watc dog Timer Reset 4: On any device RESET, these pins are configured as inp is. 5: TI)is Is the value U1a! will t)e JIl the con output latch.

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TABLE 7-2:

PIC16CXXX INSTRUCT10N

SET
14-Bit Opcocle Status Affected

II

Mnemonic, Operands

Description

Cycles MSb LSb

Notes

BYTEORIENTED ADD'NF A.f\D'/'.'F CL~F CL~'lv' C:JMF 'OECF OECFSZ INCF INCFSZ IOR'NF MOVF

FILE REGISTER

OPERATIONS
00 0111 0101

f. d

t. d
f

Add \IV anc f ."'NO W with f Clear r


Clear .",~

r. d
f.d f. d f. d f. d Cd f. d f

Como-emeut f
Decre'nen: Decremer,! f ', Sl<;;p if

1 1 1 1 1 1 1 (2) 1 1 12) 1 1 1 1 1 1 1 1

00
00 C'O 00

c-io r
0001 1001 0011 1')11 1,nD 1111 C'100 100e'
OOQO

00 00
00 C'O 00 00 00 00

MOV.'.F
il<OP
RL=

.
f. d f. d f.d f..d

RR"
SlB"'''''F S'IV:"PF XO~'I;F

Increment f Increment f. Skip if 0 Inclusive OR W wim f Mo\>e f Move'N to f No ooerauon Rotate Leftf through Carry Rotate Rlgh: f through Carfy Subtract W from f Swap nibbles in r Exdusive OR VI/ wl:h f BITORIENTED FILE REGISTER

dfff ffff c.uff ffff lttf fft!: xxxx 0= dfff fiff drff fftf dfff ffff dftf ffff dfff ffff dfff ffff dfff ffff Iff! tfff

C,OC,l

1.2 1.2

Z
Z

2
1.2 1,2

Z
Z

1.2.3

Z Z
Z

1.2

1.2.3
1.2 1,2

OOOD 1101 1100 0010 1110 011D

oxxo
dffE dfff dfff dfff dfft

(01)0

00
0) 00 00 00

r. d
f.b

Efff ffff fffE fffE ffff

C
C C.DC.l

1,2 1,2 1.2 1,2 1,2

OPERATIONS 1
01 01

BCF 8SF BTfSC BTFSS

f. b
L b

f.1l

Bit Bit Bit Bit

Clear r Set f Test f, Skip if Clear Test t, Skip if Set LITERAL AND CONTROL

1 1 [2J
1 (2)

01
01

CObo olbb lobb


11bb

pfff

bfff bfff
PffE

fHf fiff
ffff

1,2 1.2

ffff
C,DC,l Z TOPO

3 3

OPERATIONS 1
11

ADDL.."V AI\0 L'""


CALL CLR.'NDT GOTO IORLV'; r.Ir)VL'JI . RETFIE RET_.. R~T.JR" SLEEP SLSL"N XORLW Note

~
i<
1.;

1i

~ ~
><:

.
k

Ad~ literal and W AND lite 3' With "f'.' Call subroutine Clear V\,a:chOog T~mer Go to address Inclusive OR. 'iteralwith '."" r''''o~e literal to '/,' RI:i:urn rrorn imerrIJpt Re:u"n with 1i:eraln '1'1 Re:urn from subrocane Go ';1110 standl)Y Mode Subtract .. "'. frOM !rleral Excillsi'/e OR literal with V,,'

lllX
1001

11
10 0'1 10 11 11

2
1

ckkk
0000 1Jd:k 1000

lckkk kkkk kkkk kkkk kkkk kkkk


011Q DI00

2
1 1
2

kkkk
kkkk kr...kk
0000

ooxx
0(1)0 OllO'. 0,)00

kkkk JI'.kkk kkkk


1001

COO
11

2
2
1 1 1

kkkk
0000

kklck
1000

00
00 11 11

oco o 0110 i i ox kkkk


1010

0011

TOPD

kkkk

kkkk kkkk

C,DC.l Z

1: wnen an 110 register JS~odlfled as J functton ()f itself:: e.:;).,NOVE' PORTS. 1), the value used Will be that ... alue oreser: on the oins themselves. For example. if ~r,e oa:a latch is '1' for a p'n configured as inpu and is driven 10\1. I)y an e.<t..:rnal
2: 3: device, ~he oata Will be written bacK with a '0'. If .rns instruction is executed on 1'e TMRO register (and, wr-ere applicable. 0 = 1). the prescaler will oe cleared if Jssigned to :he T.merO MOdule. If .:>:-ogram Counter (PC) is modffied or a conditional test is true. the mstrucuon requires two cycles. The second cycle is executed as a J-!<)P

Page 4

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