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CMOS Comparators

The document discusses comparator design, including an ideal comparator, deviations from ideality including transient response and DC errors, an idealized case using identical balanced stages, practical design considerations focused on overload recovery and offset removal, and CMOS implementations focusing on load designs and offset nulling strategies.

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guitarfrido
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
89 views

CMOS Comparators

The document discusses comparator design, including an ideal comparator, deviations from ideality including transient response and DC errors, an idealized case using identical balanced stages, practical design considerations focused on overload recovery and offset removal, and CMOS implementations focusing on load designs and offset nulling strategies.

Uploaded by

guitarfrido
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

CMOS Voltage Comparator Design

Ideal

Comparator Deviations from ideality Idealized View of Comparator Design Practical Design Issues

PRG, VCs, 1

Ideal Comparator
Analog input (vi+-vi-) vi+ V. C. viDigital output Latch signal Latch signal Properties: Zero offset Zero delay
not valid valid compared value

Digital output

PRG, VCs, 2

Important Deviations from Ideality


1. Transient Response

PRG, VCs, 3

Deviations from Ideality, Contd


2. DC Errors

vi

Vos V. C. Digital output

viLatch signal Key Parameters: Delay time: td = f(Vinit, Vod) Metastability Vos, PSRR, CMRR

PRG, VCs, 4

Consider an Idealized Case


Chain of identical, Balanced Stages:

Assumptions:
Large Rl, idealized device Only Cgs matters, Cgd=0, Cdb=0 Balanced condition at t=0 Devices behave approximately linearly
PRG, VCs, 5

Example SPICE Simulated Result (Soo, 1984)

Voltage output of Nth Stage, Vin = 10mV

Time, sec

PRG, VCs, 5.1

Idealized Case, Contd


Result:

Final Conclusion: t
=

dmin

1.2

v out ln v id

tot g m

C
=

+C gs p g m

C 1 1+ p 2f C t gs

Delay same as regenerative latch!


vo/vin = 1000, Cp<<Cgs PRG, VCs, 6

Effective ft vs. Channel Length Silicon MOSFET


10 9 8 7 Approximate 6 Value of NMOS 5 Device ft, Ghz 4
(Assumes bias point of Vgs-VT = 0.5V)

3 2 1 0.8u 5u 3u 2u 1.5u 1.2u 1u Drawn Channel Length


PRG, VCs, 7

0.6u

93

PRG, VCs, 8

When is Comparator Performance a Factor?


ADC type Serial Sigma-Delta Successive Approximation Flash Half-Flash Pipeline Vos No No Usually no Yes Yes No Delay No Usually opamp limited Yes Yes Yes Yes

PRG, VCs, 9

Key Design Considerations

How

many stages before latch? How to do Vos cancellation if needed How to realize common-mode biasing Whether to precharge nodes to balanced state How many latch stages needed to control metastability

PRG, VCs, 10

Practical Design Considerations


Dominated by 2 issues
Overload Recovery Offset removal

General Considerations:
Cant use simple latch- Offset usually too high

vi+ G viEnough Stages to realize required offset voltage

digital output

Latch

PRG, VCs, 11

The Overload Recovery Problem

Vin

V1

V2

V3

Vod
Vin

Vinit Vlatch
Vout

time V1 V2 V3

PRG, VCs, 12

Example Simulation Results, Overload Recovery (Soo, 1984UCB)


Resistor Loaded Inverters, gmRl=5 Vinit = -5V

Voltage at nth stage output, Volts

Time, sec
PRG, VCs, 13

Design approaches:
1. Use small values of Rl
Minimizes swing Shortens time constant

2. Use Passive Clamps


Limits Swing Adds parasitics

3. Use active nulling clamps


Good in principle Tough clock generation problem

PRG, VCs, 14

Design of Low-Rl Comparators in MOS


(Soo, 1984, UCB)

Conclusion:
Nonlinear Problem, no analytical solution Best empirical results with gmRl around 4-8 Optimum number of stages 4-6 Result: 5-10x slower than pre-nulled case

Ref: Soo, PhD, UCB, 1984 PRG, VCs, 15

CMOS Implementations
Poly or Diffusion loads- large tolerance and parasitics (Allstott, JSC, 6/82) Enhancement loads- Drop large voltage PMOS Triode loads- small parasitics, can use replica bias

Triode

Can be constant or PTAT to give desired TC to delay

Vref

Bias Ref

PRG, VCs, 16

Offset Nulling Strategies


1. Input Nulling Capacitors w/feedback
Caps must be big to control chg injection, Parasitics in signal path

2. Interstage Nulling Caps


Parasitics in signal path

3. Auxiliary input stage


Minimal loading of signal path Slow in actual nulling cycle Best is nulling duty cycle is low

Refs: Yee, JSC, 6/78;Allsott JSC 12/82, Degrauwe, JSC6/85 PRG, VCs, 17

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