VLSI Implementation of Adders for High Speed d ALU

Prashant Gurjar, Rashmi Solanki Pooja Kansliwal UG Scholar, Dept. EC, GGITM, Bhopal, India Email: prashantgurjar84@gmail. .com
ABSTRACT
This paper is primarily deals the constructio on of high speed adder circuit using Hardware Description L Language (HDL) in the platform Xilinx ISE 9.2i and impl lement them on Field Programmable Gate Arrays (FPGAs) to analyze the this investigation design parameters. The motivation behind t is that an adder is a very basic building bloc ck of Arithmetic Logic Unit (ALU) and would be a lim miting factor in performance of Central Processing Unit (CP PU). In the past, thorough exami ination of the algorithms with the respect to particular technology has only been partially done. The merit of the new technology is to be evaluated by its ability to efficiently implement the computational algorithms. In the other words, the technology is developed with the aim to e efficiently serve the computation. The reverse path; evaluat ting the merit of the algorithms should also be taken. T Therefore, it is important to develop computational structu ures that fit well into the execution model of the processor an nd are optimized for the current technology. In such a case, optimization of s the critical path the algorithms is performed globally across of its implementation. In this research article, we have e simulated and der, ripple carry synthesized the various adders like full add adder, carry-look ahead adder, carry-skip p adder, carry select adder and carry-save adder by using VHDL and Xilinx ISE 9.2i. The simulated results are verified and the functionality of high speed adders and the parameters like area and speed is analyzed. Finally this p paper concludes that the carry-save adder is the more efficie ent in speed and area consumption. KEYWORDS: High Speed Adder, Field d Programmable Gate Array, Carry Skip Adder, Carry Sele ect Adder, Carry Save Adder.

Mahendra Vucha Asst. Prof, Dept. EC, GGITM, Bhopal, India Email: Mahendra.1548@gm mail.com
other kinds of processors, adders are used not only in the ALU(s), but also in other parts of o the processor, where they are used to calculate addresses, table indices, and many more.

1.2 CONCEPT OF ADDERS

Consider two binary variables x and d y. the binary sum is denoted by x+y, such that 0+0 = 0 0+1 = 1 1+0 = 1 1+ +1 = 10 Here, the result in the last case is a binary b 10(i.e., 2 inbase 10). The sum of two numbers can be out of the range of the digits in binary set. This, of course e, is the origin of the concept of a carry out. In the binary sum 1+1, the result 10 is viewed as a 0 with a 1 shifted to th he left to give a carryout is 1.

1.3 HALF ADDER

A half adder is a logic circuit th hat performs one-digit addition. It requires two inputs, and th he output is the sum of

r Figure 1. Half adder the inputs. The logic diagram of HA is i shown in figure 1. ry numbers A and B. It A HA adds two one-bit binar has two outputs, S and C (the value C theoretically carried on to the next addition).The simpl lest half-adder design, shown in figure 1, incorporates an a XOR gate for S and an AND gate for C. The Boolean eq quation and Truth table of half adder is shown bellow. (i) S = A XOR B C = A AND B (ii) or half adder Table 1. Truth table fo Input A 0 0 1 1 B 0 1 0 1 C 0 0 0 1 Output S 0 1 1 0

1.

INTRODUCTION

Digital computer ALU is an aspect of logic c design with the objective of developing appropriate algorit thms in order to achieve an efficient utilization of the avai ilable hardware. The hardware can only perform a relativ vely simple and primitive set of Boolean operations an ndthe arithmetic operations are based on a hierarchy of ope erations that are built by using algorithms against the h hardware. Since, ultimately, speed, power and utilization o of ALU are the most often used measures of the efficiency o of an algorithm.

1.1 WHAT IS AN ADDER

In digital electronics, adder is a di igital circuit that performs addition of two numbers. In many y computers and

1.4 FULL ADDER

A Full Adder (FA) is a logical circuit th hat performs an addition operation on three binary digits. The full adder produces a sum and a carry value, which are both binary digits. The logical diagram of full adder is shown in figure 2.

used to generate the i-th bit of the sum, si, and a carry, s called a Ripple Carry ci+1, to the next adder stage. This is Adder (RCA), since the carry signal ripple from the least s The layout significant bit position to the most significant. of a ripple carry adder is simple, wh hich allows fast design time. However, the ripple carry add der is relatively slow, since each full adder must wait for the carry bit which is . The RCA is shown in coming from the previous full adder. figure. 3.

Figure 2. Full adder or values carried A FA adds binary numbers and accounts fo in as well as out. A one-bit full adder ad dds three one-bit numbers, often written as A, B, and Ci he ere A, B are the operands, and Ci is a bit carried in (in the eory from a past addition). The circuit produces a two-b bit output sum typically represented by the signals Co (Car rry) and S(Sum). the Boolean equation and truth table is show wn bellow. S = A XOR B XOR Ci (iii)

Figure 3. Ripple carry y adder

2.2 CARRY - LOOK AHEAD ADDER A

A significant speed improvement in the implementation of a parallel adder was introduced by a Carry-Look aheadheoretically one of the Adder (CLA). The CLA adder is th fastest schemes used for the addition n of two numbers, since the delay to add two numbers depen nds on the logarithm of the size of the operands. Carry look k ahead logic uses the concepts of generating (G) and prop pagating (P) carries. Its work is based on two signals called d P and G for each bit position. The P and G are shown bellow. Ci+1 = Gi + Pi.Ci Here, Gi = Ai.Bi and Pi = (Ai Bi) Si = Ai Bi Ci = Pi Ci. C The Si and Ci+1 represent the sum and carry from ith full ahead adder can be adder respectively.The carry-looka broken up in two modules: (1) The Pa artial Full Adder, PFA, which generates Si, Pi and Gi. (2) The T Carry Look-ahead Logic, which generates the carry-out t bits. The structure of CLA for 4-bit adderis shown in figure 4.

OR (CiAND A) Co = (A AND B) OR (B AND Ci) O (iv) dder Table 2. Truth table for full ad A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1 Sum 0 1 1 0 1 0 0 1

A FA can be constructed by cascading of two HA.The HA and the sum A and B are connected to the input of first H of first HA is connected as one input al long with Ci to second HA and it give SUM output. The logical OR of first ARRY output of and second HAs carry outputs a gives CA FA.

2. COMPLEX ADDERS:
The reference to eve of adding single bits, lets extend it to adding binary words. In genera al, adding two nbit words yields an n-bit sum and a carry y-out bit Cn.The carry is carried from lower bit adder to h higher bit adder. Based on carry transfer from LSB to MSB B, the adders are classified.

2.1 RIPPLE CARRY ADDER:

A ripple carry adder for N-b bit numbers is implemented by concatenating N full adde ers as shown on Figure 3. At the i-th bit position, the i-th bit ts of operands A and B and a carry signal from the preceding g adder stage are

Figure 4: Carry Lookah head adder

3. IMPLEMENTATION OF HSA:
The alternate approaches for designing High Speed Adders (HSA) have been designed in the literature he objective of [1], [2], [3], [4]. All of them have th decreasing the computation time and diff fferent tradeoffs. This paper examines few of them bellow.

3.1 CARRY SKIP ADDER

Since the Cin-to-Cout represents the long gest path in the ripple-carry-adder an obvious attempt is to accelerate carry propagation through the adder. This is a accomplished by using Carry-Propagate pi signals within a group of bits. If all the pi signals within the group are pi = 1, the condition p. exist for the carry to bypass the entire group P(i,i+3) = Pi+3. Pi+2.P i+1.Pi Using the individual propagate values, the output from the tage output of AND gate is ORed with Ci+4 to produce a st Carry = Ci+4 + P(i,i+3). Ci

Figure 6. Carry Select t Adder The higher order bits a7 a6 a5 a4 and b7b6 b5 b4 are used as he sum with a carry in two 4-bit adders. Adder calculates th of C=0, while the other adder does the same only it has a carry-in value of C=1. Both sets of o results are used as inputs to an array of 2:1 MUXs. The e carry bit C4 from the first adder is used as the select signal to MUX. If C4 = 0, t to the output, while a then the result of C=0 adder are sent value of C4=1 selects the result of C= =1 adder for S7 S6 S5 S4. The carry-out bit C8 is also selected by b the MUX array.The design speeds up the addition of the e word by allowing the upper and lower portions of the sum to be calculated s that it requires an simultaneously. The price paid is additional word adder, a set of multi iplexers and associated interconnect wiring. The design beco omes viable if speed is more important than area consumptio on.

3.3

CARRY SAVE ADDE ER

Carry save adder are based on the e idea that a full adder Figure 5. Carry skip adder n the carry-out of As shown in the figure 5, if P(i,i+3) = 0, then the group is determined by the value of Ci+4. However, if P(i,i+3) = 1, then the carry-in bit is Ci= 1, then the group group of adders. carry-in is automatically send to the next g The name carry-skip is due to the f fact that if the condition P(i,i+3). Ci is true and then the carry y-in bit skips the block entirely.

3.2 CARRY SELECT ADDER

The Carry Select Adder (CSL LA) divides the words to be added into blocks and forms tw wo sums for each block in parallel (one with a carry in of ZER RO and the other with a carry in of ONE) The carry out is computed using , since the group the equation for the carry out of the group, propagate signal Pi is the carry out of an ad dder with a carry input of ONE and the group generate Gi signal is the carry O. This speeds-up out of an adder with a carry input of ZERO ary for selection the computation of the carry signal necessa in the next block. The upper 8-bits are computed plexer (MUX) is conditionally using two CSLAs. A multip then used to select the valid result. The fig gure 6 shows the block diagram of CSA. As a concrete example, consider r an 8-bit adder that is split into two 4-bit groups. The lowe er order bits a3 a2 a1 a0 and b3 b2 b1 b0 are fed into the 4-bit a adder to produce the sum bits S3 S2 S1S0 and a carry-out bit C4 as shown. ve Adder Figure7.Carry Sav really has three inputs and produces two outputs as shown. t third input with While it is usually associates the a carry in, it could equally well be used as a regular 3 reduction network value. The full adder is used as 3:2 where it starts with bits from 3 bits words, adds them and de. An n-bit carry save then has an output that is 2-bits wid adder can be build by using n separ rate adders. The name carry-save arises from the fact that t we save the carry out words instead of using it immediatel ly to calculate the final sum. Carry-save adders are useful in i situations where we need to add more than two numb bers. Since the design automatically avoids the delay in the carry-out bits.

4 RESULT AND DISCUSSIONS

The design of high speed adders is necessary to increase the computation speed of ALU and it supports to design of high speed processor. In this research, the hardware implementation of various adders has been done to analyze the speed and area. The RTL code has been written in VHDL, Xilinx ISE 9.2i is used to simulate and synthesize the design. The simulation helps to verify the design and the synthesis report gives the speed and area of the design. Finally, the VLSI implemented designs are targeted to the COMPARISON OF ADDERS: 32-bit adders: Table 3: synthesis report of 32-bit adders S.No. 1. 2. 3. 4. 5. 6 Parameter XOR (1-bit) No. of Slices Levels of Logic CPU Processing Time Memory Usage Logic Delay Route Delay Total Delay Ripple carry 32 37/960 34 4.68 s 174924 KB 23.859 ns 14.806 ns 38.665 ns Carry-look ahead 64 37/960 34 4.59 s 174988 KB 23.859 ns 14.806 ns 38.665 ns Carry-skip 64 42/960 27 4.34 s 175948 KB 17.440 ns 9.402 ns 26.842 ns Carry-select 48 51/768 20 3.40 s 134356 KB 14.081 ns 15.774 ns 29.855 ns Carry-Save 31 19/768 3 2.71 s 167716 KB 6.103ns 1.721ns 7.824ns FPGA device xc3s500e-5-ft256 and captured the real time speed and area of the designs. The comparison table is shown in bellow. The table 3, 4, 5 and Figure 8 shows synthesis report of 32 bit adder, synthesis report of 16 bit adder, synthesis report of 8 bit adder and speed comparison of various adders respectively.The figure 8 represents the comparison chart by taking speed in MHz on Y axis and various adders on X axis.

16-bit adders:

Table 4: synthesis report of 16-bit adders S.No. 1. 2. 3. 4. 5. 6 Parameter XOR (1-bit) No. of Slices Levels of Logic CPU Processing Time Memory Usage Logic Delay Route Delay Total Delay Ripple carry 16 18/960 18 3.77 s 140796 KB 14.067 ns 7.623 ns 21.69 ns Carry-look ahead 32 18/960 18 3.555 s 140796 KB 14.067 ns 7.623 ns 21.69 ns Carry-skip 32 21/960 15 4.67 s 141820 KB 11.316 ns 5.326 ns 16.642 ns Carry-select 24 22/768 16 3.66 s 134356 KB 12 ns 11.163 ns 23.163 ns Carry-Save 31 10/768 3 3.97s 133404 KB 6.103ns 1.721ns 7.824ns

5.3.2

8-bit adders: Table 5: Synthesis report of 8-bit adders

S.No. 1. 2. 3. 4. 5. 6

Parameter XOR (1-bit) No. of Slices Levels of Logic CPU Processing Time Memory Usage Logic Delay Route Delay Total Delay

Ripple carry 8 9/960 10 3.453 s 139772 Kb 9.171 ns 4.032 ns 13.203 ns

Carry-look ahead 16 9/960 10 3.44 s 139772 Kb 9.171 ns 4.032 ns 13.203 ns

Carry-skip 16 11/960 9 3.44 s 140796 Kb 8.254 ns 3.286 ns 11.54 ns

Carry-select 12 11/768 9 2.945 s 134356 Kb 8.977 ns 6.945 ns 15.922 ns

Carry-Save 15 5/768 3 3.70 133404KB 6.103ns 1.721ns 7.824ns

100 80 60 40 20 0 8 - Bit adder 16 - Bit adder 32-Bit adder Ripple carry Carry-look ahead Carry-skip Carry-select Carry-save

Figure 8. Speed (in MHz) comparison chart of adders

5. CONCLUSION
The research article describes about the hardware implementation of high speed adders. In this paper, the various adders like full adder, ripple carry adder, carry-look ahead adder, carry-skip adder, carry select adder and carry- save adeer have been simulated and synthesized on Xilinx ISE 9.2i platform and their parameters are captured. Finally, the captured parameters like speed and area are compared for 8 bit, 16-bit adders and 32-bit adders. From the table 5, this paper concludes that the carry-save adder is the efficient adder in speed and area consumption. The analysis in table 6 for 32 bit adder is shown below. Table 6: Speed & Area analysis for 32 bit adder Adder Ripple Carry Adder Carry-look ahead adder Carry-skip adder Carry-select adder Carry-save adder Speed ( MHz) 25.8 25.8 37.2 33.4 127.8 Area ( XOR gate) 32 64 64 48 63

6. REFERENCES
[1]Bruce Shriver and Bennett Smith, The Anatomy of a High- Performance Microprocessor, IEEE Computer society Press, Los Alamitos, CA, 1998. [2] James M. Feldman and Charles T. Retter, Computer Architecture, McGraw-Hill, New York, 1994. [3] Ken Martin, Digital Integrated Circuit Design, Oxford University Press, New York, 2000. [4] BehroozParhami, Computer Arithmetic, Oxford University Press, New York, 2000. A comprehensive, in depth treatment of the subject. [5] David A. Patterson and John L. Hennessy, Computer Organization & Design, 2nd edition, MorganKoufmann Publishers, San Fransisco, 1998. [6] Jan M.Rabaey, Digital Integrated Circuits, Prentice Hall, Upper Saddle River, NJ, 1996. [7] AbdellatifBellaouar and Mohamed I.Elmasry, Lowpower Digital VLSI Design, Kluwer Academic Publishers, Norwell, MA, 1995. [8] William Stallings, Computer Design and Architecture, 4th Edition, Prentice Hall, Upper Saddle River, NJ, 1996. [9] John P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic Publishers, Norwell, MA, 1999.

[10] Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, 2nd edition, Addision-Wesley, Reading, MA, 1993. [11] Wayne Wolf, Modern VLSI Design, 2nd edition, Prentice Hall PTR, Upper Saddle River, NJ, 1998. 7. ACKNOWLEDGEMENT The authors would like to express my gratitude to the following people for their support in the work leading to this report: Dr. P.S. Venkataramu, Principal, GGITM, who has been the driving force behind this paper. Mrs. VibhaTiwari, HOD, EC Dept., GGITM, Bhopal, India, for her academic support. Mr. Mahendra Vucha, Asst. professor, EC Dept. &project guide, provided much inspiration to usthrough out of this paper. AshutoshAgrawal, my classmate and friend, never seemed to lose faith that the paper would be eventually completed. 8. AUTHORS BIOGRAPHY PrashantGurjarworkingfor hisB.E degree at Gyan Ganga Institute of Technology and Management, Dept. of Electronics and communication Engineering, Bhopal (M. P), India.. His areas of interest are Embedded System Design and VLSI Technologies. RashmiSolankiworkingfor herB.E degree at Gyan Ganga Institute of Technology and Management, Dept. of Electronics and communication Engineering, Bhopal (M.

P), India.. Her areas of interest are Embedded System Design. PoojaKansliwalworkingfor herB.E degree at Gyan Ganga Institute of Technology and Management, Dept. of Electronics and communication Engineering, Bhopal (M. P), India.. Her areas of interest are Embedded System Design. Mahendra Vucha received his B. Tech in Electronics & Communication Engineering from JNTU, Hyderabad in 2007 and M. Tech degree in VLSI and Embedded System Design from MANIT, Bhopal in 2009. He is currently working for his Ph. D degree at MANIT and also working as Asst. Prof in Gyan Ganga Institute of Tech & Mgmt, Dept. of Electronics and Communication Engineering, Bhopal (M.P), India. His areas of interest are Hardware Software Co-Design, Analog Circuit design, Digital System Design and Embedded System Design.