VIT UNIVERSITY, VELLORE SCHOOL OF ELECTRONICS ENGINEERING M.TECH.
VLSI DESIGN CUSTOM IC DESIGN LAB FALL 2012-13 VIVA-QUESTIONS Max Marks: 20 Answer ALL questions 1. What happens to delay if you increase load capacitance? 2. What are the limitations in increasing the power supply to reduce delay? 3. What happens if we increase the number of contacts or via from one metal layer to the next? 4. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 5. Why dont we use just one NMOS or PMOS transistor as a transmission gate? 6. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD 7. Why should the number of CMOS transistors that are connected in series be reduced? 8. While trying to drive a huge load, driver circuits are designed with number of stages with a gradual increase in sizes. Why is this done so? What not use just one big driver gate? 9. In a simple inverter circuit, if the pmos in the Pull-Up Network is replaced by an nmos and if the nmos in the Pull-Down Network is replaced by a pmos transistor, what is the design? 10. What is the effect of gate voltage on mobility? 11. If given a choice between NAND and NOR gates, which one would you pick? Explain. Time: 30 minutes
12. Draw a transistor level two input NAND gate and perform the sizing for equal rise and fall times. 13. Find the functions X and Y implemented by the following circuit
14. What are design rules? Why is metal- metal spacing larger than poly -poly spacing. 15. Consider the following figure.
Identify the region of operation and voltage range of VDS and VGS. 16. Find the function, F, implemented by the following circuit
17. In the transfer characteristics of a inverter, P(Vin = 1.2V, Vout = 2.6V) & Q(Vin = 1.4, Vout = 0.4V) are the points at which the slope is -1. Calculate the Noise Margin NML. 18. In the transfer characteristics of a inverter, P(Vin = 1.2V, Vout = 2.6V) & Q(Vin = 1.4, Vout = 0.4V) are the points at which the slope is -1. Calculate the Noise Margin: NMH. 19. Draw transistor level schematics for the complex logic static CMOS logic cell AOI221. Clearly label the inputs, the output, Vdd and Gnd. 20. The flowing figure shows the pass transistor logics with NMOS and PMOS. Level the source and drain of the circuits, and calculate the Vout of the circuits
