THE CLASS D AMPLIFIER DESIGN

A thesis Submitted in partial fulfillment of the requirements

For the Award of the Degree of
MASTER OF TECHNOLOGY
IN
VLSI TECHNOLOGY

Under the Esteemed Guidance of

Dr. KAUSHIK SAHA
Group manager
ST Microelectronics Pvt. Ltd.
Greater Noida-201308

By
A.RUDRESH
(100137007)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SCHOOL OF ENGINEERING AND TECHNOLOGY
SHARDA UNIVERSITY
GREATER NOIDA -201306

10SETM.Tech (VLSI) 0011

MAY-2012

Dedicated to my
Parents &
Teachers

Declaration

I hereby that the thesis entitled with THE CLASS D AMPLIFIER DESIGN submitted to school of
engineering and technology, SHARDA UNIVERSITY, for requirements of the degree of
MASTERS OF TECHNOLOGY in VLSI TECHNOLOGY is the result of original research work carried
out under supervision of DR.KAUSHIK SAHA Group manager ST microelectronic .I have not
submitted the same in part or full to this university or to any other university for the award of
any other degree or diploma.

GREATER NOIDA
Date

RUDRESH ARAVAPALLI

CERTIFICATE

This is to certify that the dissertation entitled THE CLASS D AMPLIFIER DESIGN submitted by
RUDRESH ARAVAPALLI (100137007) in partial fulfillment for the requirements for the award of
the degree of MASTER OF TECHNOLOGY in VLSI TECHNOLOGY to the SCHOOL OF
ENGINEERING AND TECHNOLOGY, SHARDA UNIVERSITY, GREATER NOIDA, is bona fide record
of the work carried out by him under my supervision and guidance.

Dr. KAUSHIK SAHA

(Supervisor)
Group manager
ST Microelectronics Pvt. Ltd.
Greater Noida-201308

SUBJECT APPROVED
(Dr. KAUSHIK SAHA)
Supervisor
Group manager
ST Microelectronics Pvt. Ltd.
Greater Noida-201308
U.P. India

FORWARDED
(Dr. MAHIPAL JAIN)
Dean
School of Engineering & Technology
SHARDA UNIVERSITY
Greater Noida-201308
U.P. India

ACKNOWLEDGEMENTS
As I hold the finished thesis in my hand, it gives me great pleasure to thank the many people
who make this journey possible. My utmost gratitude goes to my Supervisor Dr. KAUSHIK SAHA
for believing in me and taking me under his wing. His enthusiasm for new ideas,
encouragement and sound advice inspired me to think outside the box and made this M.TECH
an exciting intellectual adventure.
I am indebted to Dr. Rajeev K. SRIVASTAVA, Group Manager, HED, ST Microelectronics
Pvt. Ltd., Greater Noida , for generously providing some of the most essential resources to
conduct this study.
I would also like to thank Prof. R.M.MEHRA, Emeritus Professor, School of Engineering &
Technology, Sharda University, Greater Noida, helping shape this study.
A special; thanks to Mr. PRATEEK SIKKA, ST Microelectronics Pvt. Ltd., Greater Noida (U.P)
for their guidance during some critical moments in this study.
I would like to thank my friends for providing a fun environment in which to learn and grow.
Lastly and most importantly, I would like to thank the people closest to me; my family
members for their love, wisdom and support in my most difficult times. To them I dedicate this
thesis.

RUDRESH ARAVAPALLI

ABSTRACT

Audio amplifiers play an important role in every system that involves audible sound. General
power amplifiers till recently have been very inefficient, bulky and unreliable. Though Class AB
amplifiers have major market share in the audio industry because of their efficiency compared to
previous classes of amplifiers such as Class A and Class B, recent demand for smaller devices
with longer battery life has resulted in replacement of class AB amplifiers(linear amplifiers) with
Class D(switching amplifiers). Class D amplifiers provide the balance between efficiency and
distortion required by portable devices, hi-fi audio systems, as they utilize the switching
operation where the transistors are either fully on or fully off resulting in amplification with zero
power dissipation ideally.

The main focus of this thesis is to design a CLASS D AMPLIFIER with the specification of
30W power, 8ohm load, 20 kHz cutoff frequency, and required 95 % efficiency. The design uses
the complementary MOSFETs, the comparator and the filter values to balance the audio wave
with low distortion. This audio amplifier is implemented with +/-15V dc battery and the desired
simulation results are obtained on cadence ORCAD 16.0 with 95% efficiency.
Further, based on the need to improve area consumed by the battery, I have tried to implement
amplifier with the dual power supply by using center tap full wave rectifier also. As designers in
the future will be switching to Class D amplifiers because of the recent advances in switching
amplifiers, an effort was made to develop the thesis so as to be able to serve as a basic reference
guide which gives them a good understanding of existing architectures, challenges in efficient
power amplifier design, modulation methods, power stage topologies and implementation of
Class D amplifiers. A detailed study of parameters and parasitic that affect the performance of
class D amplifiers has been carried out with design, implementation, and simulation of various
stages. Various component selection decisions and layout issues have been discussed for an
efficient, EMI free, low distortion class D amplifier.

Table of Contents
Abstract
Acknowledgements
Chapter 1: Introduction
1.1 Motivation...............................................................................................................1
1.2 Linear vs. Switch Mode...........................................................................................1
1.3 Class A Amplifier.....................................................................................................2
1.4 Class B Amplifier.........................................................................................................3
1.5 Class AB Amplifier..................................................................................................3
1.6 Class D amplifier-Theory of Operation...................................................................4
1.7 Conclusion....................................................................................................................5
1.8 Scope and Outline.........................................................................................................5
Chapter 2: Modulation Methods for Class D amplifier
2.1 Hysteresis Modulation based PWM........................................................................8
2.2 Carrier based PWM.....................................................................................................8
2.3 Pulse Density Modulation...........................................................................................9
2.4 Pulse Width Modulation Implementation...................................................................12
2.4.1 Description of Circuit...............................................................................................12
2.4.1a Comparator Selection.............................................................................................14
2.4.1b Selection of frequency and amplitude of triangular sampling signal.............15
2.5 First order Delta Sigma Modulator Implementation...................................................15
2.6 Conclusion...................................................................................................................18
Chapter 3: Switching Stage
3.1 Switching Devices for Class D: BJT or MOSFET or IGBT? ....................................20
3.2 MOSFET Structure and Operation..........................................................................21
3.3 Major causes of non-linearity at switching stage....................................................22
3.3.1 Effect of Dead time on non-linearity................................................................22
3.3.1a Dead Time Vs THD........................................................................................23
3.3.2 Effect on Rds (ON) on distortion.....................................................................24
3.3.3 Timing errors in switching stage..............................................................................26

3.3.4 Power Supply Pumping ...........................................................................................27

3.4 Characteristics of Class D amplifiers...........................................................................29
3.4.1 Switching and Conduction Losses............................................................................29
3.5 Necessity for a Gate Driver..........................................................................................31
3.5.1 Gate drive losses....................................................................................................31
3.6 MOSFET Selection: Class D application.............................................................31
3.6.1 Drain-Source Breakdown voltage.............................................................................32
3.6.2 Gate Charge (Qg)......................................................................................................32
3.6.3 Static Drain-to-Source On-Resistance (Rds (ON))...............................................33
3.6.4 Body diode reverse recovery characteristics..............................................................34
3.7 Conclusion.....................................................................................................................34
Chapter 4: Output Filter Design
4.0 Why do we need a filter for Class D amplifiers? .........................................................35
4.1 Filters topologies: Class D amplifier.........................................................................35
4.1.1 Full Filter............................................................................................................35
4.1.2 Half Filter...................................................................................................................38
4.1.3 No Filter.....................................................................................................................39
4.2 Filter Loss Calculations.............................................................................................40
4.3 Electro Magnetic Interference in Class D amplifiers.............................................41
4.3.1 Sources of EMI in class D amplifiers.........................................................................41
4.3.1a Differential mode Noise............................................................................................41
4.3.1b Use of Ground Plane.................................................................................................43
4.3.2 Common Mode Noise.................................................................................................43
4.3.2a Common mode noise suppression.............................................................................44
4.3.3 Reducing EMI using Shielding...................................................................................45
4.4 Conclusion......................................................................................................................45
Chapter 5: Implementation and simulation results
5.1 Design Specifications.46
5.2 Required Components46
5.3 Design Implementation.......46

5.3.1 Input Switching Stage..47

5.3.2 The Power Amplification Stage...47
5.3.3 Filter Components Calculations...49
5.4 Final Design on ORCAD 16.0........50
5.5results....51
5.6 Conclusion...53
References............................................................................................................................54

LIST OF FIGURES
Fig 1.1 Class A amplifier........................................2
Fig 1.2 Class B amplifier.3
Fig 1.3 Class AB amplifier..3
Fig 1.4 Class D amplifier............................................................................3
Fig 2.1 Pulse Width Modulation.........................................................................................4
Fig 2.2 Hysteresis Modulation based PWM........................................................................7
Fig 2.3 Carrier Based Modulation...9
Fig 2.3.a Input, Carrier and PWM wave forms....9
Fig 2.4 Pulse Density Modulation..10
Fig 2.5 System level diagram of Class D amplifier with delta sigma modulation.10
Fig 2.6 Fist order sigma delta modulator....11
Fig 2.7 Approximate linear analysis of delta sigma amplifier12
Fig 2.8 Pulse Width Modulator...13
Fig 2.9 Pulse width modulator wave forms.14

Fig 2.10 First Order Delta Sigma Modulator.........................................................................16

Fig 2.11 Pulse density modulation waveforms...18
Fig 3.1 Half Bridge .................................................................................................................19
Fig 3.2 Full Bridge..20
Fig 3.3 MOSFET structure..21
Fig 3.4 Dead Time....................................................................................................................22
Fig 3.5a Distortion for dead time =56ns..23
Fig 3.5b Distortion for dead time =40ns..24
Fig 3.6 Effect of drain-to-source ON resistance......24
Fig 3.7 amplitude distortion caused by rds(on)...25
Fig 3.8a Effect of threshold voltage on switching delay.26
Fig 3.8b Effect of gate source voltage on switching delay......27
Fig 3.9a Half Bridge.....27
Fig 3.9b Full Bridge.....28
Fig 3.9c supply voltage pumping effect...28
Fig 3.10 Output of a comparator at very high carrier frequencies....30
Fig 3.11 Gate Driver....31
Fig 3.12 Effect of Rds(on) on efficiency.33
Fig 4.1 Full Second Order Butterworth filter...36
Fig4.2 BTL Half Circuit Model36
Fig 4.3 Combination of Two Half-Circuit Models...........................37
Fig 4.4 Half Filter..38
Fig 4.5 Differential Mode Noise41
Fig 4.6 Load Bypassing.42

Fig 4.7 Ground plane.43

Fig 4.8 Common Mode Noise...43
Fig 4.9a Common Mode noise suppression with ferrites..44
Fig 4.9b Common Mode suppression with capacitor44
Fig 4.10 Shielded Twisted Pair Connection..45
Fig 5.1 Simulated CLASS D Amplifier Design50
Fig 5.2 Comparator Output Wave Form....51
Fig 5.3 Final Output of the Class D Amplifier..51
Fig 5.4 FFT of Output Wave Form52

LIST OF TABLES
Table 5.1: MOSFET comparison table......49