ATJ209X Product

Program Guide
Version 1.4

Copyright 2005 Actions Semiconductor Co., Ltd. All rights reserved.

ATJ209X PROGRAM GUIDE

Declaration
All contents of this document are protected by copyright law and reproduction in whole or in part is
prohibited without the prior written consent of Actions Semiconductor Co., Ltd. Other product
names used in this publication are for identification purposes only and may be trademarks or
registered trademarks of their respective companies.
The information presented in this document does not form part of any quotation or contract, is
believed to be accurate and reliable. Actions Semiconductor Co., Ltd. reserves the right to make
changes to specifications and product descriptions at any time without notice, and to discontinue or
make changes to its products at any time without notice. Actions Semiconductor Co., Ltd.
specifically disclaims any and all liability for any consequence of the application or use of any
product or circuit. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
Actions Semiconductor Co., Ltd. is one of Licensee of Thomson Licensing S.A. and is approved to
distribute these semiconductor devices using MPEG Layer-3 (mp3) coding technology (mp3
decoder chips) by Thomson Licensing S.A. Supply of this product does not convey a license nor
imply any right to distribute content created with this product in revenue-generating broadcast
systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via
Internet, intranets and/or other networks), other content distribution systems (pay-audio or
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such use is required. For details, please visit http://mp3licensing.com.
Actions Semiconductor Co., Ltd. is one of Licensee of Microsoft Licensing, GP. Actions
Semiconductor Co., Ltd. is approved to distribute these semiconductor devices using Windows
Media Audio (wma) coding technology (wma codec chips) by Microsoft Licensing, GP. This
product includes technology owned by Microsoft Corporation and cannot be used or distributed
without a license from Microsoft Licensing, GP.

Additional Support
Additional product and company information can be obtained by visiting the Actions website at:
http://www.actions-semi.com

Copyright 2005 Actions Semiconductor Co., Ltd. All rights reserved.

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Table of Contents
1. Short Description ...................................................................................................................................................1
2. Block Diagram .......................................................................................................................................................2
3. Functions Block......................................................................................................................................................3
3.1 Clock /Bus Controller/DMA/IRQ/CTC .........................................................................................................3
3.1.1 Clock Control..............................................................................................................................................3
3.1.2 Bus Controller.............................................................................................................................................3
3.1.3 DMA Controller..........................................................................................................................................3
3.1.4 CTC Controller ...........................................................................................................................................3
3.1.5 IRQ Controller ............................................................................................................................................3
3.2 USB2.0 SIE .......................................................................................................................................................3
3.2.1 USB Control Registers.............................................................................................................................3
3.2.2 Endpoint Registers...................................................................................................................................3
3.3 Nand Flash/SMC State Machine ....................................................................................................................4
3.4 MMC/SD Flash Card Controller....................................................................................................................4
3.5 ATA Interface ...................................................................................................................................................4
3.6 I2C Interface ....................................................................................................................................................4
3.7 SPI Interface.....................................................................................................................................................4
3.8 SDRAM Interface ............................................................................................................................................4
3.9 UART and IR Interface...................................................................................................................................5
3.10 Key Scan Interface.........................................................................................................................................5
3.11 SPDIF Interface..............................................................................................................................................5
3.12 ICON LCD 4*20.............................................................................................................................................5
3.13 GPIO and Multifunction Configuration ......................................................................................................5
3.14 LOSC/RTC,HOSC/PLL,PMU/DC-DC ........................................................................................................6
3.14.1 LOSC/RTC................................................................................................................................................6
3.14.2 HOSC/PLL................................................................................................................................................6
3.14.3 PMU/DC-DC ............................................................................................................................................6
3.15 ADC, DAC and Headphone Driver ..............................................................................................................6
3.16 CMOS Sensor Interface & GPIOK..............................................................................................................6

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4

Register Definition .............................................................................................................................................7

4.00 Register00-- MCU Clock Control Register (BackToFunctionsBlock)....................................................7
4.01 Register01--EM Low Page Register (BackToFunctionsBlock) ...............................................................8
4.02 Register02--EM High Page Register (BackToFunctionsBlock) ..............................................................8
4.03 Register03--EM Page Inc/Dec Register (Back).........................................................................................9
4.04 Register04-- MCU-A15 Control Register (BackToFunctionsBlock).......................................................9
4.05 Register05-- Internal SRAM Page Register (BackToFunctionsBlock).................................................10
4.06 Register06-- DMA1 Source Address 0 Register(Back) ..........................................................................14
4.07 Register07--DMA1 Source Address 1 Register (Back) ..........................................................................14
4.08 Register08--DMA1 Source Address 2 Register (Back) ..........................................................................14
4.09 Register09--DMA1 Source Address 3 Register (Back) ..........................................................................14
4.0A Register0A--DMA1 IPM/IDM/ZRAM2 SRC Address Register(Back) ...............................................14
4.0B Register0B--DMA1 Destination Address 0 Register (Back) .................................................................15
4.0C Register0C--DMA1 Destination Address 1 Register (Back).................................................................15
4.0D Register0D--DMA1 Destination Address 2 Register (Back).................................................................15
4.0E Register0E--DMA1 Destination Address 3 Register(Back) ..................................................................15
4.0F Register0F--DMA1 IPM/IDM/ZRAM2 DST Address Register (Back) ...............................................15
4.10 Register10--DMA1 Byte Counter low Register(Back)...........................................................................16
4.11 Register11--DMA1 Byte Counter High Register(Back).........................................................................16
4.12 Register12--DMA1 Mode Register (Back) ..............................................................................................16
4.13 Register13--DMA1 Command Register(Back).......................................................................................17
4.14 Register14--DMA2 Source Address 0 Register (Back) ..........................................................................18
4.15 Register15--DMA2 Source Address 1 Register (Back) ..........................................................................18
4.16 Register16--DMA2 Source Address 2 Register (Back) ..........................................................................18
4.17 Register17--DMA2 Source Address 3 Register (Back) ..........................................................................18
4.18 Register18--DMA2 IPM/IDM/ZRAM2 SRC Address Register (Back)................................................18
4.19 Register19--DMA2 Destination Address 0 Register(Back)....................................................................19
4.1A Register1A--DMA2 Destination Address 1 Register(Back) ..................................................................19
4.1B Register1B--DMA2 Destination Address 2 Register(Back) ..................................................................19

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4.1C Register1C--DMA2 Destination Address 3 Register(Back)..................................................................19
4.1D Register1D--DMA2 IPM/IDM/ZRAM2 DST Address Register(Back) ...............................................19
4.1E Register1E--DMA2 Byte Count low Register(Back) .............................................................................20
4.1F Register1F--DMA2 Byte Count High Register(Back) ...........................................................................20
4.20 Register20--DMA2 Mode Register(Back)...............................................................................................20
4.21 Register21--DMA2 Command Register(Back).......................................................................................21
4.22 Register22--CTC Prescale Register(Back)..............................................................................................22
4.23 Register23--CTC T Period Low Register(Back) ....................................................................................22
4.24 Register24--CTC T Period High Register(Back)....................................................................................22
4.25 Register25--DMA/CTC IRQ Status Register(Back) ..............................................................................22
4.26 Register26--Master Interrupt Status Register(Back).............................................................................23
4.27 Register27--Master Interrupt Enable Register(Back) ...........................................................................23
4.28 Register28--Flash Controller Nand Enable Register(Back)..................................................................24
4.29 Register29--Flash Controller Address/DMA5 Select Register(Back)...................................................24
4.2A Register2A--Flash COMMAND register(Back) ....................................................................................25
4.2B Register2B --Flash Controller ECC control Register(Back) ................................................................25
4.2C Register2C --User ECC Register0(Back) ...............................................................................................26
4.2D Register2D --User ECC Register1(Back) ...............................................................................................26
4.2E Register2E--DSP Control/Status Register(Back)...................................................................................27
4.2F Register2F--DSP Boot Mode Register(Back) .........................................................................................27
4.30 Register30--DSP HIP Register 0(DATA) (Back).....................................................................................27
4.31 Register31--DSP HIP Register 1(DATA) (Back).....................................................................................27
4.32 Register32--DSP HIP Register 2(DATA) (Back).....................................................................................28
4.33 Register33--DSP HIP Register 3(DATA) (Back).....................................................................................28
4.34 Register34--DSP HIP Register 4(DATA) (Back).....................................................................................28
4.35 Register35--DSP HIP Register 5(DATA) (Back).....................................................................................28
4.36 Register36--DSP HIP Register 6(STATUS) (Back).................................................................................28
4.37 Register37--DSP HIP Register 7(STATUS) (Back).................................................................................28
4.38 Register38--SPDIF Control Register(Back)............................................................................................28

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4.39 Register39--SPDIF Status Register(Back) ..............................................................................................31
4.3A Register3A--SPDIF FIFO DATA Register(Back) ..................................................................................32
4.3B Register3B--SPDIF Channel Status Register (Back).............................................................................32
4.3C Register3C --USB5V VCC Regulator Register (Back) .........................................................................33
4.3E Register3E --USB Internal Resistor Control Register (Back) ..............................................................33
4.3F Register3F --VDD & VCC voltage detect Control Register(Back).......................................................34
4.40 Register40--High frequency crystal control Register(Back) .................................................................35
4.41 Register41--PLL Performance tune Register (Back) .............................................................................35
4.42 Register42-- PLL Control Register (Back) .............................................................................................36
4.43 Register43--RTC Control Register (Back)..............................................................................................38
4.44 Register44--RTC IRQ Status Register (Back) ........................................................................................39
4.45 Register45--RTC Time Low Register (Back)..........................................................................................39
4.46 Register46--RTC Time Middle Register (Back) .....................................................................................39
4.47 Register47--RTC Time High Register (Back).........................................................................................39
4.48 Register48--RTC Alarm Low Register (Back)........................................................................................40
4.49 Register49--RTC Alarm Middle Register (Back)...................................................................................40
4.4A Register4A--RTC Alarm High Register (Back) .....................................................................................40
4.4B Register4B--Losc Divider Low Byte Register (Back) ............................................................................40
4.4C Register4C--Losc Divider Middle Byte Register (Back).......................................................................40
4.4D Register4D--Losc Divider High Byte Register (Back)...........................................................................40
4.4E Register4E--Watch Dog Register (Back) ................................................................................................40
4.4F Register4F --DC to DC Control Register (Back)....................................................................................41
4.50 Register50 --USB FIFO Control Register (Back)...................................................................................42
4.51 Register51USB DMA6 Control Register (Back) ................................................................................42
4.52 Register52USB Interrupt Status0 Register (Back).............................................................................43
4.53 Register53USB Interrupt Status1 Register (Back).............................................................................43
4.54 Register54USB Interrupt Enable0 Register(Back) ............................................................................44
4.55 Register55USB Interrupt Enable1 Register(Back) ............................................................................44
4.56 Register56--USB Control Register(Back) ...............................................................................................44

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4.57 Register57--USB Status Register(Back) ..................................................................................................45
4.58 Register58--Endpoint Index Register(Back) ..........................................................................................45
4.59 Register59--Endpoint Configuration Register(Back) ............................................................................46
4.5A Register5A--Endpoint Control Register(Back) .....................................................................................46
4.5B Register5B--Endpoint Status Register(Back) ........................................................................................47
4.5C Register5C --Endpoint Interrupt Request Register(Back)...................................................................48
4.5D Register5D --Endpoint Interrupt Enable Register (Back) ...................................................................48
4.5E Register5E --Endpoint MaxPacketSize0 Register(Back)......................................................................48
4.5F Register5F --Endpoint MaxPacketSize1 Register (Back)......................................................................49
4.60 Register60 --Endpoint Data Register (Back) ..........................................................................................49
4.61 Register61 --Endpoint Byte Count0 Register (Back) .............................................................................49
4.62 Register62 --Endpoint Byte Count1 Register (Back) .............................................................................49
4.63 Register63 --Endpoint Transfer Count0 Register (Back) ......................................................................49
4.64 Register64 --Endpoint Transfer Count1 Register (Back) ......................................................................50
4.65 Register65 --Endpoint Transfer Count2 Register (Back) ......................................................................50
4.66 Register66--USB Register Page Index (Back).........................................................................................50
4.67 Register67--Device Address Register (Back) ..........................................................................................51
4.68 Register68--USB Test Modes Register (Back) ........................................................................................51
4.69 Register69--Frame Number0 Register (Back)........................................................................................51
4.6A Register6A--Frame Number1 Register (Back) ......................................................................................51
4.70 Register70 --MCU & DMA Clock Control Register (Back) ..................................................................51
4.71 Register71 --I2C Address Register (Back) ..............................................................................................52

4.72 Register72 --UART2 Sharp IR and SIR Baud Rate Register (Back) ................................................53
4.73 Register73--UART2 control Register(Back)...........................................................................................54
4.74 Register74--UART2/IR FIFO DATA Register(Back) ............................................................................55
4.75 Register75--IR Control Register(Back) ..................................................................................................55
4.77 Register77 --LRADC2 DATA Register(Back) ........................................................................................56
4.78 Register78--UART2 Mode & FIFO Status Register(Back) ...................................................................56
4.79 Register79--UART2 DRQ/IRQ Enable/Status Register(Back) .............................................................57

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4.7A Register7A-- I2C Control Register(Back) ..............................................................................................57
4.7B Register7B--I2C Status Register (Back) .................................................................................................59
4.7C Register7C --I2C Data Register(Back)...................................................................................................60
4.7D Register7D --SPI Control Register(Back) ..............................................................................................60
4.7E Register7E --SPI Clock Divide Control Register(Back) .......................................................................61
4.7F Register7F --SPI Data Register(Back) ....................................................................................................61
4.80 Register80 --DAC Control Register(Back) .............................................................................................61
4.81 Register81 --DAC Sample Rate Control Register(Back).......................................................................62
4.82 Register82 --Internal DAC PCM Out Lo Register(Back) .....................................................................63
4.83 Register83 --Internal DAC PCM Out Middle Register(Back)..............................................................63
4.84 Register84 --Internal DAC PCM Out High Register(Back) .................................................................63
4.85 Register85 --FIFO Status Register(Back) ...............................................................................................64
4.86 Register86 --Internal DAC Dither Control Register(Back) ..................................................................64
4.87 Register87--Internal DAC Analog Output Volume Control Register (Back) ......................................65
4.88 Register88--Internal DAC Analog Block Control Register (Back).......................................................65
4.89 Register89 USB DMA6 Address0 Register (Back) ...............................................................................65
4.8A Register8A USB DMA6 Address1 Register (Back)..............................................................................66
4.8B Register8B USB DMA6 Clock Register (Back) ...................................................................................66
4.8C Register8C --USB Global Control Register (Back) ...............................................................................66
4.8D Register8D--DMA4 Control and Status Register (Back) ......................................................................68
4.8E Register8E--GPIOK[7..0] Input and Output Enable (Back)................................................................68
4.8F Register8F--GPIOK[7..0] Data Register (Back) ....................................................................................69
4.90 Register90--ITU-R601 XY Data Register (Back) ...................................................................................69
4.91 Register91--DMA4 Destination Address high (Back) ............................................................................69
4.92 Register92--Cmos Sensor Control Register (Back)................................................................................69
4.93 Register93--Hsync Start Position Low(in pclk) (Back)..........................................................................70
4.94 Register94--Hsync Start & End Position High(in pclk) (Back) ............................................................70
4.95 Register95--Hsync End Position Low(in pclk) (Back) ...........................................................................70
4.96 Register96--Vsync Start Position Low(in Hsync) (Back).......................................................................70

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4.97 Register97--Vsync Start & End Position High(in Hsync) (Back) .........................................................70
4.98 Register98--Vsync End Position Low(in Hsync) (Back) ........................................................................71
4.99 Register99--DMA4 Destination Address Low (Back) ............................................................................71
4.9A Register9A--AUDIO ADC data register (Back).....................................................................................72
4.9B Register9B--Audio ADC Control Register 0 (Back)..............................................................................72
4.9C Register9C --BATTERY ADC DATA Register (Back) ..........................................................................72
4.9D Register9D --External input I2S DATA Register(Back) .......................................................................74
4.9F Register9F--Audio ADC modulator performance tuning register (Back) ...........................................74
4.A0 RegisterA0-A7 ATA Decode Registers (Back)........................................................................................75
4.A8 RegisterA8--DMA66 Destination/Source Address0(Back) ...................................................................76
4.A9 RegisterA9--DMA66 Destination/Source Address1(Back) ...................................................................76
4.AA RegisterAA--DMA66 Destination/Source Memory Select(Back)........................................................76
4.AB RegisterAB--DMA66 Byte Counter Low Register(Back) ....................................................................77
4.AC RegisterAC--DMA66 Byte Counter High Register(Back)...................................................................77
4.AD RegisterAD-- Serial LCM Control Register(Back) ..............................................................................79
4.AE RegisterAE--DMA3 Byte Counter Hi Register(Back) ......................................................................79
4.B0 RegisterB0 --SDRAM TYPE REGISTER (Back) .................................................................................79
4.B1 RegisterB1 --SDRAM COMMAND

REGISTER (Back)................................................................79

4.B2 RegisterB2--SDRAM ADDRESS 2 (Back)..........................................................................................80

4.B3 RegisterB3--SDRAM ADDRESS 1 (Back)..........................................................................................80
4.B4 RegisterB4--SDRAM ADDRESS 0 (Back)..........................................................................................80
4.B5 RegisterB5--SDRAM Control Register (Back) ...................................................................................80
4.B6 RegisterB6--DMA3 SRAM ADDRESS LOW (Back) ........................................................................81
4.B7 RegisterB7--DMA3 SRAM ADDRESS HI (Back)..............................................................................81
4.B8 RegisterB8--DMA3 COUNTER LOW BYTE (Back) ........................................................................81
4.B9 RegisterB9--DMA3 MODE(Back) ..........................................................................................................81
4.BA RegisterBA--DMA3 Command Register(Back)....................................................................................82
4.BC RegisterBC-- DMA66 Control /Status Register (Back)........................................................................87
4.BD RegisterBD--ATA Config Register (Back) .............................................................................................88

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4.BE RegisterBE--Battery charger Control Register (Back) ........................................................................88
4.BF RegisterBF --Battery charger Status Register (Back)...........................................................................89
4.C0 RegisterC0--Key Scan Data Register (Back) .........................................................................................89
4.C1 RegisterC1--Key Scan Control Register (Back) ....................................................................................90
4.C2 RegisterC2--LCD Data0 Register(Back)................................................................................................91
4.C3 RegisterC3--LCD Data1 Register(Back)................................................................................................92
4.C4 RegisterC4--LCD Data2 Register(Back)................................................................................................92
4.C5 RegisterC5--LCD Data3 Register(Back)................................................................................................92
4.C6 RegisterC6--LCD Data4 Register(Back)................................................................................................92
4.C7 RegisterC7--LCD Data5 Register(Back)................................................................................................92
4.C8 RegisterC8--LCD Data6 Register(Back)................................................................................................92
4.C9 RegisterC9--LCD Data7 Register(Back)................................................................................................93
4.CA RegisterCA--LCD Data8 Register(Back) ..............................................................................................93
4.CB RegisterCB--LCD Data9 Register(Back) ..............................................................................................93
4.CC RegisterCC --Flash ECC Register0(Back)............................................................................................93
4.CD RegisterCD --Flash ECC Register1(Back)............................................................................................93
4.CE RegisterCE --Flash ECC Register2(Back) ............................................................................................94
4.CF RegisterCF --Flash ECC Register3(Back) .............................................................................................94
4.D0 RegisterD0 --BAT ADC and LRADC1/LRADC2 Control and Status Register (Back) .....................95
4.D1 RegisterD1--BATTERY ADC Control and Touch Panel Sense Period Select Register (Back) .........95
4.D2 RegisterD2--Touch Panel Enable and Scan Period Select Register (Back).........................................96
4.D3 RegisterD3--Audio ADC performance tuning register(Back)..............................................................96
4.D4 RegisterD4--Audio ADC First Control Register (Back) .......................................................................97
4.D5 RegisterD5--Audio ADC Second Control Register(Back) ....................................................................97
4.D6 RegisterD6--Analog Input Gain Control Register(Back) .....................................................................98
4.D7 RegisterD7--Audio ADC FIFO control register(Back) .........................................................................99
4.D8 RegisterD8--LRADC1 data Register (Back)..........................................................................................99
4.D9 RegisterD9--Touch Panel X Position Data Low Byte Register(Back) ...............................................100
4.DA RegisterDA--Touch Panel X Position Data High Byte Register(Back) .............................................100

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4.DB RegisterDB--Touch Panel Y Position Data Low Byte Register(Back) ..............................................100
4.DC RegisterDC--Touch Panel Y Position Data High Byte Register (Back) ............................................100
4.DE RegisterDE--Touch Panel ADC IRQ Control and Status Register (Back) .......................................100
4.DF RegisterDF --Power Control Register (Back)......................................................................................101
4.E0 RegisterE0 --SD control register1 (Back).............................................................................................102
4.E1 RegisterE1--SD control register2 (Back)..............................................................................................102
4.E2 RegisterE2--CMD/RSP register (Back) ................................................................................................103
4.E3 RegisterE3--CRC7 calculation result register (Back) .........................................................................103
4.E4 RegisterE4--Data in/out register (R/W) (E4h) (Back)......................................................................103
4.E5 RegisterE5--CRC16 calculation result register high (Back)...............................................................103
4.E6 RegisterE6--CRC16 calculation result register low (Back) ................................................................103
4.E7 RegisterE7--SD Status Register (Back) ................................................................................................104
4.E8 RegisterE8-- RS E(x) FIFO Register (Back) ........................................................................................104
4.E9 RegisterE9-- RS ECC Register(Parity Symbols FIFO) (Back) ..........................................................105
4.EA RegisterEA--ECC4 TEST(ECC4 TEST Register, 0EAh) (Back) ......................................................105
4.EB RegisterEB --R-S ECC Status/Control Register(Back) ......................................................................107
4.EC RegisterECUSB VBUS Control Register (Back) ............................................................................ 113
4.EE RegisterEE--MFP Select/GPO_A[2:0] Data Output Register (Back) ............................................... 113
4.EF RegisterEF--GPIO_B[7:0] and KEYI/O[3:0] Config Register(Back) ............................................... 116
4.F0 RegisterF0--GPIO_B[7:0] Output Enable Register (Back) ................................................................ 116
4.F1 RegisterF1--GPIO_B[7:0] Input Enable Register (Back) ................................................................... 117
4.F2 RegisterF2--GPIO_B[7:0] Data Output/Input Register (Back) ......................................................... 117
4.F3 RegisterF3--GPIO_C[3:0] Output/Input Enable Register (Back) ..................................................... 117
4.F4 RegisterF4--GPIO_C[3:0] Data Output/Input Register (Back) ......................................................... 118
4.F5 RegisterF5--GPIO_D[5:0] Output Enable Register (Back) ................................................................ 118
4.F6 RegisterF6--GPIO_D[5:0] Input Enable Register (Back)................................................................... 118
4.F7 RegisterF7--GPIO_D[5:0] Data Output/Input Register(Back) .......................................................... 119
4.F8 RegisterF8--GPIO_E[7:0] Output Enable Register(Back) ................................................................. 119
4.F9 RegisterF9--GPIO_E[7:0] Input Enable Register (Back) ................................................................... 119

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4.FA RegisterFA--GPIO_E[7:0] Data Output/Input Register (Back) ........................................................ 119
4.FB RegisterFB--GPIO_F[7:0] Output Enable Register (Back) ...............................................................120
4.FC RegisterFC--GPIO_F[7:0] Input Enable Register (Back)..................................................................120
4.FD RegisterFD--GPIO_F[7:0] Data Output/Input Register (Back)........................................................120
4.FE RegisterFE--GPIO_G[3:0] Output/Input Enable Register (Back)....................................................120
4.FF RegisterFF--GPIO_G[3:0] Data Output/Input Register(Back) .........................................................121
5. Abbreviation .......................................................................................................................................................122

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Revision History
Version

Date

Description

Ver1.0

Feb, 2005

Ver1.1

May, 2005 2nd version, file format modified

Ver1.2

Jun, 2005

Battery adc typic value in different mode added

Ver1.3

July, 2005

Some content modified

Ver1.4

Oct2006 Some content modified

1st version created

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ATJ209X PROGRAM GUIDE

1. Short Description
ATJ209X is a third generation single-chip highly-integrated digital music system solution for devices
such as dedicated audio players, PDAs, and cell phones. It includes an audio decoder with a high
performance DSP with embedded RAM and ROM, ADPCM record capabilities and USB interface for
downloading music and uploading voice recordings. ATJ209X also provides an interface to SPDIF, flash
memory, LED/LCD, button and switch inputs, headphones, microphone and FM radio input and control.
ATJ2095/2097/2099 contains a high performance DSP, which can easily be programmed to support many
kinds of digital audio standards such as MP3,WMA,ect. For devices like USB-Disk, ATJ209X can act as a
USB mass storage slave device to personal computer system. ATJ209X has low power consumption to
allow long battery life and an efficient flexible on-chip DC-DC converter that allows many different battery
configurations, including 1xAA, 1xAAA, 2xAA,2xAAA and Lilon. The built-in Sigma-Delta DAC include a
headphone driver to directly drive low impedance headphones. The ADC include inputs for both
Microphone and Analog Audio in to support voice recording and FM radio integration features. ATJ209X
provides a true ALL-IN-ONE solution that is ideally suited for highly optimized digital audio players.

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Copyright 2005 Actions Semiconductor Co., Ltd. All rights reserved.

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2. Block Diagram
ATJ209X PROGRAM GUIDE

ATJ209X PROGRAM GUIDE

3. Functions Block
3.1 Clock /Bus Controller/DMA/IRQ/CTC
3.1.1 Clock Control
Clock control includes Register00 , Register70

3.1.2 Bus Controller

Bus Controller includes RegisterA0, Register01, Register02, Register03, Register04, Register05
six registers.

3.1.3 DMA Controller

DMA1 and DMA2 controller includes 16 registers from Register05 to Register21.

3.1.4 CTC Controller

CTC controller includes Register22, Register23, Register24 3 registers.

3.1.5 IRQ Controller

IRQ Controller includes Register25, Register26, Register27 3 registers.

3.2 USB2.0 SIE

3.2.1

USB Control Registers

USB control registers include Register3E, RegisterEC, Register89~Register8C, Register50~

Register57, Register66~ Register69 , totally 18 registers.

3.2.2

Endpoint Registers
Endpoint Registers include Register58~Register65 , totally 14 registers.

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3.3 Nand Flash/SMC State Machine

Nand flash/Smc state machine registers include Register28 ~ Register2D, RegisterCC ~ RegisterCF,
RegisterEB, RegisterE8, RegisterE9, RegisterEA.

3.4 MMC/SD Flash Card Controller

MMC/SD flash card controller registers include SD status register RegisterE7, SD control
register1 RegisterE0, SD control register2 RegisterE1, CMD/RSP register RegisterE2, CRC7
calculation result register RegisterE3, Data in/out register RegisterE4, CRC16 calculation result
register RegisterE5 and RegisterE6.

3.5 ATA Interface

ATA interface includes registersATA cnfig register RegisterBD, DMA66 control /status register
RegisterBC, ATA decode registers RegisterA0~RegisterA7, DMA66m destination/source address
registers RegisterA8 and RegisterA9, DMA66 destination/source memory select register RegisterAA,
DMA66 byte counter register RegisterAB and RegisterAC.

3.6 I2C Interface

I2C Interface includes registers-- I2C control register Register7A, I2C status register Register7B,
I2C address register Register71, I2C data register Register7C.

3.7 SPI Interface

SPI Interface registers include SPI control register Register7D, SPI clock divide control
register Register7E, SPI data register Register7F.

3.8 SDRAM Interface

SDRAM Interface registers include SDRAM type register RegisterB0, SDRAM command
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register RegisterB1, SDRAM address registers RegisterB2, RegisterB3 and RegisterB4, SDRAM
control register RegisterB5, DMA3 SRAM address RegisterB6 and RegisterB7, DMA3 byte counter
low register RegisterB8, DMA3 byte counter high register RegisterAE, DMA3

command register

RegisterBA

3.9 UART and IR Interface

includes registers UART2

UART and IR interface

Sharp IR and SIR baud rate register,

Register72, UART2 control register Register73, UART2/IR FIFO data register Register74, UART2
Mode & FIFO status register Register78, UART2 DRQ/IRQ Enable/Status register register79, IR
Control Register register75.

3.10 Key Scan Interface

Key Scan Interface includes registers key scan data register RegisterC0, key scan control
register RegisterC1,

3.11 SPDIF Interface

SPDIF Interface includes registers SPDIF control register Register38, SPDIF status register
Register39, SPDIF FIFO data register Register3A, SPDIF channel status Register Register3B.

3.12 ICON LCD 4*20

ICON LCD 4*20 includes data registers RegisterC2~ RegisterC9.

3.13 GPIO and Multifunction Configuration

GPIO and multifunction configuration includes registers MFP Select/GPO_A[2:0] data output register
RegisterEE,

GPIO_B[7:0]

and

KEYI/O[3:0]

config

register

RegisterEF

and

other

GPIO

control/enable/data registers from RegisterF0 to RegisterFF.

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3.14 LOSC/RTC,HOSC/PLL,PMU/DC-DC
3.14.1 LOSC/RTC
This block includes register Register43 ~ register4E.

3.14.2 HOSC/PLL
This block include register Register40 ~ register42.

3.14.3 PMU/DC-DC
This block includes battery charger control register RegisterBE, battery charger status register
RegisterBF, USB5V VCC regulator register Register3C, VDD & VCC voltage detect control register
Register3F, DC To DC Control Register Register4F, ADC control and status register RegisterD0, battery
ADC data register Register9C, LRADC2 data register Register77, power control register RegisterDF

3.15 ADC, DAC and Headphone Driver

This block includes DAC control register Register80, External I2S input data register Register9D,
DAC

control register Register81 ~ Register88, AUDIO ADC data register

register9A, Battery

ADC/LRADC1 control & touch panel sense period select register RegisterD1, touch panel enable and
scan period select register RegisterD2 , audio ADC performance tuning register RegisterD3, audio ADC
modulator performance tuning register

Register9F, audio ADC first and second control register

RegisterD4 and RegisterD5, analog input gain control register RegisterD6, audio ADC FIFO control
registerD7, audio ADC fs control register Register9B, LRADC1 data register RegisterD8, touch panel
position data register RegisterD9 ~ RegisterDC, TPADC IRQ control and status register RegisterDE.

3.16 CMOS Sensor Interface & GPIOK

This block includes registers Register8D ~ Register99.

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Register Definition

4.00

Register00-- MCU Clock Control Register (BackToFunctionsBlock)

It may take a while before MCU Clock Changes. When the MCU clock is stopped (DC, or Standby
mode), there are several ways to recover the clock to non-divided LOSC clock source:
1. Push Reset button
2. POWER ON RESET
3. Key Board IRQ
4. Alarm IRQ
5. SIRQ
6. Touch Panel IRQ
7. USB wake up IRQ

Bits

Description

Access

Reset

7:6

Number of Wait states for external memory access

0 0:
0, zero wait state (default)
0 1:
1, one wait state
1 0:
2, two wait states
1 1:
3, three wait states

R/W

00

5:4

MCU clock source select

0 0:
LOSC (Low frequency oscillator)
0 1:
HOSC (High frequency oscillator)
1 0:
MCU PLL (Phase Locked Loop)
1 1:
reserved

R/W

00

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2:0

4.01

External Bus Width.0:8-bit, 1: 16-bit.

If this bit is 1, the bus width is 16 bits when it operates external
hardware. It is used by MCU or DMA. When MCU/DMA writes or reads, it
just needs writing to IOA0h or reading from IOA0h. When reading, read
low byte first, then high byte. When writing, write low byte first, then high
byte. These operations only send MRD-, MWR-, D[15..0], the external
hardware chip enable signals need to be enabled by software.
For example:
16Bit NAND Flash can use old-mode.
16Bit Color LCD can use GPIO port as chip enable signal.

RW

MCU clock division control

000
/1(default)
001
/2
010
/4
011
/8
100
/16
101
/32
110
/64
111
DC

R/W

000

Access

Reset

R/W

Register01--EM Low Page Register (BackToFunctionsBlock)

Bits
7:0

Description
Extended page address bits, for EMA22-15

NOTE: EM-External Memory

4.02

Register02--EM High Page Register (BackToFunctionsBlock)

Bits

Description

Access

Reset

Software reset. Write 1 to this bit will reset system, after resetting it will be
cleared.

R/W

R/W

its operation is equal to external reset- pin.

Software reset flag.
6

0: software reset not occured,1:software reset occurred.

Writing 1 to this bit will clear it.

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Extended page address bits, for EMA28-23
EMA28, 27,26=000B, decode to CE0001B, decode to CE1010B, decode to CE2011B, decode to CE31XXB, reserved

5:0

R/W

000000

NOTE: CE0- is just for MROM/NorFlash/Sram, CE1/2/3- can be used for Nand Flash or others except
MROM.

4.03

Register03--EM Page Inc/Dec Register (Back)

Bits
7:0

4.04

Description
2s complement to add to page address
NewReg02h*256+NewReg01h=OldReg02h*256+OldReg01h+Reg03h

Access

Reset

Access

Reset

Register04-- MCU-A15 Control Register (BackToFunctionsBlock)

Bits

Description

Watch Dog Flag,

1 means WD reset or irq ever occurred, writing 1 to this bit will clear it.

R/W

External Reset flag,

1 means external reset had been asserted, writing 1 to this bit will clear
the bit.

R/W

Low Bat NMI- pending.

The LBNMI- voltage can be set by the regDF
If LBNMI- occurred , this bit will be set . Writing 1 to this bit will clear it. if
VbatMon<LBD (LBD is set by Reg), it issues SysReset-. After
VbatMon>LBD, circuit should release SysReset- and wake up MCU
again.

R/W

DMA clock source select

00
LOSC
01
HOSC
10
MCU PLL
11
DC=Low level

R/W

00

SIRQ- enable. 0:disable, 1: enable.

R/W

LBNMI- Enable. 0: disable , 1: enable.

R/W

4:3

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4.05

A15 control bit.

0 force MCUs A15 to be 1, execute program from CE0 memory
space 1 for normal operation. The boot code after power on reset must
jump 800xh followed by an IO write to 04h to set this bit for normal
operation.

R/W

Register05-- Internal SRAM Page Register (BackToFunctionsBlock)

MCU 64KB Memory Space
0000H

Internal
Memory
Space
(MCU.A15=0)

ZRAM1
16KB-64

16KB

IPMH IPMM
16KB 16KB

IPML
16KB

IDMH IDMM IDML ZRAM2 URAM

16KB 16KB 16KB (3+3)KB 2k+256

8000H
Entended
Memory
Space
(MCU.A15=1)

32KB

BANK0(32KB)

Brom

BANK1(32KB)
BANK2(32KB)

FFFFH

Trom
BANK3(32KB)

......

BANK..(32KB)

If IA15=0 -> mapped to internal Memory

If IA14=0, mapped to internal ZRAM 16K-64 ZRAM1

If IA14=1, mapped to internal DSP IPM/IDM when they are mapped into MCU memory space 3
extended address bits of a IO mapped register (Mapped at registered are used to decode the access to
one of these memory blocks

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Bit 2 1 0

Accessed Block
IPM low byte

001

IPM middle byte

010

IPM high byte

011

reserved

100

IDM low byte

101

IDM middle byte

110

IDM high byte

111

ZRAM2

B1+B2

000

Since IPM/IDM is mapped to MCU memory space per 8K block, IA13 is used to select low/high
block of 8K bytes in each 16K byte block.
If IA15=1 -> Extended address bits are IO mapped at 01h and 02h for EMA15-28. EMA15-25 are
output as address bus, while the EMA26-28 are used to decode CE0- ~ CE3-.
CE0- is used to access boot code from ROM/MASK/NOR- type Flash.
CE1- to CE3- can be configured to access ROM, or RAM or NAND-type Flash.

ATJ209Xs internal MCU MROM/SRAM memory mapping:

1)

(16K-64) byte ZRAM1(IA15=0,IA14=0): 0000H-3FBFH

2)

6Kbyte ZRAM2 (IA15=0, IA14=1, IOReg05.[2:0]=111): 4000H-57FFH

3)

(2K+256) byte URAM: 5800H-60FFH it has synchronization and asynchronism accessing

mode.

4)

12Kbyte BROM (IA15=1,Reg02=00h, Reg01=00h): 8000h-AFFFh

5)

21Kbyte g1 (IA15=1,Reg02=00h,Reg01=02h): 8000h-D3FFh

6)

17Kbyte TROM2 (IA15=1,Reg02=00h,Reg01=03h): 8000h-C400h

ATJ209Xs internal DSP IPM/IDM memory mapping:

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1) 16K x24bit IPM SRAM:

0000H-3FFFH

2) 16K x24bit IDM SRAM : 0000H-3FFFH

ATJ209Xs internal DSP IPM/IDM memory mapping accessed by MCU:

1)

16K x3 byte IPM SRAM:

4000H-7FFFH

2)

16K x3 byte IDM SRAM : 4000H-7FFFH

(Hi/Mid/Low Byte Select and Mapping Mode controlled by IOReg05)

DMA Mode Notes:

1: When DMA1 and DMA2 are active, MCU will halt, and DMA1 and DMA2 have priority.
2: DMA3, DMA4, FLASHDMA or USB DMA is active, MCU will not halt.
ZRAM1 and ZRAM2 Notes:
Input: A[13:0], ID[7:0], ZRAMRD-, ZRAMWROutput: RD[7:0] (Tri-state)
Speed: max read time 30 ns from ZRAMRD- going low
Power consumption: stand by when both WR- and RD- are inactive, access current
as low as possible.

ZRAM2 is compose of B1 and B2

each of them is 2k*8 byte SRAM.B1 ,B2 and ZRAM1(B0) can be

operated independently. It has the following modes:

1)

MCU running at B0, while DMA[M] read B1 and DMA[N] write B2.B1 and B2 are vise versa. M=1, 2,
3, 4, 5, 6, 66; N=1, 2, 3, 4, 5, 6, 66; M!=N.

2)

MCU running at B0+B1+B2 or B0+B1 or B0+B2.

IPM and IDM Notes:

Power consumption: stand by when both WR- and RD- are inactive, access current is as low as possible.
PM/DM can be visited by MCU, DSP, DMA1, DMA2, DMA3, DMA4, DMA5 and DMA66 .When DSP visits
low or high bytes of 8Kbytes, MCU/DMA1~5/DMA66 can visit high or low bytes of 8Kbytes at the same

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time.

ISRAMP (Internal SRAM Page Register, 05h)

Bits

Description

Access

Reset

0: low 8K block of IPM is mapped to DSP,

1: low 8K block of IPM is mapped to MCU/DMA[N]

R/W

0: hi 8K block of IPM is mapped to DSP,

1: hi 8K block of IPM is mapped to MCU/DMA[N]

R/W

0 low 8K block of IDM is mapped to DSP,

1 low 8K block of IDM is mapped to MCU/DMA[N]

R/W

0 hi 8K block of IDM is mapped to DSP,

1 hi 8K block of IDM is mapped to MCU/DMA[N]

R/W

Watchdog IRQ or Reset- Select.0:reset-,1:irq.

0 when watchdog timeout, it send Reset- signal.
1 when watchdog timeout, it send Irq signal.

R/W

Extended IPM/IDM page address bit.

0 0 0 IPM low byte
0 0 1 IPM middle byte
0 1 0 IPM high byte
0 1 1 reserved
1 0 0 IDM low byte
1 0 1 IDM middle byte
1 1 0 IDM high byte
1 1 1 B1+B2+URAM
B1: 4000H-4BFFH
B2: 4C00H-57FFH
URAM: 5800H-60FFH

R/W

000

2:0

In DMA[N], N=1, 2, 3, 4, 5, 6, 66.

The following list is register05 data in different condition.
WHEN DSP ACCESS
IPMH
IPMM
IPML
IDMH

WHEN MCU ACCESS

Low 8k

0XXXX010B

1XXXX010B

High 8k

X0XXX010B

X1XXX010B

Low 8k

0XXXX001B

1XXXX001B

High 8k

X0XXX001B

X1XXX001B

Low 8k

0XXXX000B

1XXXX000B

High 8k

X0XXX000B

X1XXX000B

Low 8k

XX0XX110B

XX1XX110B

High 8k

XXX0X110B

XXX1X110B

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IDMM
IDML

4.06

Low 8k

XX0XX101B

XX1XX101B

High 8k

XXX0X101B

XXX1X101B

Low 8k

XX0XX100B

XX1XX100B

High 8k

XXX0X100B

XXX1X100B

Register06-- DMA1 Source Address 0 Register(Back)

Bits
7:0

4.07

Description

4.08

6:0

4.09

R/W

Access

Reset

R/W

Register07--DMA1 Source Address 1 Register (Back)

Description
DMA1SA[15:8]

Register08--DMA1 Source Address 2 Register (Back)

Bits
7

Reset

DMA1SA[7:0]

Bits
7:0

Access

Description

Access Reset

DMA1 Source DSP Mode Select. 0:normal, 1:DSP mode.

R/W

DMA1SA[22:16]

R/W

xxxxxxx

Register09--DMA1 Source Address 3 Register (Back)

Bits

Description

Access

Reset

External Memory Select,

0 selects Int.Memory, 1 selects external memory

R/W

Int.Memory select,
0 selects ZRAM, 1 selects IPM/IDM/ZRAM2

R/W

Reserved.

R/W

xxxxx

Access

Reset

R/W

xxx

4:0

DMA1SA[28:24]

4.0A Register0A--DMA1 IPM/IDM/ZRAM2 SRC Address Register(Back)

Bits

Description

7:3

Reserved

2:0

DMA1ISA[2:0] these bits should be set the same as R05h_2:0 if

IPM/IDM/ZRAM2 is selected.

NOTE: SRCsource

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4.0B Register0B--DMA1 Destination Address 0 Register (Back)

Bits
7:0

Description

Access

Reset

R/W

Access

Reset

R/W

Access

Reset

R/W

Access

Reset

DMA1DA[7:0]

4.0C Register0C--DMA1 Destination Address 1 Register (Back)

Bits
7:0

Description
DMA1DA[15:8]

4.0D Register0D--DMA1 Destination Address 2 Register (Back)

Bits
7:0

4.0E

Description
DMA1DA[23:16]

Register0E--DMA1 Destination Address 3 Register(Back)

Bits

Description

External Memory Select,

0: Int.Memory, 1: external memory

R/W

Int.Memory select,
0: ZRAM, 1: IPM/IDM/ZRAM2

R/W

Reserved

R/W

xxxxx

Access

Reset

4:0

DMA1DA[28:24]

4.0F Register0F--DMA1 IPM/IDM/ZRAM2 DST Address Register (Back)

Bits
7:3

Description
Reserved

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2:0

DMA1IDA[2:0].
0 0 0 IPML
0 0 1 IPMM
0 1 0 IPMH
0 1 1 reserved
1 0 0 IDML
1 0 1 IDMM
1 1 0 IDMH
1 1 1 ZRAM2(B1+B2+URAM)

R/W

xxx

Access

Reset

R/W

Access

Reset

R/W

xxxxxxx

Access

Reset

DMA1 wait state select

00
0 wait state
01
1 wait state
10
2 wait states
11
3 wait states

R/W

00

DMA1 Destination DSP transfer mode

0: linear mode,
1: DSP mode, it is used when transmitting DSP code or data.

R/W

DMA1 DST down count,

0: up count (default), 1: down count

R/W

DMA1 SRC down count,

0: up count(default), 1: down count

R/W

NOTE: DST-- Destination

4.10

Register10--DMA1 Byte Counter Low Register (Back)

Bits
7:0

4.11

Description
DMA1IDA[7:0]

Register11--DMA1 Byte Counter High Register (Back)

Bits
7
6:0

4.12

Description
Reserved
DMA1BC[14:8]
Maximum byte transferred is 32Kbytes

Register12--DMA1 Mode Register (Back)

Bits

7:6

Description

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2

DMA1 for DSP BOOT, 0: normal, 1: DSP BOOT

R/W

DMA1 DST is IO. 0 : Memory 1: IO .When DMA DST is IO, usually the IO
is a FIFO or other array, the IO address will not increase or decrease.

R/W

DMA1 SRC is IO. 0 : Memory 1: IO .When DMA SRC is IO, usually the IO
is a FIFO or other array, the IO address will not increase or decrease.

R/W

Access

Reset

DMA1 TC IRQ enable.

0 disables IRQ. 1 enables IRQ when DMA1 finishes the whole block
transfer.
TC: Transmit complete.

R/W

DMA1 Half Transfer IRQ enable.

0 disables IRQ. 1 enables IRQ when DMA1 finishes half of the defined
block transfer.

R/W

DMA1 Continue Block Transfer enable.

0 disables the continuous block transfer mode and Bit 1 of this register will
be cleared when the last byte of the block is transferred.
1 enables the continuous block transfer mode and Bit 1 of this register will
not be cleared and SRC address counter/DST address counter/byte
length counter will be reloaded with their corresponding registers when
DMA1 finishes the block transfer.

R/W

DMA1 Priority, 0 DMA1 low priority,

1: DMA1 high priority When both DMA1 Priority and DMA2 Priority are set
or cleared simultaneously, the priority is in the style of the first start one
which is also the first end one.

R/W

External Trigger
00
DRQ1A, UART2 TX DRQ
01
DRQ1B, reserved
10
DRQ1C, reserved
11
DRQ1D, SPDIF TX DRQ

R/W

00

External DRQ trigger enable,

0: disable external DRQ trigger. 1: enable

R/W

DMA1 Start.
After TC, the bit will be cleared. The low-go-high edge of this bit will load
SRC start address, DST start address, byte count into the current working
counters.

R/W

4.13
Bits

3:2

Register13--DMA1 Command Register (Back)

Description

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4.14

Register14--DMA2 Source Address 0 Register (Back)

Bits
7:0

4.15

Description

Access

Reset

R/W

Access

Reset

R/W

Access

Reset

DMA2 Source DSP Mode Select. 0:linear, 1: DSP Mode.

R/W

DMA2SA[22:16]

R/W

xxxxxxx

Access

Reset

DMA2SA[7:0]

Register15--DMA2 Source Address 1 Register (Back)

Bits
7:0

4.16

Description
DMA2SA[15:8]

Register16--DMA2 Source Address 2 Register (Back)

Bits
7
6:0

4.17

Description

Register17--DMA2 Source Address 3 Register (Back)

Bits

Description

External Memory Select,

0: Int.Memory,1: external memory

RW

Int.Memory select, 0: ZRAM, 1: IPM/IDM/ZRAM2

RW

Reserved

R/W

xxxxx

Access

Reset

4:0

4.18

DMA2SA[28:24]

Register18--DMA2 IPM/IDM/ZRAM2 SRC Address Register (Back)

Bits
7:3

Description
Reserved

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2:0

4.19

DMA2ISA[2:0]
0 0 0 IPML
0 0 1 IPMM
0 1 0 IPMH
0 1 1 reserved
1 0 0 IDML
1 0 1 IDMM
1 1 0 IDMH
1 1 1 ZRAM2(B1+B2+URAM)

xxx

Access

Reset

R/W

Access

Reset

R/W

Access

Reset

R/W

Access

Reset

Register19--DMA2 Destination Address 0 Register(Back)

Bits
7:0

R/W

Description
DMA2DA[7:0]

4.1A Register1A--DMA2 Destination Address 1 Register(Back)

Bits
7:0

Description
DMA2DA[15:8]

4.1B Register1B--DMA2 Destination Address 2 Register(Back)

Bits
7:0

Description
DMA2DA[23:16]

4.1C Register1C--DMA2 Destination Address 3 Register(Back)

Bits

Description

External Memory Select,

0: Int.Memory, 1: external memory

R/W

Int.Memory select, 0: ZRAM, 1: IPM/IDM/ZRAM2

R/W

Reserved

R/W

xxxx

Access

Reset

4:0

DMA2DA[28:24]

4.1D Register1D--DMA2 IPM/IDM/ZRAM2 DST Address Register (Back)

Bits
7:3

Description
Reserved

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2:0

DMA2IDA[2:0]
0 0 0 IPML
0 0 1 IPMM
0 1 0 IPMH
0 1 1 reserved
1 0 0 IDML
1 0 1 IDMM
1 1 0 IDMH
1 1 1 ZRAM2

R/W

xxx

Access

Reset

R/W

Access

Reset

R/W

xxxxxxx

Access

Reset

DMA2 wait state select

00
0 wait state
01
1 wait state
10
2 wait states
11
3 wait states

RW

00

DMA2 Destination DSP transfer mode,

0: linear mode,
1: DSP mode, it is used when transmit DSP code or data.

R/W

DMA2 DST down count.

0: up count, 1: down count

R/W

DMA2 SRC down count.

0: up count, 1: down count

R/W

DMA2 for DSP for DSP BOOT, 0: normal, 1 : DSP BOOT

R/W

4.1E

Register1E--DMA2 Byte Count Low Register (Back)

Bits
7:0

4.1F

Description
DMA2BC[7:0]

Register1F--DMA2 Byte Count High Register (Back)

Bits
7
6:0

4.20

Description
Reserved
DMA2BC[14:8]

Register20--DMA2 Mode Register (Back)

Bits

7:6

Description

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1

DMA2 DST is IO. 0 : Memory 1: IO. When DMA DST is IO, usually the IO
is a FIFO or other array, the IO address will not increase or decrease.

R/W

DMA2 SRC is IO. 0 : Memory 1: IO. When DMA SRC is IO, usually the IO
is a FIFO or other array, the IO address will not increase or decrease.

R/W

Access

Reset

DMA2 TC IRQ enable.

0 disable IRQ. 1 enables IRQ when DMA2 finishes the whole block
transfer.

RW

DMA2 Half Transfer IRQ enable.

0 disable IRQ. 1 enables IRQ when DMA2 finishes half of defined block
transfer.

R/W

DMA2 Continue Block Transfer enable.

0 disables the continuous block transfer mode and Bit 1 of this register will
be cleared when the last byte of the block is transferred. 1 enables the
continuous block transfer mode and Bit 1 of this register will not be
cleared and SRC Address Counter/DST Address Counter/Byte Length
Counter will be reloaded with their corresponding registers when DMA2
finishes the block transfer.

R/W

DMA2 Priority,
0: DMA2 low priority, 1: DMA2 high priority When both DMA1 Priority and
DMA2 Priority are set or cleared simultaneously, the priority is in the style
of the first start one which is also the first end one.

R/W

3:2

External DRQ trigger select

00
DRQ2A, UART2 RX DRQ
01
DRQ2B, ADCFIFO RX DRQ
10
DRQ2C, external input I2S DRQ
11
DRQ2D, SPDIF RX DRQ
If ADC FIFO DRQ is selected ,the DMA Clock should be a quarter of MCU
clock.
If I2S DRQ is selected, the DMA Clock should be HOSC and there is no
wait in DMA2.

R/W

00

External DRQ trigger enable,

0: disable external DRQ trigger, 1: enable

R/W

4.21
Bits

Register21--DMA2 Command Register (Back)

Description

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4.22

DMA2 Start.
After TC the bit will be cleared. The low-go-high edge of this bit will load
SRC start address, DST start address, byte count into current working
counters.

R/W

Access

Reset

CTC1 enable, 0 disable(default), 1 enable

RW

pre-scale, /1, /2 /3 /4 .. /128.

Clock source of CTC is from HOSC.

R/W

xxxxxxx

Access

Reset

RW

Access

Reset

RW

Access

Reset

Register22--CTC Prescale Register(Back)

Bits
7
6:0

4.23

Description

Register23--CTC T Period Low Register(Back)

Bits
7:0

4.24

Description
TPERIOD[7:0], period low byte register of CTC

Register24--CTC T Period High Register(Back)

Bits
7:0

4.25

Description
TPERIOD[15:8], period register of CTC

Register25--DMA/CTC IRQ Status Register(Back)

Bits

Description

CTC IRQ pending

RW

DMA2 Half Transfer IRQ pending

RW

DMA2 End Transfer IRQ pending

RW

DMA1 Half Transfer IRQ pending

RW

DMA1 End Transfer IRQ pending

RW

SIRQ- pending,writing 1 to this bit will clear it.

RW

Reserved.

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4.26

software controlled DMA1/DMA2 reset signal,

The low-go-high edge of this bit will generate a pulse to reset
DMA1/DMA2 state machine, bytes counter, and clear H.W DRQ status
etc. After the pulse the bit will be cleared to 0.

RW

Access

Reset

RW

Register26--Master Interrupt Status Register(Back)

Bits

Description

ADC interrupt(3), READ ONLY

KeyBoard(1), Writing 1 to this bit will clear the bit, otherwise the bit is
unchanged

RTC interrupt(3), READ ONLY

DMA/CTC/SDRAM/Cmos sensor interrupt(3), READ ONLY

SIRQ/ATAIRQ/I2C/SPI/RB interrupt(3), READ ONLY

USB interrupt(5), READ ONLY

UART/IR/SPDIF interrupt(2), READ ONLY

DSP interrupt(1) pending, when dspirq disable, if the DSP irq occurs, this
bit will still be set to 1. Writing 1 to this bit will clear the bit, otherwise
unchanged

RW

Access

Reset

4.27
Bits

Register27--Master Interrupt Enable Register(Back)

Description

ADC interrupt Enable, 0 disable, 1 enable

RW

Key Board IRQ Enable, 0 disable, 1 enable

RW

RTC interrupt Enable, 0 disable, 1 enable

RW

DMA/CTC/SDRAM/Cmos sensor interrupt Enable.

0: disable, 1: enable

RW

SIRQ/ATAIRQ/I2C/SPI/RB interrupt enable.

0: disable, 1: enable

RW

USB interrupt Enable, 0 disable, 1 enable

RW

UART/IR/SPDIF interrupt Enable, 0 disable, 1 enable

RW

DSP interrupt Enable, 0 disable, 1 enable

RW

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4.28

Register28--Flash Controller Nand Enable Register(Back)

Bits

Description

Access

Reset

Reserved.

RW

Data Ready IRQ Enable.0:disable, 1:enable.

RW

Reserved.

enable Nand Flash access on Bank 3,ie. CE3-. 1 enable.

RW

enable Nand Flash access on Bank 2,ie. CE2-. 1 enable.

RW

enable Nabd Flash access on Bank 1,ie. CE1-. 1 enable.

RW

Flash Mode select, 0 old mode, 1 new mode

If 2 or more Nand Flash are used, only one can be enabled at one time.

RW

Nand Flash State Machine Status, Read Only,

0: the state machine is in its idle state.
1: the state machine is busy. When CE1- or CE2- enables, enable the
ALE and CLE output. CE1-, CE2- should be controlled separately, each of
them can use 1.8v or 3.3v.

Access

Reset

RW

Note: 1.8V power requirements: 1.65V

1.95V.

3.3V power requirements: 2.70V

3.60V.

4.29

Register29--Flash Controller Address/DMA5 Select Register(Back)

Bits

Description

Data Ready IRQ pending,

the bit will be set to 1 when low-go-high edge of the R/B- signal occur,
writing 1 to this bit will clear it.

Ready/Busy Status bit. It indicates that the flash current status.

DMA5 End Transfer or 16Bytes Spare End flag, the bit will be set to 1
when DMA5 finishes DATA or Spare transfer, writing 1 to this bit will clear
the bit. Hardware will automatically clear this bit when MCU sends the
next command.

RW

DMA5 wait state Select,

Bit4 3 wait state
00
0 wait state
01
1 wait state
10
2 wait states
11
3 wait states

RW

00

4:3

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2

DMA5 Waits H/L Level Select.

1:flash R-/W- low Level, 0: flash R-/W- high Level.

RW

RW

00

Address Cycle Mode Select

Bit 1 0 Address Cycle Mode
00
5 Cycle Mode
01
4 Cycle Mode
10
3 Cycle Mode
11
reserved

1:0
Cycle mode

Erase
(Row)

W/R
(Col+Row)

LB
(Col)

SB
(Col)

5 cycle mode

4 cycle mode

3 cycle mode

DMA5 Buffer Registers are memory (zram) mapping registers. see register 2bh for the details.

4.2A Register2A--Flash COMMAND register(Back)

Bits
7:0

Description

Reset

Flash COMMAND [7..0]

Access

4.2B Register2B --Flash Controller ECC control Register(Back)

if ECC Enable bit 0 the ECC generated after writing 256 bytes data or read back will be stored in

ECC[13..0] and ECC[13..0].

ECC is only for Hamming Code. 1bit correction & 2bit detection.
Bits

Access

Reset

Memory MAP Address Select,

Bit 7 6 Memory MAP
0 0 [3fc0-3fcfh]
0 1 [3fd0-3fdfh]
1 0 [3fe0-3fefh]
1 1 [3ff0-3fffh]

RW

00

Reserved to 0.

RW

User ECC storage control bit.

0:normal, The twelfth and The 13th byte will store ECC3.
1: The twelfth and The 13th byte will store the seventh and the eighth
byte of user data.

RW

7:6

Description

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Bit[3-2] : ECC type
Bit 3 2
ECC Type
00
128 bytes ( 20 bits ECC )
01
256 bytes ( 22 bits ECC )(default)
10
512 bytes ( 24 bits ECC )
11
2k bytes ( 28 bits ECC )

RW

01

ECC Storage Select, 0: Flash ECC Register storage ECC1,

1: Flash ECC Register storage ECC2

RW

1 BIT ECC Enable. 1: enable, 0: disable.

RW

Access

Reset

3:2

4.2C Register2C --User ECC Register0 (Back)

Bits

Description

ECC 5

ECC5

ECC 4

ECC 4

ECC 3

ECC3

ECC 2

ECC2

Access

Reset

4.2D Register2D --User ECC Register1(Back)

Bits

Description

ECC 1

ECC1

ECC 0

ECC0

Reserved

3:0

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4.2E

Register2E--DSP Control/Status Register (Back)

Bits

Access

Reset

DSP Reset.
0: DSP reset, 1: normal operation

RW

IDM/IPM option select, DUMMYS[0:2]

RW

000

DSP phase timing control.

0: normal phase, 1: extended IPM/IDM Read

RW

DSP clock select, 0 from PLL, 1 from HOSC

RW

DSPCKEN.
0: DSP CLK=DC(LOW), 1: enable CLK toggle to DSP.

RW

IRQ2DSP-.
0: asserts IRQ2- to DSP core to interrupt DSP by MCU

RW

Access

Reset

1001

7
6:4

4.2F

Description

Register2F--DSP Boot Mode Register (Back)

Bits
7:4

Description
Chip Version 1001B

( read only )

Reserved.

CE3- Multiplexed Select.

0: normal as CE3-, if SD Card is enabled, CE3- is used as MMC_DAT,
1: MAP to GPO_A3.

RW

BMODE MMAP DSP BOOT

0 0 reserved
0 1 reserved
1 0 HIP boot
1 1 No boot, start at 0x000h from internal IPM

RW

11

Access

Reset

RW

Access

Reset

RW

1:0

4.30

Register30--DSP HIP Register 0(DATA) (Back)

Bits
7:0

4.31

Description
HIP DATA Register 0 [7..0]

Register31--DSP HIP Register 1(DATA) (Back)

Bits
7:0

Description
HIP DATA Register 1 [7..0]

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4.32

Register32--DSP HIP Register 2 (DATA) (Back)

Bits
7:0

4.33

Description

4.34

4.35

4.36

4.37

4.38

Access

Reset

RW

Access

Reset

RW

Access

Reset

RW

Access

Reset

RW

Access

Description
HIP DATA Register 4 [7..0]

Reset

Register35--DSP HIP Register 5 (DATA) (Back)

Description
HIP DATA Register 5 [7..0]

Register36--DSP HIP Register 6 (STATUS) (Back)

Description
HIP Status Register 6 [7..0]

Register37--DSP HIP Register 7 (STATUS) (Back)

Description
HIP Status Register 7 [7..0]

Register38--SPDIF Control Register (Back)

Bits
7

Register34--DSP HIP Register 4 (DATA) (Back)

Bits
7:0

Reset

RW

HIP DATA Register 3 [7..0]

Bits
7:0

Access

Description

Bits
7:0

Register33--DSP HIP Register 3 (DATA) (Back)

Bits
7:0

Reset

RW

HIP DATA Register 2 [7..0]

Bits
7:0

Access

Description
SPDIF enable. 0:disable,1:enable.

RW

reserved.

this bit should be set to 1.

RW

SPDIF DRQ enable. 0:disable, 1:enable.

RW

6:5

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2

SPDIF FIFO reset.

0: FIFO reset valid, 1: FIFO reset invalid.

RW

SPDIF Block In IRQ enable.0: disable, 1: enable.

RW

SPDIF Data In IRQ enable.0: disable, 1: enable.

RW

NOTES:
1. Frames, sub-frames and blocks
An audio sample is placed in a structure known as a sub-frame. The sub-frame, shown in Figure 1,
consists of 4 bits of preamble, 4 bits of auxiliary data, and 20 bits of audio data, 3 bits called validity,
user, channel status, and a parity bit. The preamble contains bi-phase coding violations and
identifies the start of a sub-frame. The audio sample word length can vary up to 24 bits and the LSB
is transmitted first. If the word length is greater than 20 bits, the sample occupies both the audio and
auxiliary data fields. If it is 20 bits or less, the auxiliary field can be used for other applications such
as voice. The parity bit generates even parity and can detect an odd number of transmission errors
in the sub-frame. When the validity bit is low, it indicates the audio sample is fit for the conversion to
analog. The user and channel status bits are sent once per sample, and when it is accumulated
over a number of samples, then define a block of data. The user bit channel is undefined and
available to the user for any purpose. The channel status bit conveys, over an entire block, the
important information about the audio data and transmission link. Each of the two audio channels
has its own channel status data with a block structure that repeats every 192 samples.
Figure 2 the consecutive sub-frames are defined as a frame, containing channels A and B, and 192
frames define a block. The preambles that identify the start of a sub-frame are different for each of
the two channels with another unique one identifying the beginning of a channel status block.
2.

Modulation and Preambles

The data is transmitted with bi-phase-mark encoding to minimize the DS component and to allow
clock recovery from the data. As illustrated in Figure 3, the 1s in the data has transitions in the
center, and the 0s does not have after bi-phase-mark encoding.

Also, the bi-phase-mark data switches polarity at every data bit boundary. Since the value of the
data bit is determined by whether there is a transition in the center of the bit, the actual polarity of
the signal is irrelevant. Each sub-frame starts with a preamble. This allows a receiver to lock on to
the data within one sub-frame. There are three defined preambles: one for each channel and one to

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ATJ209X PROGRAM GUIDE

indicate the beginning of a channel status block (which is also channel A). To distinguish the
preambles from arbitrary data patterns, the preambles contain two bi-phase-mark violations.
Bi-phase-mark data is required to transition at every bit period, but each preamble violates that
requirement twice. In Figure 3 each bit boundary, indicated by the dashed lines, contains a
transition in the bi-phase data; Each preamble shown in Figure 4 has two bit boundaries with no
transition, which enables the receiver to recognize the data as a preamble. Since bi-phase-mark
encoding is not polarity conscious, both phases are shown in the table. Preambles X and Y
indicate a sub-frame containing channels A and B respectively. Preamble Z replaces preamble X
once every 192 frames to indicate the start of a channel status block. There are two channel status
blocks, one for channel A and one for channel B .Since there are 192 frames in a block, each
channel has a channel status block of 192 bits long. These 192 channel status bits in a block can be
arranged as 24 bytes. The blocks have one of the two formats, professional or consumer. The first
bit of the channel status block defines the format with 0 indicating consumer and 1 indicating
professional.

Figure 1

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Figure 2

Figure 3

Figure 4

28-level by 8 bits FIFO are used to buffer data for TX and RX. After receiving 192 frame- four bytes of
channel status is appended into the RX FIFO. When TX FIFO is empty and SPDIF is enabled, 0 is to
send out for all frames.

4.39
Bits

Register39--SPDIF Status Register (Back)

Description

Access

Reset

SPDIF TX FIFO Full (read only). 1: full.

SPDIF RX FIFO Empty (read only). 1: empty.

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5

SPDIF Block in IRQ pending, writing 1 to this bit will clear it, while 0
unchanged.

RW

SPDIF Data in IRQ pending,writing 1 to this bit will clear it, while 0
unchanged.

RW

SPDIF TX FIFO error Pending. Writing 1 to this bit will clear it , otherwise
unchanged.

RW

SPDIF RX FIFO error Pending. Writing 1 to this bit will clear it , otherwise
unchanged.

RW

SPDIF Receive error Pending. Writing 1 to this bit will clear it, otherwise
unchanged.

RW

Reserved.

Access

Reset

RW

4.3A Register3A--SPDIF FIFO DATA Register (Back)

Bits
7:0

Description
SPDIF FIFO DATA,
Write : SPDIF TX FIFO .
Read : SPDIF RX FIFO.

4.3B Register3B--SPDIF Channel Status Register (Back)

For RX:
There are 32 bits status per 192 frames transfer. All these 4-byte status bits are mapped into this register.
An internal read pointer is used to point to the current byte from which data will be returned at the next
read. The internal read pointer will increase after read from this register. When SPDIF receives all 192
frames of a block, SPDIF IRQ will be issued to notify MCU to read channel status. The internal pointer will
be cleared when SPDIF is issued.
For TX:
Another 4 bytes status are also implemented for transmit, which are mapped into this register also. An
internal write pointer is used to point to the byte position for the next write. When read from this register,
the internal write pointer will be cleared to point to the first byte of TX channel status. The write pointer will
move to the next byte after write to this register.
SPDIFCH(SPDIF Channel Status Register, 03Bh)

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Bits
7:0

Description

Reset

RW

Access

Reset

SPDIF Channel status

Access

4.3C Register3C--USB5V VCC Regulator Register (Back)

Bits

Description

Reserved.

1.8V Regulator Output Enable.0:disable,1:enable.

This regulator is used only for 1.8V Nand Flash and the corresponding
pins.

RW

Reserved.

RW

Reserved..

RW

Reserved. .

RW

USB 5V VCC(Regulator) voltage control

000
2.6V
001
2.7V
010
2.8V
011
2.9V
100
3.0V
**101
3.1V
110
3.2V
111
3.3V

RW

101

Access

Reset

2:0

4.3E
Bits

Register3E --USB Internal Resistor Control Register (Back)

Description

Internal Pull Up Enable. Set this bit to enable internal 1500 pull up
resistor on the D+.

R/W

Internal Resistor Enable. Set this bit to enable internal 45 precise

resistors on the D+ and D- respectively.

R/W

Internal Resistors Calibration. Set this bit to one to trig the internal
resistors calibration process which will adjust the internal precise
resistors to 45.

R/W

Plugged In Enable. Set this bit to one to enable the plugged in detector
and to switch in the two 500K pull-up resistors.

R/W

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3

Plugged In. When Plugged In Enable bit is set, this read only bit returns
a zero if both D+ and D- are high. Otherwise this bit returns a one. When
Plugged In Enable bit is zero, this bit will always return a zero. The
Plugged In Enable bit must be set to one for enough time (at least 1ms)
before the state of this bit becomes reliable.

R/W

100

Access

Reset

Note: A debounce mechanism of D+ and D- should be implemented to

filter temporary SE1 when data lines of D+ and D- transition in data
transfer.
2:0

4.3F
Bits

Value of Internal Pull Up Resistor.

0 0 0 1.1k
0 0 1 1.2k
0 1 0 1.3k
0 1 1 1.4k
1 0 0 1.5k
1 0 1 1.6k
1 1 0 1.7k
1 1 1 1.8k

Register3F --VDD & VCC voltage detect Control Register (Back)

Description

VDD voltage detect enable; 0: disable; 1: enable

RW

VCC voltage detect enable; 0: disable; 1: enable

RW

VCC voltage detect level select

**000
2.4V
001
2.5V
010
2.6V
011
2.7V
100
2.8V
101
2.9V
110
3.0V
111
3.1V

RW

000

5:3

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2:0

4.40

VDD voltage detect level select

**000
1.4V
001
1.5V
010
1.6V
011
1.7V
100
1.8V
101
1.9V
110
2.0V
111
2.1V

RW

000

Register40--High Frequency Crystal Control Register (Back)

The ATJ209X supports 24Mhz crystal, and it is the system clock source.
A low jitter PLL referenced to 24MHz is used to generate clock for DSP and for serial

communication protocols such as USB, UART, etc. The clock used in serial communications is
48MHz, so the PLL generates frequency at multiple of 48MHz to support DSP and serial
communication simultaneously. Another PLL referenced to 24MHz is used to generate 22.5792MHz
for sample rate 44.1K/22.05KHz/11.025KHz and 24.576MHz for audio sequence of 48khz.
HFCCTL(High frequency crystal control Register, 040h)
Bits

Description

high frequency crystal Oscillator enable.

0: disable, 1: enable

Power ok status. 0:power on,1:power on finished

Access

Reset

RW

5:4

when is 11, enable external DAC 96KHz fs

RW

3:2

high frequency crystal Oscillator GMMIN select bits

RW

01

1:0

MCU PLL bias current select

00
2uA
**01
3uA
10
4uA
11
5uA

RW

01

Access

Reset

4.41
Bits

Register41--PLL Performance Tune Register (Back)

Description

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7:6

PLL1 bias current select

00
2uA
**01
3uA
10
4uA
11
5uA

RW

01

5:4

PLL2 bias current select

00
2uA
**01
3uA
10
4uA
11
5uA

RW

01

Internal SRAM Bist Select. 0:ZRAM/URAM/ZRAM2,1:PM/DM

RW

RW

3
2

Internal SRAM Bist enable. 0:disable,1:enable

IST is for testing PM/DM/URAM/ZRAM2/ZRAM, the clock source is PLL1
output.

SRAM Bist finished. 0:Bist is testing,1:Bist finished.

Writing 1 to this bit will clear it.

RW

SRAM Bist Status. 0:Bist pass, 1:Bist failed.

Writing 1 to this bit will clear it.

RW

Access

Reset

RW

4.42
Bits
7

Register42-- PLL Control Register (Back)

Description
PLL1EN, PLL1 enable, 0:disable, 1:enable

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DSP clock frequency control

6:2

00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Clk for DSP DSP MIPS

24MHz
6
36MHz
9
48MHz
12
60MHz
15
72MHz
18
84MHz
21
96MHz
24
108MHz
27
120MHz
30
132MHz
33
144MHz
36
156MHz
39
168MHz
42
180MHz
45
192MHz
48
204MHz
51
216MHz
54
228MHz
57
240MHz
60
252MHz
63
264MHz
66
276MHz
69
288MHz
72
300MHz
75
312MHz
78
324MHz
81
336MHz
84
348MHz
87
360MHz
90
372MHz
93

RW

00010

PLL2EN, 0 disable PLL2, 1 enables PLL2

RW

PLL2 output select. 0: 24.576MHz for 48K sample rate series, 1:

22.5792MHz for 44.1K sample rate series.

RW

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ATJ209X PROGRAM GUIDE

4.43

Register43--RTC Control Register (Back)

6_44R
5.34GER

zH2QRI

23KTNI
4 8 3 6 1

4.34GER
)galf
wolfrevo(0.34GER
6.34GER

daol
3.34GER
erapmoC
7.34GER
A4GER
94GER
84GER
256

QRI
remiT
CTR

re tn uo c p u
ti b4 2

QRI
mralA

CSOL
7_44R

D4GER

1 256

74GER
64GER
54GER

XUM

C4GER

1 256

B4GER

RTCCTL(RTC Control Register, 043h)

Bits

Description

Access

Reset

RTC Alarm enable, 0 disable, 1 enable (POR- RESET)

RW

RTC timer enable, 0 disable, 1 enable

RW

IRQ2HZEN, 0.5 sec IRQ enable, 0 disable, 1 enable

RW

Clear RTC time counter, writing 1 to this bit will clear time counter of RTC.
After that, this bit will be cleared automatically.

RW

Load RTC time counter, writing 1 to this bit will load time counter of RTC
to RTC Time Register for host to read. After that, this bit will be cleared
automatically.

RW

10

2:1

reserved--***

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ATJ209X PROGRAM GUIDE

4.44

RTC timer overflag, Read Only, set when RTC time counter overflows,
cleared when clear RTC time counter, in other words, when write 1 to the
Bit 4 of this register.

RW

Access

Reset

Register44--RTC IRQ Status Register (Back)

Bits

Description

External Crystal OSC enable, 0: disable, 1: enable

RW

RTC clock source select, 0: internal ICOSC (about 32K), 1:32768 Crystal
OSC
If 32768Hz crystal is needed, we must write 1 to bit7, and after 1s write 1
to bit6! This bit can only changed from 0 to 1 after it is set ,it cannot be
written back with 0.

RW

Reserved.

RW

Reserved.

RW

Reserved.

RW

RTC Alarm IRQ pending bit (POR- RESET),

writing 1 to this bit will clear it.

RW

10

RTC timer IRQ pending bit,

writing 1 to this bit will clear it.

RW

2Hz IRQ pending bit, writing 1 to this bit will clear it.

RW

Access

Reset

Access

Reset

Access

Reset

4.45
Bits
7:0

4.46
Bits
7:0

4.47
Bits
7:0

Register45--RTC Time Low Register (Back)

Description
RTC Time is a up counter with 2Hz clock source
Bit 7-0: low byte of RTC Time Register

Register46--RTC Time Middle Register (Back)

Description
Middle byte of RTC Time Register

Register47--RTC Time High Register (Back)

Description
High byte of RTC Time Register

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4.48
Bits
7:0

4.49
Bits
7:0

Register48--RTC Alarm Low Register (Back)

Description
Alarm counter is a down counter with 2Hz clock source
Bit 7-0: low byte of RTC Alarm Register

Access

Reset

Access

Reset

Access

Reset

Access

Reset

Access

Reset

Access

Reset

Access

Reset

Register49--RTC Alarm Middle Register (Back)

Description
Middle byte of RTC Alarm Register

4.4A Register4A--RTC Alarm High Register (Back)

Bits
7:0

Description
High byte of RTC Alarm Register

4.4B Register4B--Losc Divider Low Byte Register (Back)

Bits
7:0

Description
LOSC Divider is a down counter with LOSC output
as clock.
Low byte of LOSC Divider Register

4.4C Register4C--Losc Divider Middle Byte Register (Back)

Bits
7:0

Description
middle byte of LOSC Divider Register

4.4D Register4D--Losc Divider High Byte Register (Back)

Bits
7:0

4.4E
Bits

Description
high byte of LOSC Divider Register.
When the Divider Counter overflows, LDIVIRQ will occur.
FLDIVIRQ = [1/(Reg4Bh+1)] *[1/(Reg4Ch+1)] *[1/(Reg4Dh+1)] *FLOSC

Register4E--Watch Dog Register (Back)

Description

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6:4

3
2:0

4.4F

Watch Dog timer enable, when WD timer is enabled and the WD timer
overflows, an internal reset (WDRST-) is generated to force the system to
reset status and then reboot.

RW

Watch Dog timer clock select,

WDCKS Clock Selected Watch Dog Length
000
1 KHz
176 ms
001
512 Hz
352 ms
010
128 Hz
1.4 s
011
32 Hz
5.6 s
100
8 Hz
22.2 s
101
4 Hz
45 s
110
2 Hz
90 s
111
1 Hz
180 s

RW

010

Clear bit, write 1 to clear WD timer, cleared automatically

RW

Reserved.

Register4F --DC to DC Control Register (Back)

Bits

Description

Access

Reset

DCOP1 and DCOP2 output enable; 0: disable; 1: enable, DC to DC uses

external NPN.

RW

VCC(DC-DC/Regulator) voltage control

000
2.6V
001
2.7V
010
2.8V
011
2.9V
100
3.0V
**101
3.1V
110
3.2V
111
3.3V

RW

101

6:4

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3:0

VDD(DC-DC/Regulator) voltage control

0000
1.6V
0001
1.7V
0010
1.8V
0011
1.9V
**0100
2.0V
0101
2.1V
0110
2.2V
0111
2.3V
1000
2.4V
1001
2.5V
1010
2.6V
1011
2.7V

RW

0100

Access

Reset

R/W

Access

Reset

Reserved.

DMA6 Busy. A logical 1 indicates the DMA6 engine is busy.

Reserved.

DMA6 BUS select. 0: 8-bit, 1: 16-bit.

RW

DMA6 Endpoint. This field determines which endpoint is using the

DMA6 channel.

R/W

R/W

4.50

Register50--USB FIFO Control Register (Back)

Bits
7:3
2
1:0

Description
Reserved.
Ep_Ptr_Chg.
FIFO Configuration. 2K bytes FIFO configuration for endpoint A and B.
As shown in section 5.

4.51

Register51USB DMA6 Control Register (Back)

Bits
7:5

Description

0: Endpoint A
0

1: Endpoint B

DMA6 Enable. Writing a 1 to this bit to start requesting DMA6 cycles. If

EOT input is asserted, or transfer count reaches zero, this bit is
automatically reset.

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4.52

Register52USB Interrupt Status0 Register (Back)

Bits

Description

Access

Reset

Setup Packet Interrupt. When set, this bit indicates a setup data packet
has been received. This bit must be cleared by writing a 1 before the next
setup packet can be received.

R/W

DMA6 Done Interrupt. When set, this bit indicates EP_TC counter
reaches zero or EOT# input has been asserted. Writing a logical 1 clears
this bit.

R/W

Reserved.

Endpoint D Interrupt. When set, Endpoint Ds EP_IRQ register should

be read to determine the cause of interrupt.

Endpoint C Interrupt. When set, Endpoint Cs EP_IRQ register should

be read to determine the cause of interrupt.

Endpoint B Interrupt. When set, Endpoint Bs EP_IRQ register should

be read to determine the cause of interrupt.

Endpoint A Interrupt. When set, Endpoint As EP_IRQ register should

be read to determine the cause of interrupt.

Endpoint 0 Interrupt. When set, Endpoint 0s EP_IRQ register should

be read to determine the cause of interrupt.

4.53

Register53USB Interrupt Status1 Register (Back)

Bits

Description

Access

Reset

Connect/Disconnect Interrupt. When set, this bit indicates an USB

cable or charger is connected or disconnected. Writing a 1 clears this bit.
This flag can wakeup MCU from DC.

R/W

R/W

R/W

6:5
4

Reserved.
Root Port Reset Interrupt. When set, this bit indicates a root port reset
has been received. Writing a logical 1 clears this bit. This flag can
wakeup MCU from DC.
Resume Interrupt. When set, this bit indicates a device resume has
occurred. Writing a logical 1 clears this bit. This flag can wakeup MCU
from DC.
Even if the corresponding enable bit is 0, when the event occur, this
status bit will still be set

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2

Suspend Interrupt. When set, this bit indicates a suspend request has
been received. Writing a logical 1 clears this bit.

R/W

Even if the corresponding enable bit is 0, when the event occur ,this
status bit will still be set .
1

Control Status Interrupt. When set, indicates an IN or OUT token

associated with Control Status Stage has been received. Writing a logical
1 clears this bit.

R/W

SOF Interrupt. When set, this bit indicates a Start Of Frame has been
received. Writing a logical 1 clears this bit.

R/W

Access

Reset

4.54

Register54USB Interrupt Enable0 Register (Back)

Bits

Description

Setup Packet Interrupt Enable.

R/W

DMA6 Done Interrupt Enable.

R/W

Reserved.

Endpoint D Interrupt Enable.

R/W

Endpoint C Interrupt Enable.

R/W

Endpoint B Interrupt Enable.

R/W

Endpoint A Interrupt Enable.

R/W

Endpoint 0 Interrupt Enable.

R/W

Access

Reset

R/W

4.55

Register55USB Interrupt Enable1 Register (Back)

Bits
7
6:5

Description
Connect/Disconnect Interrupt Enable.
Reserved.

Root Port Reset Interrupt Enable.

R/W

Resume Interrupt Enable.

R/W

Suspend Interrupt Enable.

R/W

Control Status Interrupt Enable.

R/W

SOF Interrupt Enable.

R/W

Access

Reset

4.56
Bits

Register56--USB Control Register (Back)

Description

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7:5

Go Suspend. Writing a logic 1 to this bit and the USB block enters the
suspend state. This bit is automatically reset when the resume interrupt
is set.

R/W

Root Port Resume Enable. A logical 1 enables resume from the USB
root port.

R/W

Remote Wakeup Enable. A logical 1 enables the remote wakeup from

the external WAKEUP# pin.

R/W

Send Resume. Writing a 1 to this bit will generate a resume signal to the
upstream port. This bit should be written after a device remote wakeup
has been received. This bit is automatically reset.

USB Connection. Writing a 1 connects the 1.5 k pull-up resistor on D+

line and the OPMODE of UTMI is switched to Normal. Writing a 0
disconnects the pull-up resistor on D+ line and the OPMODE of UTMI is
switched to Non-Driving.

R/W

Access

Reset

Reserved.

D+ Status. This bit reflects the status of D+ pin.

D- Status. This bit reflects the status of D- pin.

VBUS Status. This bit reflects the status of VBUS pin.

Access

Reset

4.57

Reserved.

Register57--USB Status Register (Back)

Bits
7:4

4.58

Description

USB Speed. This bit indicates the USB transfer speed.

0: Full Speed

Register58--Endpoint Index Register (Back)

Bits
7:3

1: High Speed

Description
Reserved.

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2:0

R/W

Access

Reset

R/W

R/W

R/W

Endpoint Index. This field selects a target endpoint for registers access
by microcontroller.

R/W

000: Endpoint 0
001: Endpoint A
010: Endpoint B
011: Endpoint C
100: Endpoint D

4.59

Register59--Endpoint Configuration Register (Back)

Bits
7

Description
Endpoint Enable. When set, this bit enables the endpoint.
EP0 enable bit turn on default and should not be read/written.

6:5

Endpoint Type. Endpoint 0 must be Control type.

00: Bulk
01: Interrupt
10: Isochronous
11: Reserved

Endpoint Direction.
0: OUT (Host to Device)
1: IN (Device to Host)

3:0

Endpoint Number. Valid endpoint number is from 0 to 15.

4.5A Register5A--Endpoint Control Register (Back)

Bits

Description

Access

Reset

7:6

ISO Packet Number. For ISOCHRONOUS IN endpoint only, these bits

determine the number of packets per microframe (High Speed).

R/W

00

00: one packet 01: two packets 10: three packets 11: invalid
5

FIFO Flush. Writing a logic 1 resets the pointers, status flags, and byte
count of the indexed endpoint FIFO.

Stall Endpoint. Writing a logical 1 stalls the indexed endpoint.

R/W

NAK OUT Mode. This bit is used only for OUT endpoints. In this mode, a
NAK will be returned to the host if another OUT packet is received while
the Short Packet Received Interrupt has been set.

R/W

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2

FIFO Auto-Validate. This bit is used only for IN endpoints. When set, the
SIE will automatically validate IN packet with maximum packet size.

R/W

Control Status Handshake. This bit is used only for CONTROL

endpoint. Writing a 1 clears this bit. When a setup packet has been
received, this bit is automatically set. The control status phase will be
acknowledged with a NAK if this bit is not cleared. It will be
acknowledged with ACK following OUT token or zero-length packet
following IN token if this bit is cleared.

R/W

Validate Endpoint. This bit is used for IN endpoints. Writing a logic 1

validates the data in FIFO of an IN endpoint for transmitting on next IN
token. Setting this bit will send zero-length packet to host if FIFO is
empty. This bit is automatically cleared when a short packet or a
zero-length packet has been successfully transmitted to host.

R/W

4.5B Register5B--Endpoint Status Register (Back)

Bits

Description

Access

Reset

Control Status End. This bit is used only for CONTROL endpoint. When
set, this bit indicates the status stage of control transfer is finished. This
bit is reset when the next setup packet has been received.

Reserved.

Handshake STALL. When set, this bit indicates the last packet could not
be accepted or provided, because the endpoint was stalled. Writing a 1
clears this bit.

R/W

Handshake ACK. When set, this bit indicates the last packet (received
or) transmitted has been acknowledged with ACK. Writing a 1 clears this
bit.

R/W

Handshake NAK. When set, this bit indicates the last packet (received
or) transmitted has been acknowledged with NAK. Writing a 1 clears this
bit.

R/W

Timeout. When set, this bit indicates the last packet received or
transmitted has not been acknowledged because of bus error. Writing a 1
clears this bit.

R/W

FIFO Empty. When set, this bit indicates the FIFO of indexed endpoint is
empty.

FIFO Full. When set, this bit indicates the FIFO of indexed endpoint is
full.

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4.5C Register5C--Endpoint Interrupt Request Register (Back)
Bits

Access

Reset

Short Packet Received Interrupt. This bit is used only for OUT
endpoints. When set, it indicates a short data packet has been received.
In NAK OUT Mode, the next OUT packet cannot be received if this bit is
set. Writing a 1 clears this bit.

R/W

Data Packet Received Interrupt. This bit is used only for OUT
endpoints. When set, it indicates a data packet has been received from
host. Writing a 1 clears this bit.

R/W

Data Packet Transmitted Interrupt. This bit is used only for IN

endpoints. When set, it indicates a data packet has been transmitted to
host. Writing a 1 clears this bit.

R/W

OUT Token Interrupt. When set, it indicates an OUT token has been
received. Writing a 1 clears this bit.

R/W

IN Token Interrupt. When set, it indicates an IN token has been

received. Writing a 1 clears this bit.

R/W

Access

Reset

7:5

Description
Reserved.

4.5D Register5D--Endpoint Interrupt Enable Register (Back)

Bits
7:5

Description
Reserved.

Short Packet Received Interrupt Enable.

R/W

Data Packet Received Interrupt Enable.

R/W

Data Packet Transmitted Interrupt Enable.

R/W

OUT Token Interrupt Enable.

R/W

IN Token Interrupt Enable.

R/W

4.5E

Register5E--Endpoint MaxPacketSize0 Register(Back)

Bits

Description

Access

Reset

7:0

Endpoint MaxPacketSize [7:0]. This register determines the lower byte

of the maximum packet size of indexed endpoint.

R/W

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4.5F

Register5F--Endpoint MaxPacketSize1 Register (Back)

Bits

Description

Access

Reset

DMA6 Valid Enable. This bit is used only for endpoint A and B. 1: Enable
0: Disable

R/W

R/W

6:3

Reserved.

2:0

Endpoint MaxPacketSize [10:8]. This field is used only for endpoint A

and B. This field determines the higher byte of the maximum packet size
of the indexed endpoint.

4.60

Register60--Endpoint Data Register (Back)

Bits

Description

Access

Reset

7:0

Endpoint Data. This register provides access for a microcontroller to the

FIFO of the indexed endpoint.

R/W

Access

Reset

Access

Reset

4.61

Register61--Endpoint Byte Count0 Register (Back)

Bits
7:0

Description
Endpoint Byte Count [7:0].
For OUT endpoint, this indicates the number of valid bytes in FIFO.
For IN endpoint, this indicates the number of empty bytes in FIFO.

4.62

Register62--Endpoint Byte Count1 Register (Back)

Bits

Description

7:3

Reserved.

2:0

Endpoint Byte Count [10:8]. This field is used only for endpoint A and
B.

Access

Reset

For OUT endpoint, this indicates the number of valid bytes in FIFO.
For IN endpoint, this indicates the number of empty bytes in FIFO.

4.63
Bits

Register63--Endpoint Transfer Count0 Register (Back)

Description

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7:0

4.64

Endpoint Transfer Count [7:0]. This register is used only for endpoint A
and B. This field determines the total number of bytes to be transferred
during DMA6 transfer. For an IN endpoint, the remaining data in FIFO is
validated when this count reaches zero or EOT pin is asserted.

R/W

Register64--Endpoint Transfer Count1 Register (Back)

Bits

Description

Access

Reset

7:0

Endpoint Transfer Count [15:8]. This register is used only for endpoint
A and B. This field determines the total number of bytes to be transferred
during the DMA6 transfer. For an IN endpoint, the remaining data in FIFO
is validated when this count reaches zero or EOT pin is asserted.

R/W

4.65

Register65--Endpoint Transfer Count2 Register (Back)

Bits

Description

Access

Reset

7:0

Endpoint Transfer Count [23:16]. This register is used only for endpoint
A and B. This field determines the total number of bytes to be transferred
during DMA6 transfer. For an IN endpoint, the remaining data in FIFO is
validated when this count reaches zero or EOT pin is asserted.

R/W

Access

Reset

R/W

4.66

Register66--USB Register Page Index (Back)

Bits
7:3

Description
Reserved.
USB Register Page Index. Registers of 67h-6Fh are selected by these
bits.
000: USB Control Registers

2:0

001: Reserved.
010: Reserved.
011: Reserved.
others: Reserved

Note: When USBREGPGIDX(66h)=00h, the registers of 67h-6Fh are USB Control Registers and they
listed below for detail.

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4.67

Register6--Device Address Register (Back)

Bits
7
6:0

4.68

Description

Access
/

USB Device Address. This field specifies the USB device address
assigned by the host controller.

R/W

0000000

Access

Reserved.

Reset

Reset

Register68--USB Test Modes Register (Back)

Bits

Description

7:3

Reserved.

2:0

Reserved.

R/W

000

4.69

Register69--Frame Number0 Register (Back)

Bits

Description

Access

Reset

7:0

Frame Number[7:0]. This field contains the frame number from the last
received Start Of Frame.

Access

Reset

4.6A Register6A--Frame Number1 Register (Back)

Bits

Description

7:3

Reserved.

2:0

Frame Number[10:8]. This field contains the frame number from the last
received Start Of Frame.

000

4.70

Register70--MCU & DMA Clock Control Register (Back)

les

CSOH

]0..2[tib h00geR=M
klc08z

14XUM

M/

CSOL
LLPUCM

]0..2[tib hD3geR=N
klcamd

N/

les

CSOH
14XUM

CSOL
LLPUCM

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MCUCLK2 (MCU & DMA Clock Control 70h)
Bits

Access

Reset

MCU PLL Enable .0:disable, 1: enable.

R/W

6:3

MCU PLL output clock select.

0000
27MHz
0001
30MHz
0010
33MHz
0011
36MHz
0100
39MHz
0101
42MHz
0110
45MHz
0111
48MHz
1000
51MHz
1001
54MHz
1010
57MHz
1011
60MHz
1100
63MHz
1101
66MHz
1110
69MHz
1111
72MHz

R/W

0000

2:0

PA Antipop current tuning .

000 7uA
001 8uA
010 9uA
**011 10uA
100 11uA
101 12uA
110 13uA
111 14uA

R/W

011

Access

Reset

RW

0000000

4.71

Description

Register71--I2C Address Register (Back)

Bits
7:1

Description
I2C Slave Address.

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in master mode , R/W control bit
In slave mode: I2C Slave Address Match. 0 match ,send IRQ to MCU, 1
not match no IRQ
In master mode , address 7-bit is used to setting the slave address,so the
I2C data register just store the data.
In slave mode , address 7-bit is used to compare with the address that
master sending out.so the I2C data register can store the address and
data.

4.72

RW

Register72--UART2, Sharp IR and SIR Baud Rate Register (Back)

UART is used for asynchronous serial communication with FIFO as data buffer for full-duplex

operation. UART protocol contains a start bit, 5~8 data bits, a parity bit and a stop bit. The start bit must
be 0 and the stop bit must be 1. Before communication, UART operation mode must set to be the same
as remote terminal, such as baud rate, number of data bits, even/odd/no parity etc. Baud rate is up to
1.5MBaud and LSB first in TX/RX.
28-level by 8 bits FIFO are used to buffer data for TX and RX.
OTS

OTS

tiB ataD 8-5

RAP

langiS oN

langiS oN
tca/ataD-TRAU
tiB
tratS

lanoitpO lanoitpO

UART2, Sharp IR and SIR Baud Rate Register

Prescale
Value

13

1.625

Baud
Rate

Divisor

%Error

Divisor

600

192

0.16%

1200

96

0.16%

1800

64

2000

%Error

Divisor

%Error

0.16%

58

0.53%

2400

48

0.16%

3600

32

0.16%

256

0.16%

4800

24

0.16%

192

0.16%

7200

16

0.16%

128

0.16%

208

0.16%

9600

12

0.16%

96

0.16%

156

0.16%

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14400

0.16%

64

0.16%

104

0.16%

19200

0.16%

48

0.16%

78

0.16%

28800

0.16%

32

0.16%

52

0.16%

38400

0.16%

24

0.16%

39

0.16%

57600

0.16%

16

0.16%

26

0.16%

115200

0.16%

0.16%

13

0.16%

230400

0.16%

460800

0.16%

750000

921600

0.16%
-

2
1

0.00%
0.00%

1500000
BaudRate (UART2

Bits

Sharp IR and SIR Baud Rate Register, 072h)

Access

Reset

RW

Access

Reset

7:6

Clock pre-scale select

Bit 7 6 Pre-scale
0 0 /13
0 1 /13
1 0 /1.625
11
/1

RW

00

5:3

Bit 5: STKP, Stick parity

Bit 4: EPS, Even parity
Bit 3: PEN, Parity enable
PEN EPS STKP
Selected Parity
0 x
x
None
1 0
0
Odd
1 1
0
Even
1 0
1
logic 1
1 1
1
logic 0

RW

000

STOP select, if this bit is 0, 1 stop is generated in transmission. If this bit is

1 and 5 bits transmission is selected, 1.5 stop bit is generated. If this bit is
1 and 6/7/8 bits transmission is selected, 2 stop bits are generated. The
receiver always checks 1 stop bit only.

RW

7:0

4.73

Baud rate generator, clock division

Register73--UART2 control Register(Back)

Bits

Description

Description

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WL[1:0], bits per transmission
WL1 0
Bit per transmission
00
5 bits
01
6 bits
10
7 bits
11
8 bits

1:0

4.74

RW

00

Access

Reset

RW

Register74--UART2/IR FIFO DATA Register (Back)

Bits

Description
UART2/IR FIFO Data, writing to this port will write data to UART2/IR TX
FIFO, reading from this port will read data from UART2/IR RX FIFO

7:0

4.75

Register75--IR Control Register (Back)

Bits

Description

Access

Reset

IR_PLS, send interaction IR pulse, effective only in MIR/FIR mode. Write

1 to this bit to send a 2us interaction IR pulse at the end of the frame and
the bit is automatically cleared after sending the pulse.

RW

Data Rate of MIR, 0 for 1.152MBPS, 1 for 0.576MBPS

RW

Pulse with for IRDA-SIR, 0 for 1.6us, 1 for 3/16 of bit length

RW

4:0

reserved

NOTES:
IR can be configured to operate in 4 modes: Sharp-IR mode, IRDA-SIR mode, IRDA-MIR mode,
IRDA-FIR mode.
1. Sharp-IR mode
The same as UART, but DASK modulation is used, i.e., no IR emission for logical 1 but there is a
500KHZ pulse train for logical 0. Baud rate is up to 38.4KBaud.
2. IRDA-SIR mode
The same as UART, but the data representation is different, i.e., no IR emission for logical 1 but
there is a pulse of 1.6us or 3/16 data bit period for logical 0. Baud rate is up to 115.2Kbaud.
3. IRDA-MIR mode
Support 0.576M and 1.152M Baud
No pulse for logical 1, 1/4 data period pulse for logical 0
Packet oriented protocol: STA-STA-ADDR-DATA-CRC16-STO
STA : 8-bit beginning flag, 01111110 binary

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ADDR: 8-bit address field
DATA: 8-bit control field plus up to 2045(2048-3) bytes data field
CRC16 : CCITT 16-bit CRC, CRC(x)=x16+x12+x5+1
STO : Ending flag, 01111110 binary
Bit stuffing: Insert 0 after 5 consecutive 1, CRC is calculated before zero insertion
LSB is transmitted first
Abort sequence requires minimum of 7 consecutive 1
8 bits are used per character before zero insertion
4 .IRDA-FIR mode
4M BPS mode
4 PPM ( 4 pulse position modulation) used
2 bits encoded per bit cell, bit cell is 500ns (1/2M), pulse is 125 ns, or 250 ns
Packet oriented protocol: PA-STA-DD-STO
PA: preamble field, 16 repeated transmission of the following pattern:
1000 0000 1010 1000
STA: Start Flag, 0000 1100 0000 1100 0110 0000 0110 0000
DD: encoded data including CCITT 32-bit CRC, the polynomial for the CRC-32 is
CRC(x)=x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
STO: Stop Flag, 0000 1100 0000 1100 0000 0110 0000 0110

4.77

Register77--LRADC2 DATA Register (Back)

Bits

Access

Reset

RW

XX

Access

Reset

Reserved

UART2/IR TX FIFO FULL, read only

UART2/IR RX FIFO EMPTY, read only

7:0

4.78

Description
LRADC2 DATA[7..0]

Register78--UART2 Mode & FIFO Status Register (Back)

Bits
7:6

Description

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2:0

4.79

UART2/IR EOP, write this bit to high when next write to UART2/IR TX
FIFO is the last byte of the packet. Next write to TX FIFO after this bit is
set will clear this bit automatically. When read from this bit, the EOP status
bit of UART2/IR receiver is returned. This bit can be polled by MCU to see
if end of package is reached.

RW

Mode Select
0 0 0 UART2
0 0 1 Sharp IR
0 1 0 IRDA-SIR
0 1 1 IRDA-MIR
1 0 0 IRDA-FIR

RW

000

Access

Reset

Register79--UART2 DRQ/IRQ Enable/Status Register (Back)

Bits

Description

UART2/IR enable, 0 disable, 1 enable

RW

FIFO mode control, for all UART2 FIFOs

0 issue DRQ when vacancy in TX FIFO or issue IRQ at least 1 data in RX
FIFO,
1 issue DRQ/IRQ when TX FIFO is half empty or RX FIFO is half full

RW

UART2/IR RX FIFO error, writing 1 to this bit will clear the bit and reset the
FIFO

RW

UART2/IR receive error, 0 receive OK, 1 receive error occurs. Writing 1 to

this bit will clear the bit, otherwise the bit is unchanged.

RW

UART2/IR TX FIFO error, writing 1 to this bit will clear the bit and reset the
FIFO

RW

UART2/IR RX IRQ is pending, writing 1 to the bit to clear it, while 0

unchanged.

RW

UART2/IR IRQ enable

RW

UART2/IR DRQ enable

RW

4.7A Register7A--I2C Control Register (Back)

The ATJ2097/99 I2C can be configured as either a master or a slave device. In master mode, it
generates the clock(I2C_SCL) and initiates transactions on the data line(I2C_SDA). Data on the I2C
bus is byte-oriented. In multi-Master mode,10-bit address and Hi-speed mode are not supported. See
the I2C_Bus_Specification_1995 for the detailed information

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Pull-up resistors are required on both of the I2C lines as all of the I2Cdrivers are open drain.
Typically the external 2k-Ohm resisters are used to pull the signals up to VCC.

L C Sf
W
HGIHt
OLt
/1
gnimiT ecafretnI C2I

A T S : U St

LCS
ft
O
TS:USt

T
A D : D Ht

ft
T A D : D Ht

F U Bt
A
TS:DHt

ADS

I2CCTL(I2C Control Register, 07Ah)

Bits

Description

Access

Reset

I2C Enable, 0:disable, 1: enable I2C receive and transmit channel Before
enable this bit,mode should be changed to F1, and then change to other
mode.

RW

In master mode, operating mode select. 0: standard (100kbps), 1: fast

(400kbps)In slave mode, Start IRQ enable.----0: disable, 1: enable

RW

I2C IRQ enable, 0:disable, 1:enable

RW

I2C master or slave select . 0:master, 1:slave

RW

3:2

I2C cond[1..0]. generate a bus control .(master mode only)

0 0 no effect
0 1 generate start condition
1 0 generate stop condition
1 1 SCL will be released to high level to generate repeated start
condition

RW

00

Writing 1 to this bit will release the clock and data line to idle in slave
mode only and it will be cleared atuomatically. MCU should write 1 to this
bit after receiving the last bit of a whole transfer.

RW

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In transmitting ack ----ACK enable. Controls generation of an ACK signal

in receive mode0do not generate an ack at 9th SCL, 0generate an ack
signal at 9th SCL. In receiving ack ---Last Received Bit. Use the read only
bit to check for ACK signals from the receiver (slave), or to monitor SDA
operation of SDA when writing 11 to control reg bit[3..2] for the repeated
starts.

RW

4.7B Register7B--I2C Status Register (Back)

Bits

Description

Access

Reset

I2C Buffer Flag. Automatically cleared when I2C data reg is written or read
Automatically set when the buffer is empty in transmit mode or when the
buffer is full in receive mode. Writing 1 to this bit will clear it.
transmit
0--transmit in progress
1--transmit complete
receive
0---receive in progress
1---receive complete

RW

I2C STOP bit. This bit is cleared when the I2C mode is disable or when
the start bit was detected last. Writing 1 to this bit will clear it.
1---indicate that the STOP bit was detected last
0---STOP bit was not detected last

RW

I2C START bit. This bit is cleared when the I2C mode is disable or when
the stop bit was detected last. Writing 1 to this bit will clear it.
1---indicate that the START bit was detected last
0---START bit was not detected last

RW

I2C R/W bit.

Read/Write bit information. This bit holds the R/W bit information following
the last address match. This bit is valid only from the address match to the
next start bit, stop bit or NAK bit.
1---Read
0---Write

RW

I2C D/A. Data/Address bit

1---indicate the last byte received or transmitted is data
0---indicate the last byte received or transmitted is address

RW

I2C IRQ pending bit. Writing 1 to this bit will clear it.

RW

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I2C writing collision detect bit. Writing 1 to this bit will clear it.
1---the I2C data register is written while it is still transmitting the previous
byte
0---no collision

RW

I2C overflow bit. Writing 1 to this bit will clear it.

1---a new byte is receiving while the previous byte has not been read
0---no overflow

RW

Access

Reset

RW

Whenever writing collision or overflow is set, NAK will occur automatically.

4.7C Register7C--I2C Data Register (Back)

I2CDAT(I2C Data Register, 07Ch)
Bits

Description
I2C Data/Address[7:0]

7:0

4.7D Register7D--SPI Control Register(Back)

The ATJ2097/99 SPI can be configured as either a master or a slave device. During an SPI
transfer, data is shifted out and shifted in(transmitted and received) simultaneously. The SPI_SCK line
synchronizes the shifting and sampling of the information. It is an output when the SPI is configured as a
master or an input when the SPI is configured as a slave.
gnimiT ecafretnI IPS
HCt

PCt

LCt
KLCS
HOt

0D
0D

5D

6D

SOt
7D

NID
TUOD

7D
ODt

SPICTL (SPI Control Register, 07Dh)

Bits
7

Description
SPI Enable,
0:disable, 1: enable SPI receive and transmit channel

Access

Reset

RW

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6

SPI master/slave select, 0:master, 1:slave

RW

SPI Clock Polarity Select (CPOS)

0: Active high clocks selected; SPI_SCK idles low
1: Active low clocks selected; SPI_SCK idles high

RW

SPI pin ss control output, this bit is valid only in master mode
1---output high(default)
0---output low .

RW

SPI Transfer CompleteThis bit is set to 1 at the end of an SPI transfer,

and cleared by an read or write to the SPI Data Register.

RW

SPI Write Collision Error FlagThis bit is set if the SPI Data Register is
written before the end of transfer is signaled, and cleared by reading the
SPI Control Register with this bit set, followed by an access of the SPI
Data Register

RW

SPI IRQ Enable, 0:disable, 1:enable

RW

SPI IRQ pending flag, 0: no IRQ pending 1: has IRQ pending, cleared by
writing 1 to this bit when the bit has been set to 1.

RW

Access

Reset

SPI Clock Divide Factor (SPICKFactor) [7:1]

RW

1111111

Reserved to 0.

RW

Access

Reset

RW

Access

Reset

RW

4.7E

Register7E --SPI Clock Divide Control Register (Back)

Bits
7:1
0

Description

SPI_CLK=MCUCLK/(SPICKFactor[7:0])

4.7F

Register7F --SPI Data Register (Back)

Bits
7:0

4.80
Bits

Description
SPI Data[7:0]

Register80 --DAC Control Register (Back)

Description
External I2S DAC pad enable.0: disable,1:enable.
GPIO_K4 map to DAC_MCLK
GPIO_K6 map to DAC_LR
GPIO_K5 map to DAC_DATAIN
GPIO_K3 map to DAC_Bitclk

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6

External I2S input/output.0:output,1:input.

When I2S is used as input,it can support 24bit only

RW

Internal DAC enable. 0:disable, 1:enable.

RW

External I2S DRQ Destination Select.

0:Int.DAC and DMA2 Sel,1:DMA2 Sel.

RW

Internal DAC MODE.

0: external output I2S DAC,1:on-chip Sigma-Delta

RW

Int. DAC digital output enable, 0 disable, 1 enable

RW

Internal DAC Mute.

0: enable DAC Playback, 1:mute DAC Playback

RW

Internal DAC Quantization bit select.

0: 2 bits, 1: 1 bit quantization

RW

Access

Reset

RW

000

4.81

Register81 --DAC Sample Rate Control Register(Back)

Bits

Description

Reserved

I2S input sample rate ready.0: not ready,1:ready.

Writing 1 to this bit will clear it.

5:3

I2S input sample rate.

000 reserved
001 32KHz
010 44.1KHz
011 48KHz
100 reserved
101 64KHz
110 88.2KHz
111 96KHz

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2:0

4.82

DACSR[2:0], Sample rate of Internal DAC

IO42h-Bit0=0 DAC SR[2:0] Fs
000
48KHz
001
32KHz
010
24KHz
011
16KHz
100
12KHz
101
8KHz
11x
reserved
IO42h-Bit0=1 DAC SR[2:0] Fs
000
44.1KHz
001
reserved
010
22.05KHz
011
reserved
100
11.025KHz
101/110/111
reserved

Reset
xxxx

Access

Reset

Internal DAC PCM[3:0]

3:0

Reserved

xxxxxxxx

Register83 --Internal DAC PCM Out Middle Register (Back)

Bits

4.84

Access
W

Description

7:4

7:0

000

Register82 --Internal DAC PCM Out Lo Register (Back)

Bits

4.83

RW

Description
Internal DAC PCM[11:4]

Register84 --Internal DAC PCM Out High Register (Back)

Bits

Description

Access

Reset

7:0

DAC PCM[19:12]
Write to this register will transfer 20-bit PCM data into DAC PLAYBACK
FIFO These 82h/83h/84h ports are also mapped into a 24-bit DSP
memory mapped EM port 0x3FEDh. When DSP write, D23-D4 are written
into the FIFO, D3-0 are discarded.

xxxxxxxx

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4.85

Register85 --FIFO Status Register (Back)

DACFIFOSTA(DAC FIFO Status Register, 085h)

Bits

Access

Reset

Reserved

Internal DAC PLAYBACK FIFO FULL flag, Read Only

The above bits are also mapped into a 24-bit DSP memory mapped EM
port 0x3FEEh, low byte of this port.
DSP3FEEh.bit0: reserved
DSP3FEEh.bit1: reserved
DSP3FEEh.bit2: Internal DAC FIFO FULL

Internal DAC FIFO counter reset control.

0: reset valid 1: reset invalid

RW

DAC QU[3:0], quantizer level=[3*(22+QU[3:0])]/64,

Default=81/64=1.27

RW

0101

Access

Reset

7:6

3:0

4.86

Description

Register86 --Internal DAC Dither Control Register Back)

DACCTL (internal DAC Dither Control Register, 086h)

Bits

Description

7:6

Reserved

5:4

LRADC2 temperature detecting setting

00 30 degree
01 40 degree
10 45 degree
11 55 degree

RW

00

DAC Dither Enable, 0 disable(default), 1 enable

RW

DAC Dynamic Dither Enable, 0 disable, 1 enable (default)

RW

Dither Amplitude
**1 1
x1
10
x 1/2
01
x 1/4
00
x 1/8

RW

11

1:0

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4.87
Bits

7:6

5
4:0

4.88
Bits

Register87--Internal DAC Analog Output Volume Control Register (Back)

Description

Access

Reset

The bias current select for DAC REF (VRDA) buffer

00
6uA
*01
10uA
10
14uA
11
18uA

RW

01

OP used in DAC Add bias current select, 0: normal , 1: normal *1.5

RW

Master/Headphone Amp Volume control Bit, total 32 level, -1.8dB/step.

RW

00000

Access

Reset

Register88--Internal DAC Analog Block Control Register (Back)

Description

DACEN, enable analog circuit of the internal DAC.

0: disable, 1: enable.

RW

MIXEN, analog mixer and PA enable. 0: disable, 1: enable

RW

5:4

The bias current select for OPDA1/OPDA2 ,first & second stage
**00 4uA
01
7uA
10
10uA
11
13uA

RW

00

3:2

The bias current select for OPDA3,third stage.

**00 4uA
01
7uA
10
10uA
11
13uA

RW

00

1:0

The bias current select for the power amplifier (OPO)

**00
smaller
01
normal
10
bigger
11
biggest

RW

00

Access

Reset

4.89
Bits

Register89 USB DMA6 Address0 Register (Back)

Description

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7:0

R/W

Access

Reset

R/W

Access

Reset

RW

000

DMA6 Address[7:0]. This field contains the source or destination

address[7:0] for UDMA(DMA6) engine which only accesses the B1+B2
RAM.

R/W

01

4.8A Register8A USB DMA6 Address1 Register (Back)

Bits

Description

7:5

Reserved.

4:0

DMA6 Address[12:8]. This field contains the source or destination

address[13:8] for UDMA(DMA6) engine which only accesses the B1+B2
RAM.

4.8B Register8B USB DMA6 Clock Register (Back)

Bits
7:5

Description
MCU accessing USB BLOCK wait states select.
0 0 0 no wait
0 0 1 1 wait
0 1 0 2 waits
0 1 1 3 waits
1 0 0 4 waits
1 0 1 5 waits
1 1 0 6 waits
1 1 1 7 waits

4:2

Reserved.

1:0

DMA6 Clock. These bits are used to select the clock at which the DMA6
engine accesses the USB endpoint FIFO in 16 bits.
00: 30M
01: 20M
10: 15M
11: 7.5M

4.8C Register8C --USB Global Control Register (Back)

Bits

Description

Access

Reset

USB Global Reset. This bit should be set to one by firmware for normal
operation.

R/W

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USB Mode Select. The two bits are used to select USB mode, only in F7
mode, USB can work in abnormal mode.
6:5

00: normal mode

R/W

R/W

R/W

01: external PHY mode

R/W

R/W

10: Reserved
11: Reserved
Memory Mode Select. This bit is used to select access mode and
source clock of synchronous memory used as FIFO by SIE.
4

0: USB FIFO
1: general memory

3
2
1
0

Software VBus. This bit is used to simulate 5V VBus connection.

0: normal

1: software connection

Reserved.
PHY PLL 12M Source Select.
0: 24M/2

1: external 12M

MCU Wakeup Enable. A logical 1 enables USB wakeup MCU from DC.

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4.8D Register8D--DMA4 Control and Status Register (Back)
Bits

Description

Access

Reset

7:5

DMA4 Destination Memory Select

0 0 0 IPML
0 0 1 IPMM
0 1 0 IPMH
0 1 1 SDRAM
1 0 0 IDML
1 0 1 IDML
1 1 0 IDML
1 1 1 ZRAM2(B1+B2) if usb is accessing B1 mem,DMA4 will access B2
mem, vise versa.
If SDRAM is selected and DMA4 DRQ is enabled, then the bridge
between SDRAM and Sensor will be enabled, otherwise disabled.
When the bridge enabled, the data writing to SDRAM is not the same, it is
decided by the software stopping the bridge, Another way the bridge is not
bidirectional, the data stream is from sensor to SARAM

RW

000

Vsync or SAV IRQ pending, 0: no irq occurred, 1: irq occurred. Writing 1 to

this bit will clear it.

RW

Hsync End or EAV IRQ pending, 0: no irq occurred, 1: irq occurred .writing
1 to this bit will clear it.

RW

GPIOK[7..2] enable. 0:disable, 1:enable.

RW

GPIOK2 used as CKOUT(clk=24MHz). 0:disable, 1:enable.

RW

DMA4 Busy Status. 0: idle, 1:busy. (read only)

RW

Access

Reset

4.8E
Bits

Register8E--GPIOK[7..0] Input and Output Enable (Back)

Description

GPIOK7 bidirection control. 0:output, 1: input

RW

GPIOK6 bidirection control. 0:output, 1: input

RW

GPIOK5 bidirection control. 0:output, 1: input

RW

GPIOK4 bidirection control. 0:output, 1: input

RW

GPIOK3 bidirection control. 0:output, 1: input

RW

GPIOK2 bidirection control. 0:output, 1: input

RW

GPIOK1 bidirection control. 0:output, 1: input

RW

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0

4.8F

GPIOK0 bidirection control. 0:output, 1: input

4.90

4.91

Access

Reset

RW

Access

Reset

Description
Data[7..0]

Access

Reset

Register90--ITU-R601 XY Data Register (Back)

Bits
7:0

Register8F--GPIOK[7..0] Data Register (Back)

Bits
7:0

RW

Description
Data[7..0]

Register91--DMA4 Destination Address high (Back)

Bits

Description

GPIOK2 output clock division.

0: /1 , 1: /2

RW

GPIOK[1..0] enable. 0:disable,1:enable.

RW

DMA4DAdd[13..8]

RW

xxxxxx

Access

Reset

5:0

4.92

Register92--Cmos Sensor Control Register (Back)

Bits

Description

Cmos Sensor Enable. 0:disable, 1:enable

RW

Hsync active .
0: Hsync IRQ active low, 1: Hsync IRQ active high

RW

Vsync active .
0: Vsync IRQ active low, 1: Vsync IRQ active high

RW

Video Format Select. 0: CCIR656, 1:CCIR601

RW

DMA4 DRQ enable. 0:disable, 1: enable

RW

Vsync or SAV IRQ Enable. 0:disable,1: enable

RW

PCLK active edge. 0:positive edge, 1: negative edge

RW

Hsync End or EAV IRQ Enable. 0:disable, 1:enable

RW

Memo:
Video Format.

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in CCIR656 Vsync and Hsync are used to synchronize.
in CCIR601 4 consecutive bytes (ff, 00, 00, xy) can synchronize the data transmitting. xy
involves the information of start or end of the frame.
Vsync IRQ and Hsync End IRQ issued when the corresponding signal is active
DMA4 is started through the DMA4 DRQ Enable Bit, if it is set to 0, and DMA4 will be stopped.
So DMA4 can be restarted again if the bit is set.

4.93

Register93--Hsync Start Position Low (in pclk) (Back)

Bits
7:0

4.94

Description

Reset

RW

HSP[7..0]

Access

Access

Reset

Register94--Hsync Start & End Position High (in pclk) (Back)

Bits

Description

7:5

HSP[10..8]

RW

4:0

HEP[12..8]

RW

Access

Reset

RW

Access

Reset

RW

Access

Reset

4.95

Register95--Hsync End Position Low (in pclk) (Back)

Bits
7:0

4.96

Description
HEP[7..0]

Register96--Vsync Start Position Low (in Hsync) (Back)

Bits
7:0

4.97

Description
VSP[7..0]

Register97--Vsync Start & End Position High (in Hsync) (Back)

Bits

Description

7:5

VSP[10..8]

RW

xxx

4:2

VEP[10..8]

RW

xxx

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PCLK Delay
00
11ns
01
15ns
10
5ns
11
7ns

1:0

RW

00

Hsync start and end position calculate from its active

Vsync start and end position calculate from its active.
In addition , some cmos sensors do not have Hsync and Vsync but have frame_valid and
Line_valid, in this way, these registers should be filled with 0.
g n im i T ro s n eS SO M C
8t

C NY S V
FE R H
6t

7t

4t

5t

K L CP
1t
3t
2t
084

9 74

87 4

] 0: 7 [Y

a t aD d i la V

gnimiTlatnoziroH

4.98

Register98--Vsync End Position Low (in Hsync) (Back)

Bits
7:0

4.99
Bits

Description

Reset

RW

VEP[7..0]

Access

Access

Reset

Register99--DMA4 Destination Address Low (Back)

Description

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ATJ209X PROGRAM GUIDE

7:0

DMA4DAdd[7..0]

RW

4.9A Register9A--AUDIO ADC Data Register (Back)

Bits

Description

Access

Reset

7:0

AUDIO ADC data

If ADC is in 16-bit mode, read from left channel for low byte first, then high
byte, finally read from right channel for low byte and high byte.
If ADC is in 18-bit mode, read from left channel for low byte first, then
middle byte,then high byte, finally read the right channel for low byte,
middle byte and high byte.

Access

Reset

SPDIF/UART/IR 48MHz clock source select.

0:from HOSC, 1:from PLL1

RW

6:5

LRADC1 Fs Select.
00
200Hz
01
100Hz
10
50Hz
11
25Hz

RW

00

4:3

LRADC2 Fs Select.
00
200Hz
01
100Hz
10
50Hz
11
25Hz

RW

2:1

BATTERY ADC FS select

00
200Hz
**01
100Hz
10
50Hz
11
25Hz

RW

00

Audio adc bus control. 0: 16-bit ADC; 1: 18-bit ADC.

RW

Access

Reset

RW

4.9B Register9B--Audio ADC Control Register 0 (Back)

Bits
7

Description

4.9C Register9C --BATTERY ADC DATA Register (Back)

Bits
7:0

Description
BATTERY ADC DATA[7..0]

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ATJ209X PROGRAM GUIDE

BATTERY

ADC

Power mode[00]=00 Reg (09Ch)

VBAT(V)

Typic Value

0.7

00

0.8

0D

0.9

1E

1.0

30

1.1

40

1.2

51

1.3

62

1.4

73

1.5

84

1.6

94

1.7

A6

1.8

B6

1.9

C7

2.0

D9

2.1

E8

2.2

F9

BATTERY

ADC

Power mode[10]=10 Reg (09Ch)

VBAT(V)

Typic Value

2.6

62

2.8

73

3.0

84

3.1

8C

3.2

95

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ATJ209X PROGRAM GUIDE

BATTERY ADC Power mode[10]=11 Reg(09Ch)
VCC should be about 3.1v and above 2.9v
VBAT(V)
3.3

A0

3.4

A7

3.5

AF

3.6

B8

3.7

C0

3.8

4.9D

Typic Value

C9

Register9D --External input I2S DATA Register (Back)

Bits
7:0

Description

Reset

RW

External input I2S DATA[7..0]

Access

It is normally used as DMA source address. When DMA works, it should be in accordance with the
sequence Hi, Mid and Low.

4.9F
Bits

Register9F--Audio ADC Modulator Performance Tuning Register (Back)

Description

Access

Reset

7:6

Modulator first stage input CAP select

00=0.3p
01=0.4p
10=0.5p
11=0.6p

RW

01

5:4

Modulator first stage feedback CAP select:

00=0.15p
01=0.2p
10=0.25p
11=0.3p

RW

01

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3:2

Modulator second stage input CAP select

00=0.5p
01=0.6p
10=0.7p
11=0.8p

RW

11

1:0

Modulator second stage feedback CAP select

00=0.15p
*01=0.2p
10=0.25p
11=0.3p

RW

01

Access

Reset

R/W

4.A0

RegisterA0-A7 ATA Decode Registers (Back)

RegisterA0 16Bit DATA Register (16 Bit data,0A0h)

Bits
7:0

Description
st

16Bit DATA Register( 1 LOW Byte,2

nd

HI Byte)

IO port: A0h~A7h, R/W

When CS0- = 0,CS1- = 1 Decode to Command block registers;
When CS0- = 1,CS1- = 0 Decode to Control block registers
CS0,CS1s configuration to see IO port 0AAH bit0-1.
When data bus is 8-Bit data bus, read or write data, it only needs to operate register a0h continuously.
When data bus is 16-bit data bus, read or write data, reading or writing low byte first, then high byte

In DMA66 translating, the host shall negate CS0-, CS1-, DA2, DA1and DA0.
ATA I/O Register Decode Table
Register name

ATA register
CS0-

CS1-

DA2

DA1

CPU Register

DA0

Command block registers

0

Data *

0A0H

Error/Features

0A1H

Sector Count

0A2H

Sector Number

0A3H

Cylinder Low

0A4H

Cylinder High

0A5H

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0

Device Head

0A6H

Status/Command

0A7H

For device, data register can be 8 bits or 16 bits.

In PIO mode, whether the device is 8-bit or 16-bit is decided by the signal IO16CS- .
High level for 8-bit, low level for 16-bit.
ATADECO(ATA Decode Registers, 0A0h~0A7H)
Bits

Description

7:0

4.A8

ATA Decode Registers

Access
RW

Reset
0

RegisterA8--DMA66 Destination/Source Address0 (Back)

Bits

Description

7:0

4.A9

DMA66 Destination/Source Address0

Access
RW

Reset
X

RegisterA9--DMA66 Destination/Source Address1(Back)

Note: Data in bursting is Destination Address

Data out bursting is Source Address
Bits

Description

Access

7:0

DMA66 Destination/Source Address1

RW

Reset
X

4.AA RegisterAA--DMA66 Destination/Source Memory Select (Back)

Bits

Description
7

6:4

Reserved.

Access

Reset

Extended IPM/IDM page address bit.

Bit 6 5 4
Accessed Block
000
IPM low byte
001
IPM middle byte
010
IPM high byte
011
reserved
100
IDM low byte
101
IDM middle byte
110
IDM high byte
111
ZRAM2 (B1+B2)(4000h---57FFh)

RW

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ATJ209X PROGRAM GUIDE

3

HDD & SDRAM Bridge Enable 1: enable, 0: disable

RW

Reserved

Decode to device CS0 (R/W)

RW

Decode to device CS1 (R/W)

RW

4.AB RegisterAB--DMA66 Byte Counter Low Register (Back)

Bits
7:0

Description

Access

DMA66 Byte Counter Low Register

Reset

RW

4.AC RegisterAC--DMA66 Byte Counter High Register (Back)

Bits
7:0

Description

Access

DMA66 Byte Counter Hi Register

Reset

RW

Ultra DMA66 Timing

Ultra DMA66 has 5 modes. Each mode has unique timing requirement. And they are supported as below.
You can get the DMA mode information form ID word53 and ID word88, and configure them by features
register.
The following is the table of Ultra DMA data burst timing requirement.
Ultra DMA data burst timing requirements
Name

Mode1(ns)

Mode2(ns)

Mode3(ns)

Mode4(ns)

Min
t2cyctyp

Mode0(ns)

Min

Min

Min

Min

Max

240

Max

160

Max

120

Max

90

Comment

Max

60

Type sustained average two cycle

time

tcyc

112

73

54

39

25

Cycle time allowing for

asymmetry and clock variations

t2cyc

230

154

115

86

57

Two cycle time for clock variations

tDS

15

10

Data Setup times at recipient

tDH

Data hold time at recipient

tDVS

70

48

30

20

Data valid setup time at sender

tDVH

Data valid hold time at sender

tFS

230

200

170

130

120

First strobe time

tLI

150

150

150

100

100

Limited interlock time

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ATJ209X PROGRAM GUIDE

tMLI

20

20

20

20

20

Interlock time with minimum

tUI

Unlimited interlock time

tAZ

10

10

10

10

10

Maximum time allowed for output

drivers to release

tZAH

20

20

20

20

20

Minimum delay time required for

output

tZAD

tENV

20

0
70

20

0
70

20

0
70

20

0
55

20

Drivers to assert or negate

55

Envelope time

tSR

50

30

20

NA

NA

Strobe -to- DMARDY time

tRFS

75

70

60

60

60

Ready -to- final- Strobe time

tRP

160

125

100

100

100

Minimum time to Assert STOP or

negate DMARQ

tIORDYZ

20

20

20

20

20

Maximum time before releasing

IORDY

tZIORDY

Minimum time before releasing

IORDY

tACK

20

20

20

20

20

Setup and hold times for DMACK-

tSS

50

50

50

50

50

Time form STROBE edge to

negate of DMARQ or assert of
STOP

NOTES:
1.

Timing parameters shall be measured at the connector of the sender or receiver to which the
parameter applies. For example, the sender shall stop generating STROBE edges tRFS after the
negation of DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the
connector of the sender.

2.

All timing measurement switching points (low to high and high to low) shall be taken at 1.5V.

3.

tUI , tMLI , and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or
recipient is waiting for the other to respond with a signal before proceeding. tUI is an unlimited
interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is
a limited time-out that has a defined maximum.

4.

The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers. Timing for
tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same
capacitive load value.

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ATJ209X PROGRAM GUIDE

4.AD RegisterAD-- Serial LCM Control Register (Back)
Bits

Description

Access

Serail LCM Enable. 0:disable,1:enable.

When using serial LCM, we should enable Serial LCM first then enable
SPI.In this condition the SPI output SPI_CLK,SPI_MOSI only.

Reset

RW

6:5

VS[1:0] status.

4:1

Reserved.

Reserved.

RW

Access

Reset

RW

Access

Reset

7:6

SDRAM TYPE
00 64MBit (refresh: 4096cycles/64ms)
01 128MBit (refresh: 4096cycles/64ms)
10 256Mbit (refresh: 8192cycles/64ms)
11 512MBit (refresh: 8192cycles/64ms)

RW

00

SDRAM BUS MODE.0: 8-bit, 1: 16-bit.

RW

CAS# latency. 0: CAS# latency=2, 1: CAS# latency=3

RW

3:2

SDRAM Burst Length .

00
1
01
2
10
4
11
8

RW

11

1:0

DRAMADDR[25..24]

RW

00

Access

Reset

4.AE

RegisterAE--DMA3

Byte Counter Hi Register (Back)

Bits
7:0

4.B0

Description
DMA3BC[15..8]

RegisterB0--SDRAM TYPE REGISTER (Back)

Bits

4.B1
Bits

Description

RegisterB1--SDRAM COMMAND REGISTER (Back)

Description

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ATJ209X PROGRAM GUIDE

7:0

4.B2

SDRAM COMMAND(see figure 16 for timing detail )

Command ID
CMD action
A0h
power up
54h
burst read
44h
burst write
14h
auto refresh
10h
self refresh
18h
exit self refresh
80h
command inhibit
others
reserved

4.B3

4.B4

4.B5

Access

Reset
000xxxxx

Access

Reset

RW

Access

Reset

RW

000

RegisterB3--SDRAM ADDRESS 1 (Back)

Description
DRAMADDR[15..8]

RegisterB4--SDRAM ADDRESS 0 (Back)

Description
DRAMADDR[7..0]

RegisterB5--SDRAM Control Register (Back)

Bits

7:5

Reset

RW

DRAMADDR[23..16]

Bits
7:0

Access
RW

Description

Bits
7:0

80h

RegisterB2--SDRAM ADDRESS 2 (Back)

Bits
7:0

RW

Description
IPM/IDM
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

IPML
IPMM
IPMH
HDD
IDML
IDMM
IDMH
zram2

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ATJ209X PROGRAM GUIDE

4:3

Autorefresh Frequency Select

0 0 4k/64ms(cond: MCUCLK=24MHz)
0 1 8K/64ms(cond: MCUCLK=24MHz)
1 0 16K/64ms(cond: MCUCLK=24MHz)
1 1 2K/64ms(cond: MCUCLK=24MHz)

RW

00

SDRAM clock enable. 0: disable, 1: enable

RW

SDRAM MODE enable. 0: disable, 1: enable

RW

Reserved

RW

Access

Reset

RW

4.B6

RegisterB6--DMA3 SRAM Address Low (Back)

Bits
7:0

4.B7

Description
DMA3SramADDR[7..0]

RegisterB7--DMA3 SRAM Address Hi (Back)

Bits

Description

Access

Reset

7:6

Clock select .
0 0: MCUCLK/1(default)
0 1: MCUCLK/2
1 0: MCUCLK/3
1 1: MCUCLK/4
if MCUCLK/3 or MCUCLK/4 is selected, a reserved value should be
written to regB1h before a COMMAND is sent out.

RW

5:0

DMA3SramADDR[13..8]

RW

Access

Reset

RW

Access

Reset

R/W

4.B8

RegisterB8--DMA3 Counter Low Byte (Back)

Bits
7:0

4.B9

Description
DMA3BC[7..0]

RegisterB9--DMA3 Mode (Back)

Bits
7

Description
DMA3 for DSP transfer mode,
0:linear mode, 1: DSP mode.

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ATJ209X PROGRAM GUIDE

DMA3 SRAM down count,
0:up count, 1: down count

R/W

DMA3 memory access select.

R/W

00

Sensor & SDRAM Bridge Enable.0:disable,1:enable.

R/W

Reserved.

R/W

00

Back door select.

0 0 : normal, other :test mode back door

R/W

00

6
5:4

1:0

4.BA RegisterBA--DMA3 Command Register (Back)

Bits

Description

Access

Reset

DMA3 TC IRQ enable.0 disable IRQ. 1 enables IRQ when DMA3 finishes
whole block transfer

RW

DMA3 Half Transfer IRQ enable. 0 disable IRQ. 1 enables IRQ when
DMA3 finishes half of defined block transfer.

RW

DMA3 Continue Block Transfer enable. 0 disables the continuous block

transfer mode and Bit 1 of this register will be cleared when the last byte
of the block is transferred. 1 enables the continuous block transfer mode
and SRC Address Counter/DST Address Counter/Byte Length Counter
will be reloaded with their corresponding registers when DMA3 finishes
the block transfer. Writing 0 to this bit will stop DMA3.

RW

Reserved.

SDRAM initialization complete flag, writing 1 to this bit will clear it, while 0
unchanged.

RW

DMA3 Half Transfer IRQ pending, write 1 to this bit will clear it, while 0
unchanged.

RW

DMA3 End Transfer IRQ pending writing 1 to this bit will clear it, while 0
unchanged.

RW

DMA3 busy status. After the TC, the bit will be cleared.

RW

DMA3 Memo:
1.

When CMD Burst Read is issued, the data stream is moving from SDRAM to the SRAM selected;
while in Burst Write, it is from SRAM to SDRAM .

2.

When the Byte Counter is not the multiples of the burst length in burst reading, data should not be
moved from SDRAM to SRAM until DMA3 finishes the whole block transfer; while in burst writing,
DQM should be pulled high for the following cycles if DMA3 finishes.

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ATJ209X PROGRAM GUIDE

3.

if DMA3BC=n, it means n+1 bytes should be moved.

Parameter

Symbol

Min

Units

RAS# to CAS# Delay

Trcd

CLK

RAS# Active to Precharge CMD Time

MRS to new command

Tras
Tmrd

2
2

CLK
CLK

Self Refresh Exit Time

Auto Refresh Period
Exit Self Refresh to Active

Tsre
Trfc
Txsr

1
2
3

CLK
CLK
CLK

Auto Refresh to RAS# time

Tar

CLK

Precharge to RAS# time

Tpr

CLK

SDRAM Timing
Power up:
ecneuqeS pU rewoP
91

81

71

61

51

41

31

21

11

01

KLC

yrassecen si level hgiH

EKC
SC/

CRt

PRt

CRt

SAR/
SAC/

aAR

yeK

RDDA
0AB
1AB

aA R

PA/01A
Z-hgiH

QD
EW/

yrassecen si level hgiH

teS
retsigeR edoM
)knaB-A(
evitcA woR

hserfeR
otuA

hserfeR otuA

MQD

)sknaB llA(
egrahcerP

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ATJ209X PROGRAM GUIDE

Burst read:

Burst Read
T0

T1

T2

T3

T4

CLK
CKE

High

CS

t RCD
RAS

CAS

WE

BS

A10

Ra

ADDR

Ra

BS

Ca

DQ

DQM

BA0/1

Q n-1

Qn

low

t RCD

Row Active

Read

Precharge(All Banks)

Note:
n=BL,CL=2 for this example

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ATJ209X PROGRAM GUIDE

Burst write:

Burst Write
T0

T1

T2

T3

Tn+1

Tn+2

Tn+3

CLK
CKE

High

CS

RAS

CAS

WE

BA0/1

BS

A10

Ra

ADDR

Ra

DQ

Ca

DQM

BS

Q2

Qn

low

t RDL

Row Active

Write

Precharge

Note:
n=BL, t RDL=2 CLK

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Ver 1.4

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Copyright 2005 Actions Semiconductor Co., Ltd. All rights reserved.

h s e rf e r t s r ub s e s u m e ts y s e ht f i ti x e h se r f er f le s r e tf a dn a y r tn e hs e r fe r f l es
e ro f eb de r iu q e r s i hs e r fe r o t u a t sr u b f o ) bM 6 5 2( e l cy c K 8 r o) b M 82 1 , bM 4 6 ( e l cy c k 4 .7
. ti x e h se r f er f le s e t el p m oc o t hg i h g ni o g E K C r et f a d e r iu q e r si C Rt n u m in i M .6
. h g ih m o r f st r a ts S C / .5
. h g ih E K C g ni n r ut e r e r o fe b e l ba t s e b d n a tr a t se r kc o l c me t s yS . 4

EDOM HSERFER FLES TIXE OT

. h s er f e r fl e s m or f ti x e e ro f e b d e ri u q er s i S A Rt m um i n im , e do m h s er f e r fl e s s r e tn e e c iv e d e h t e cn O ). f C
. W O L s y a t s E K C s a g n o l s a e d o m h s e r f e r f l e s n i s n i a m e r e c i v e d e h T . 3
E K C r o f t p e c x e e r a c t n o d e b n a c k c o l c m e t s y s e h t g n i d u l c n i s t u p n i e h t l l a , e l c y c k c o l c 1 r e t f A . 2
. el c y c kc o l c e m as e h t t a w o l e b d lu o h s E K C ht i w S A C / & S A R/ , S C/ . 1

EDOM HSERFER FLES RETNE OT :etoN*

e r a c t n o D :
h se r f eR
o t uA

t i xE
hs e r fe R fl e S

yr t n E
hs e r fe R fl e S

M QD
EW/
Z-iH

QD

Z - iH

PA/01 A
1AB- 0AB
RDD A
SAC /
7 e to N *

SAR /
5 e to N *

SC/
SSt
3 et o N *

6 e t oN *
n i m CR t
91

81

71

61

51

41

31

4 e to N *
21

11

01

1 et o N *

EKC

2 e t oN *
7

KLC

tixE & re tnE hse rfeR fleS

Self Refresh Enter & Exit

ATJ209X PROGRAM GUIDE

ATJ209X PROGRAM GUIDE

UART2, Sharp IR and SIR Baud Rate Register
Prescale
Value
Baud
Rate

13
Divisor

1.625
%Error

Divisor

%Error

Divisor

%Error

600

192

0.16%

1200

96

0.16%

1800

64

0.16%

2000

58

0.53%

2400

48

0.16%

3600

32

0.16%

256

0.16%

4800

24

0.16%

192

0.16%

7200

16

0.16%

128

0.16%

208

0.16%

9600

12

0.16%

96

0.16%

156

0.16%

14400

0.16%

64

0.16%

104

0.16%

19200

0.16%

48

0.16%

78

0.16%

28800

0.16%

32

0.16%

52

0.16%

38400

0.16%

24

0.16%

39

0.16%

57600

0.16%

16

0.16%

26

0.16%

115200

0.16%

0.16%

13

0.16%

230400

0.16%

460800

0.16%

750000

921600

0.16%
-

2
1

0.00%
0.00%

1500000

4.BC RegisterBC-- DMA66 Control /Status Register (Back)

Bits

Description
7

Access

DMA66 Busying 1:DMA66 busying. 0: DMA66 idle. When DMA66 starts,

this bit will be set to 1 automatically, and when DMA66 Stops, this bit will
be cleared to 0 automatically.
Device Pausing bit. 1: Device Pausing DMA66 0:normal termination or
DMA66 restart again.

Host Pausing bit.

1: host Pausing DMA66. 0:Normal or Restart DMA66
Reserved

RW

4:1

Reset

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ATJ209X PROGRAM GUIDE

0

DMA66 enable. 1: DMA66 enable. 0: default (PIO mode)

RW

Access

Reset

ATA enable. 0:disable,1:enable.

RW

6:4

Mode Select Number

Different mode has different speed.

RW

000

3:2

Reserved.

4.BD RegisterBD--ATA Config Register (Back)

Bits
7

Description

ATA IRQ enable. 0:disable 1:enable

RW

ATA IRQ status 0:NO IRQ, 1: interrupt status. writing 1 to this bit will clear
interrupt status.

RW

Access

Reset

External resistor select

0: select external resistor to adjust charge current;
1: use internal resistor to adjust charge current.
Typical resistor value is 1KOhm for 200Ma charge current.

RW

Enable charge circuit

1: Enable charge circuit
0: Disable charge circuit. Charge circuit will not work, and consume little
power.

RW

Reserved.

Charging Status. 0: not charging, 1: charging.

Reserved.

RW

101

4.BE

RegisterBE--Battery charger Control Register (Back)

Bits

2:0

Description

Charge current configure, while using internal resistor.

000: 10mA (Resistance=20 KOhm)
001: 20mA (Resistance=10 KOhm)
010: 50mA (Resistance=4.0 KOhm)
011: 100mA (Resistance=2.0 KOhm)
100: 150mA (Resistance=1.33KOhm)
*** 101: 200mA (Resistance=1.0 KOhm)
110: 250mA (Resistance=0.8 KOhm)
111: 300mA (Resistance=0.5 KOhm)
It is same for external resistor selection.

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ATJ209X PROGRAM GUIDE

4.BF RegisterBF --Battery charger Status Register (Back)
Bits

Description

Access

Reset

External 5V supply presence

1: External 5V supply is present ;
0: External 5V supply is not present.

Battery presence.
1: Battery is present, 0: Battery is not present.

RW

xx

RW

5:3

Reserved.

2:1

Status of PWRMODE[1..0]

4.C0

LB- Detect Enable. 0:disble,1:enable.

RegisterC0--Key Scan Data Register (Back)

Bits

Description

Access

Reset

7:0

Key Scan data, there are 12 8-bit registers for key latch per scan. The 12
registers are mapped into this register, and an internal pointer is used to
point to the current register to return data when this register is read. Any
IO write to this register will clear the internal register, and the pointer will
increase by 1 to point to the next register after a IO read to the register is
performed.

RW

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KeyIn0
KeyIn1
KeyIn2
KeyIn3
KeyIn4
KeyIn5
KeyIn6
KeyIn7
KeyIn8
KeyIn9
KeyIn10
KeyIn11

ATJ209X PROGRAM GUIDE

KeyOut0
KeyOut1
KeyOut2
KeyOut3
KeyOut4
KeyOut5
KeyOut6
KeyOut7

1st Reg
2nd Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
2nd Reg
3rd Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
4th Reg
5th Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
5th Reg
6th Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
7th Reg
8th Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
8th Reg
9th Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
10th Reg
11th Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
11th Reg
12th Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

Example:
Reg$C0 Readback is $FF,$AF,$F7,$FF,$FF,$FE,$FF,$FF,$FF,$FF,$FF,$FE,
indicate following 5 keys have pressed : [KeyOut ,KeyIn]
[1,0], [1,2], [1,7], [3,4], [7,4]

4.C1

RegisterC1--Key Scan Control Register (Back)

Note : no more than one key can be pressed on the same key in line at the same time
Bits

Description

Access

Reset

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6:5

4
3:0

Key Scan Circuit Enable, 0:disable 1:enable.when Key Scan Enable

KEYI[3:0], KEYO[3:0] are decided by PAD configuration.

RW

Key Scan De-bouncing time select

Bit 1 0 De-bouncing time (=Scan Period)
0 0 40ms
0 1 80ms
1 0 160ms
1 1 320ms

RW

00

KEYI[4..11] MASK when in Key Scan mode, 0mask,1: enable.

RW

KEYI[3:0]MASK when in Key Scan mode, 0 to mask key input, 1 to enable

key input. When any pin of Keyin[3..0] is masked, it can be used as GPIO,
even if key scan mode is active.

RW

0000

KEY Scan Timing

2 elcyC

1 elcyC
0tuOyeK
1tuOyeK
7tuOyeK
8/emiT gnicnuob-eD=T
T8
T
gnimiT nacS yeK

4.C2

RegisterC2--LCD Data0 Register (Back)

Bits

Description

Access

Reset

7:4

COM[3:0] of SEG0

RW

xxxx

3:0

COM[3:0] of SEG1

RW

xxxx

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4.C3

RegisterC3--LCD Data1 Register (Back)

Bits

Description

Access

Reset

7:4

COM[3:0] of SEG2

RW

xxxx

3:0

COM[3:0] of SEG3

RW

xxxx

Access

Reset

4.C4

RegisterC4--LCD Data2 Register (Back)

Bits

Description

7:4

COM[3:0] of SEG4

RW

xxxx

3:0

COM[3:0] of SEG5

RW

xxxx

Access

Reset

4.C5

RegisterC5--LCD Data3 Register (Back)

Bits

Description

7:4

COM[3:0] of SEG6

RW

xxxx

3:0

COM[3:0] of SEG7

RW

xxxx

Access

Reset

4.C6

RegisterC6--LCD Data4 Register (Back)

Bits

Description

7:4

COM[3:0] of SEG8

RW

xxxx

3:0

COM[3:0] of SEG9

RW

xxxx

Access

Reset

4.C7

RegisterC7--LCD Data5 Register (Back)

Bits

Description

7:4

COM[3:0] of SEG10

RW

xxxx

3:0

COM[3:0] of SEG11

RW

xxxx

Access

Reset

4.C8

RegisterC8--LCD Data6 Register (Back)

Bits

Description

7:4

COM[3:0] of SEG12

RW

xxxx

3:0

COM[3:0] of SEG13

RW

xxxx

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4.C9

RegisterC9--LCD Data7 Register (Back)

Bits

Description

Access

Reset

7:4

COM[3:0] of SEG14

RW

xxxx

3:0

COM[3:0] of SEG15

RW

xxxx

Access

Reset

4.CA RegisterCA--LCD Data8 Register (Back)

Bits

Description

7:4

COM[3:0] of SEG16

RW

xxxx

3:0

COM[3:0] of SEG17

RW

xxxx

4.CB RegisterCB--LCD Data9 Register (Back)

Bits

Description

Access

Reset

7:4

COM[3:0] of SEG18

RW

xxxx

3:0

COM[3:0] of SEG19

RW

xxxx

4.CC RegisterCC --Flash ECC Register0 (Back)

Bits

Description

Access

Reset

ECC 6

ECC6

ECC 5

ECC5

ECC 4

ECC4

ECC 3

ECC3

Access

Reset

4.CD RegisterCD --Flash ECC Register1(Back)

Bits

Description

ECC 10

ECC10

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5

ECC 9

ECC9

ECC 8

ECC8

ECC 7

ECC7

Access

Reset

4.CE

RegisterCE --Flash ECC Register2 (Back)

Bits

Description

ECC 2

ECC2

ECC 1

ECC1

ECC 0

ECC0

ECC 11

ECC11

4.CF RegisterCF --Flash ECC Register3 (Back)

Bits

Description

Access

Reset

Flash ECC Error flag, 1 ECC1 or ECC2 Error ever occur. Writing 1 to this
bit will clear the bit.

RW

User ECC Error flag, 1 ECC3 Error ever occur. Writing 1 to this bit will
clear the bit.

RW

Nand Flash Test Enable. 0:disable,1:enable.

RW

Nand Flash State Machine Reset.0: reset,1:normal.

RW

ECC 13

ECC13

ECC 12

ECC12

Note: ECC bits mapping table

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P1
P2
P4

ECC 0=
ECC 1=
ECC 2=

ECC12=

P8192

ECC0= P1
ECC1= P2
ECC2= P4

ECC13= P8192

4.D0 RegisterD0--BAT ADC and LRADC1/LRADC2 Control and Status Register (Back)
Bits

Description

Access

Reset

DC to DC use internal NMOS power switch; 0: not use; 1: use .

RW

BATTERY ADC Enable. 0:disable,1:enable.

RW

LRADC1 Enable. 0:disable,1:enable.

RW

LRADC2 Enable. 0:disable,1:enable.

RW

LRADC1 IRQ Enable. 0:disable,1:enable.

RW

LRADC2 IRQ Enable. 0:disable,1:enable.

RW

LRADC1 IRQ Pending bit. 0:unoccured,1:occured.

Writing 1 to this bit will clear it.

RW

LRADC2 IRQ Pending bit. 0:unoccured,1:occured.

Writing 1 to this bit will clear it.

4.D1

RegisterD1--BATTERY ADC Control & Touch Panel Sense Period Select

Register (Back)
Bits

Description

Access

Reset

TP ADC ENABLE. 0:disable,1:enable.

RW

Reserved to 0.

RW

TP Fs select.
0 0 8k
0 1 4k
1 0 2k
1 1 1k

RW

00

5:4

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3:2

BATTERY ADC/LRADC1 Bias Current Select

00
6uA
**01
8uA
10
10uA
11
12uA

RW

01

1:0

Touch Panel sense period select

**00
1*Ts=1/TP_FS
01
2*Ts
10
3*Ts
11
4*Ts

RW

4.D2
Bits

RegisterD2--Touch Panel Enable & Scan Period Select Register (Back)

Access

Reset

Touch panel enable, 0 disable, 1 enable

RW

touch panel toggle time select bits

00
1
01
2
10
3
11
4

RW

01

Touch panel function idle bit, if write this bit, touch panel go into idle mode
for power saving, any touch again will active it; Read this bit, always is
zero

RW

3:0

Touch panel scan period select bits, if SCAN [3:0]=n, then the scan period
is 16*n*Ts (if n=0,then period=8*Ts) and here 16*n*Ts must be greater
than TPSP[1:0]*TOGS[1:0]*2.

RW

0010

Access

Reset

RW

00

6:5

4.D3
Bits

7:6

Description

RegisterD3--Audio ADC Performance Tuning Register (Back)

Description
OPA in Audio ADC & OPF in DAC bias current select:
**00 6uA
01 8uA
10 10uA
11 12uA

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5:4

Audio ADC dither level select:

**00 46.0mV
01 91.0mV
10 136mV
11 182mV

RW

00

3:2

The bias current select for OPDA1/OPDA2 in ADC

**00 4uA
01 7uA
10 10uA
11 13uA

RW

00

1:0

Audio ADC input gain control

00 -6dB
01 -3dB
10 00dB
**11 +3dB

RW

11

Access

Reset

4.D4

RegisterD4--Audio ADC First Control Register (Back)

Bits

Description

The audio ADC enable, 0 disable, 1 enable

RW

MIC input stage power control, 0 disable, 1 enable

RW

Line in input stage power control, 0 disable, 1 enable

RW

FM input stage power control, 0 disable, 1 enable

RW

Audio ADC dither on or off, 0 to off, 1 to on

2:0

4.D5
Bits

MIC amplifier gain control bits.

000
X22
001
X27
010
X32
011
X37
100
X42
101
X47
110
X52
111
X57

101

RegisterD5--Audio ADC Second Control Register (Back)

Description

Access

Reset

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Audio ADC FS select
000
8K
001
12K
010
16K
011
24K
100
32K
101
48K
11X
reserved

RW

000

MIC input to analog mixer mute, 0 mute, 1 not mute

RW

Line-in input to analog mixer mute, 0 mute, 1 not mute

RW

FM input to analog mixer mute, 0 mute, 1 not mute

RW

Audio ADC Analog Input Select

00: Select MIC, R and L is same
01: Select FMIN
10: Select Line-in
11: Select Internal Analog Mixer Output (AOUT)

RW

Access

Reset

RW

101

7:5

1:0

4.D6

RegisterD6--Analog Input Gain Control Register (Back)

AINGAINC (Analog Input Gain Control Register, D6h)

Bits
7

6:4

Description
Reserved.
Line-in input stage gain control
000
-7.5db
001
-6.0db
010
-4.5db
011
-3.0db
100
-1.5db
101
0.0db
110
1.5db
111
3.0db
Reserved.

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2:0

4.D7

FMIN input stage gain control

000
-7.5db
001
-6.0db
010
-4.5db
011
-3.0db
100
-1.5db
101
0.0db
110
1.5db
111
3.0db

RW

101

Access

Reset

RegisterD7--Audio ADC FIFO Control Register (Back)

Bits

Description

AUDIO ADC Data Ready IRQ enable. 0:disable 1: enable

RW

AUDIO ADC FIFO adjusting bit. Writing 1 to this bit to synchronize FIFO
internal state and clear DRQ also.

RW

AUDIO ADC FIFO EMPTY flag, Read Only, 0: empty, 1: not empty

RW

AUDIO ADC channel mode select.

0: R+L channel, 1: Only left channel

RW

AUDIO ADC IRQ pending bit.

writing 1 to this bit to clear it, otherwise unchanged

RW

AUDIO ADC FIFO counter reset control .

0: reset ADCFIFO, 1: not reset

RW

FIFO data doorsill setting of ADC FIFO generating IRQ or DRQ

(ADCFIFOS[1:0]): ADCFIFOS[1:0]
Startup doorsill:
00
8 of12
01
4 of12
10
1 of12
11
reserved

RW

00

Access

Reset

XXh

1:0

4.D8

RegisterD8--LRADC1 Data Register (Back)

Bits
7:0

Description
LRADC1 Data[7:0]

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4.D9

RegisterD9--Touch Panel X Position Data Low Byte Register (Back)

Bits

Description

Access

Reset

7:5

X data bit 2-0 Read only

000

4:2

Reserved

101

1:0

Defined to select Audio ADC LPF bias current

00 10uA
**01 20uA
10 30uA
11 40uA

01

4.DA RegisterDA--Touch Panel X Position Data High Byte Register (Back)

Bits
7:0

4.DB

Description

Description

7:5
4:0

0
10101

RegisterDC--Touch Panel Y Position Data High Byte Register (Back)

Bits

4.DE

Reset

RW

Reserved.

Access
R

Y data bit 2-0 read only

7:0

RegisterDB--Touch Panel Y Position Data Low Byte Register (Back)

Bits

4.DC

Reset

X data bit 10-3 read only

Access

Description

Reset

Y data bit 10-3 read only

Access

RegisterDE--Touch Panel ADC IRQ Control and Status Register (Back)

Bits

Description

Access

Reset

Panel 1st touched IRQ enable.

RW

Touch Panel X or Y Data Ready IRQ enable

RW

Reserved.

verify mode-- 0 Audio ADC normal output; 1 Audio ADC output 010101

RW

RW

st

Panel 1 touched IRQ pending bit.

writing 1 to this bit to clear it, otherwise unchanged

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2

Touch Panel X Data Ready IRQ pending bit.

Writing 1 to this bit to clear it, otherwise unchanged

RW

Touch Panel Y Data Ready IRQ pending bit.

writing 1 to this bit to clear it, otherwise unchanged

RW

Reserved

Access

Reset

RW

00

RW

10

RW

10

4.DF RegisterDF--Power Control Register (Back)

Bits

Description
Set LBD voltage level
**00=VL0
01=VL1
10=VL2
11=VL3
The following is the table of VL0~3 in different battery mode:

7:6

PWRMODE[1..0]
00/01

10

11

VL0

0.75V

1.5V/2

3.3V/2

VL1

0.85V

1.7V/2

3.4V/2

VL2

0.95V

1.9V/2

3.5V/2

VL3

1.05V

2.1V/2

3.6V/2

Set LBNMI voltage level

**00=VL1
01=VL2
10=VL3
11=VL4
PWRMODE[1..0]

5:4

00/01

11

VL1

0.85V

1.7V/2

3.4V/2

VL2

0.95V

1.9V/2

3.5V/2

VL3

1.05V

2.1V/2

3.6V/2

VL4

3:2

10

1.15V

2.3V/2

3.7V/2

Internal IBIAS resistance select, it can affect RCOSC frequency and

compare the implements power consumption:
00=540Kohm
01=520Kohm
**10=500Kohm
11=480Kohm

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1

VCCOUT control; 0: output pad disable, 1: enable

Drive capability: 35mA @VBAT=1.0V

RW

DC-DC CLOCK Select.

0:133KHz, 50% duty; 1:200KHz 75%(default).

RW

Access

Reset

4.E0

RegisterE0--SD Control Register1 (Back)

SDCTL1(SD control register1, 0E0h)

Bits

Description

SD module enable bit

Just a Local reset! 0:disable, 1:enable

RW

bus width select bit

0:1 bit, 1:4 bit

RW

Pull high resister control bit

There are five pull high resistors (75kohm) on the CMD and DAT lines.
This bit control whether these resistors will be used.0: unused, 1:used

RW

Card detect enable bit

0:disable, 1:enable

RW

3:2

Reserve to 0

RW

00

1:0

MMC CLOCK Select.

00 MCUCLK/2
01 MCUCLK
10 MCUCLK/3
11 MCUCLK/4

RW

00

Access

Reset

4.E1

RegisterE1--SD control register2 (Back)

Bits

Description

CMD indicate bit

0:CMD end, 1: output for CMD

RW

RSP indicate bit

0:RSP end, 1: input for CMD

RW

DAT in/out control bit

0: data in, 1: data out

RW

Reserved.

RW

1: Enable Clock out when read from data line

0: SD status machine reset

RW

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2

1:0

4.E2

CRC16 calculation result output enable bit

When the bit is 1, it cant do CRC checked to data lines.

RW

CRC16 registers map bit

This bit indicates which one is map into the external CRC16
register of four internal registers.
00: CRC16 register for DAT0
01: CRC16 register for DAT1
10: CRC16 register for DAT2
11: CRC16 register for DAT3

RW

00

Access

Reset

RW

Access

Reset

Data block CRC7 calculation result bit6-0

xxxxxxx

Reserved to 1

RegisterE2--CMD/RSP Register (Back)

Bits
7:0

4.E3

Description
Any data written to this register, 8 clocks should be generate to shift out
this byte.
Any data received from response line will be stored into this register.

RegisterE3--CRC7 Calculation Result Register (Back)

Bits
7:1
0

4.E4

Description

RegisterE4--Data In/Out Register (R/W) (E4h) (Back)

Bits

Description

Access

Reset

7:0

Any data written to this register, 8 clocks should be generate to shift out
this byte.
Any data received from data line will be stored into this register.

RW

Access

Reset

Access

Reset

4.E5
Bits
7:0

4.E6

Registere5--CRC16 Calculation Result Register High (Back)

Description
Data block CRC16 calculation result bit15-8.

Registere6--CRC16 Calculation Result Register Low (Back)

Bits

Description

7:0

Data block CRC16 calculation result bit7-0.

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4.E7

RegisterE7--SD Status Register (Back)

Bits

Description

Access

Reset

Card insert indication bit.

0: no card, 1: insert

RSP DRQ bit

1 indicates the command response has occurred, writing 1 to this bit will
clear it.

RW

DATin DRQ bit

1 indicates the read data block has occurred, writing 1 to this bit will clear
it.

RW

Reserved.

Clock generate complete indication bit

1 indicates 8 cycles Clock complete, writing 1 to this bit will clear it.

RW

Reserved.

1:0

Reserved.

Access

Reset

4.E8
Bits

RegisterE8--RS E(x) FIFO Register (Back)

Description
FIFO Level: 16 levels.
It is valid when E(x) FIFO read flag is 1. After read regE8H for 16 times
successively, we can get 4 symbols of E(x). Reading sequence: read the
first symbolsXi, then Yi; then the symbolsXi and Yi.

7:0

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Data and Address Relationship

4.E9

RegisterE9-- RS ECC Register (Parity Symbols FIFO) (Back)

Bits

7:0

Description
FIFO Level: 9 levels.
It is valid when Parity Symbols FIFO ready flag is 1, Read regE9H 9
times successively, we will get Parity Symbols FIFOs RS_ECC[71:0].
Read sequence is RS_ECC[7:0] first ,then RS_ECC[15:8]

Access

Reset

Access

Reset

4.EA RegisterEA--ECC4 TEST (ECC4 TEST Register, 0EAh) (Back)

Bits

Description

7:1

Reserved.

Reserved

RW

RS(511,503) encode, decode interface description

Encoder:
The interface signals of RS encoder are shown below:

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Signal Name
Y[8:0]
X[8:0]
Enable
Data

I/O
out
in
in
in

Clk
Clrn

in
in

Description
9bit parallel encode words Bytes(511Bytes).
9bit parallel data Bytes for encoding(503Bytes).
global encoder clock enable.
signal that the encoder should be output the data symbols or parity
symbols.
global clock.
signal that the encoder should be clear initial.

Decoder:
The decoder interface is as follows

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Signal name
x
error_flag
Enable
Can_not

I/O
in
out
in
out

Clk
Clrn
Error_value

in
in
out

Error_address

out

Valid

out

Description
9bit parallel encoded code word for decoding.
1 indicates that error has been corrected.
global decode clock enable.
1 indicates that more than 4 errors has been
detected and can not corrected.
global clock.
signal that the decoder should be clear initial.
9bit parallel corrected data Bytes. Each corrected words output from
the decoder.
9bit parallel corrected address Bytes. Each corrected words output
from the decoder.
if high during active clock edge, indicates that output Error data is valid
and should be latched on next clock edge.

4.EB RegisterEB --R-S ECC Status/Control Register (Back)

Bits

Description

Access

Reset

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Read-Solomon ECC Error. 0 means less or equal to 3 symbols Error

detected and can be corrected, 1 means more than 3 symbols Error
detected. Writing 1 to this bit will clear it.

WR

Flag Over Error flag. 0 means that error number does not confirm. The bit
will be set to 1 when more than 4 symbols RS_ECC errors are detected
and does not correct in the current codeword, Writing 1 to this bit will clear
it.

WR

Reserved.

WithError Flag. This bit will set to 1 when RS_ECC any errors are
detected in the current codeword, writing 1 to this bit will clear it.

WR

FIFO Ready flag. This bit will set to 1 when the RS encode or decode
engine works on 9-bit symbols has completed. Hardware will
automatically reset to 0 when the next sector DMA start.

FIFO Pointer Reset bit. 0 Reset invalid, 1 Reset valid. Writing 1 to this bit
will reset the Parity Symbols FIFO and E(x) FIFO pointer.

WR

Parity Symbols FIFO Access Mode. 0: 9Bytes Read-Solomon parity field

is to be written into the 16Bytes spare area by DMA, 1: 9Bytes
Read-Solomon parity field is to be written into the 16Bytes spare area by
MCU.

WR

4 Symbols R-S Code ECC Enable bit. 0: disable, 1: enable.

WR

Notes:
1. Symbols size supported is only for 9 parity.
2. RS(n, k) n=511, k=503
3. 9-bit symbols can be read after the E(x) FIFO Ready flag bit set to 1, the 4 9-bit symbols(E(x))
which include Error locations(Xi) and Error magnitudes(Yi) will be read to RAM by serial read
signal (16 clock).

4. RS ECC can be Read after the Parity Symbol FIFO Ready flag bit set to 1, the RS ECC will be
read to RAM by serial read signal (9 clock).

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5. Write 1 to FIFO Pointer reset bit will reset the Parity Symbols FIFO and E(x) FIFO pointer.
6. When RegEB_7 is 0, then RegEB_6 is also 0; when RegEB_7 is 1 then we should care

RegEB_6. If RegEB_6 is 1, it means 4symbols or more than 4symbols Error, and then it cannot
be decoded. If RegEB_6 is 0, it means RS ECC cannot judge whether right or not.

Encoder:
If a 512-byte data block located on RAM need writing to flash device, then it can be assumed that a
9-bytes Read-Solomon parity need writing into 16 Bytes spare area.

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ENCODE
ECC4_BLKSTRTADDR_ADDR
ECC4_BLKSTRTINDEX_INDEX

512 Byte Data Area

81

16 Byte
Spare Area

431

add one zero

every byte

72

8 Parity
Symbols

431
503 Symbol Polynomial Dividend
511 Symbol Reed-Solomon Block Code

Galois Field
Polynomial Divider

8 Parity
Symbol
Remainder

ECC4_PARSTRTADDR_ADDR
ECC4_PARSTRINDEX_INDEX

512 Byte Data Area

DATA

16 Byte
Spare Area
9 Byte
Parity

Flash ECC Read-Solomon Block coding: encoding.

Flash ECC Read-Solomon Block coding : encoding.

Decoder:
When a page is read from flash device, if hardware automatically correct has set, it must be checked, and
if errors are found RS must to be corrected.

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DECODE
ECC4_BLKSTRTADDR_ADDR
ECC4_BLKSTRTINDEX_INDEX

ECC4_PARSTRTADDR_ADDR
ECC4_PARSTRINDEX_INDEX

16 Byte
Spare Area

512 Byte Data Area

81

9 Byte
Parity

431
add one zero
every byte

72

8 Parity
Symbols

431
503 Symbol Polynomial Dividend
511 Symbol Reed-Solomon Block Code

8 SYNDROMES
8 Parity
Symbol
Remainder

Galois Field
Polynomial Divider

OK

== 0?

ERROR!
Flash ECC Read-Solomon Block coding: decoding.

Flash ECC Read-Solomon Block coding : decoding.

1. Large block: after DMA transmits one sector, sending writing spare command(0xfc) will write RS_ECC
to spare area, then transmit the next sector and the corresponding RS_ECC. When DMA reading, ECC
hardware will checkout automatically, and if there is error, it will sent an error flag.

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Large block flash
512 B
Main area

512 B
Main area

512 B
Main area

512 B
Main area

16 B
Spare
area

16 B
Spare
area

16 B
Spare
area

16 B
Spare
area

2. Small block: At the time of transmitting over 512 bytes data, RS_ECC will be written to the spare area.
When DMA reading, ECC hardware will checkout automatically, and if there is an error, it will sent an error
flag.
Small block flash
512 B
Main area

16 B
Spare
area

3. One sector DMA: RS_ECC is generated for one sector data

Read-Solomon Code ECC for 16Bytes Spare area assignment:

RS ECC Code for Main area data

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

RS_ECC_0 RS_71

RS_70

RS_69

RS_68

RS_67

RS_66

RS_65

RS_64

RS_ECC_1 RS_63

RS_62

RS_61

RS_60

RS_59

RS_58

RS_57

RS_56

RS_ECC_2 RS_55

RS_54

RS_53

RS_52

RS_51

RS_50

RS_49

RS_48

RS_ECC_3 RS_47

RS_46

RS_45

RS_44

RS_43

RS_42

RS_41

RS_40

RS_ECC_4 RS_39

RS_38

RS_37

RS_36

RS_35

RS_34

RS_33

RS_32

RS_ECC_5 RS_31

RS_30

RS_29

RS_28

RS_27

RS_26

RS_25

RS_24

RS_ECC_6 RS_23

RS_22

RS_21

RS_20

RS_19

RS_18

RS_17

RS_16

RS_ECC_7 RS_15

RS_14

RS_13

RS_12

RS_11

RS_10

RS_9

RS_8

RS_ECC_8

RS_6

RS_5

RS_4

RS_3

RS_2

RS_1

RS_0

RS_7

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4.EC RegisterECUSB VBUS Control Register (Back)

Bits

Description

7:2

Access

Reset

Reserved.

USB WAKEUP HOSC ENABLE. 0: disable, 1: enable.

RW

VBUS Enable. 0: disable, 1: enable.

RW

Access

Reset

MFP Select
000: F1(GPIO)
001: F2 (KEY8*12)
010: F3 (ILCD)
011: F4 (MROM)
100: F5 (SDRAM)
101: F6 (CF/IDE)
110: reserve
111: F8 (MROM+Sensor)

RW

000

CE0S control.
0: normal .if external pin CE0S=H, the default PAD mode is F1, otherwise
the default PAD mode is F4.
1: the same as CE0S=H.

RW

Output GPOA[3..0] Data[3:0]

RW

1001

4.EE

RegisterEE--MFP Select/GPO_A[2:0] Data Output Register (Back)

Bits

7:5

3:0

Description

Different functions of pins in different function select

PIN

F6(ATA+SDR F8(MROM+Sensor

F4(CE0S=L
F1(CE0S=H default)

F2(key8*12)

F3(ILCD)

NAME

F5(SDRAM)
AM)

default)MROM

+SDRAM)

GPO_A0

GPO_A0/ICEDI

As left

As left

As left

As left

As left

As left

GPO_A1

GPO_A1/ICECK

As left

As left

As left

As left

As left

As left

GPO_A2

GPO_A2/ICEDO

As left

As left

As left

As left

As left

As left

GPIO_B0

KEYI0/GPIO_B0

As left

As left

As left

As left

As left

As left

GPIO_B1

KEYI1/GPIO_B1

As left

As left

As left

As left

As left

As left

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KEYI2/GPIO_B2
GPIO_B2

KEYI2/GPIO_B2

As left

As left

As left

As left

As left

/SPI_SCK
GPIO_B3

KEYI3/GPIO_B3

As left

As left

As left

As left

As left

As left

GPIO_B4

KEYO0/GPIO_B4

As left

As left

As left

As left

As left

As left

GPIO_B5

KEYO1/GPIO_B5

As left

As left

As left

As left

As left

KEYO1/GPIO_B
5/SPI_MOSI
GPIO_B6

KEYO2/GPIO_B6

As left

As left

As left

As left

As left

As left

GPIO_B7

KEYO3/GPIO_B7

As left

As left

As left

As left

As left

As left

GPIO_C0

GPIO_C0

As left

As left

As left

As left

As left

As left

As left

As left

As left

As left

GPIO_C2

GPIO_C2

As left

As left

As left

As left

GPIO_C0/I2C_S
CL
GPIO_C1/I2C_S
GPIO_C1

GPIO_C1
DA/SIRQGPIO_C2

GPIO_C2
/MMC_SCLK
GPIO_C3

GPIO_C3

GPIO_C3

GPIO_C3

CE0-

CE0-

CE0-

CE0-

GPIO_D0

GPIO_D0

GPIO_D0

COM0

A0

A0

A0/ATA-A0

A0

GPIO_D1

GPIO_D1

GPIO_D1

COM1

A1

A1

A1/ATA-A1

A1

GPIO_D2

GPIO_D2

GPIO_D2

COM2

A2

A2

A2/ATA-A2

A2

GPIO_D3

GPIO_D3

GPIO_D3

COM3

A3

A3

A3

A3

As left

As left

As left

As left

As left

As left

As left

As left

As left

As left

GPIO_D4/UART
_RX/SPI_MISO/
GPIO_D4

GPIO_D4
SPDIF_RX/IR_R
X

GPIO_D5/UART
GPIO_D5

GPIO_D5

_TX/SPI_SS/SP
DIF_TX/IR_TX

GPIO_E0

GPIO_E0

GPIO_E0

SEG0

A6

A6

A6

A6

GPIO_E1

GPIO_E1

GPIO_E1

SEG1

A7

A7

A7

A7

GPIO_E2

GPIO_E2

GPIO_E2

SEG2

A8

A8

A8

A8

GPIO_E3

GPIO_E3

GPIO_E3

SEG3

A9

A9

A9

A9

GPIO_E4

GPIO_E4

KEYO4

SEG4

A10

A10

A10

A10

GPIO_E5

GPIO_E5

KEYO5

SEG5

A11

A11

A11

A11

GPIO_E6

GPIO_E6

KEYO6

SEG6

A12

A12

A12

A12

GPIO_E7

GPIO_E7

KEYO7

SEG7

A13

GPIO_F0

GPIO_F0/MMC_D0

KEYI4

SEG8

A14

D8

D8/ATA-D8

A14

GPIO_F1

GPIO_F1/MMC_D1

KEYI5

SEG9

A15

D9

D9/ATA-D9

A15

A13

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GPIO_F2

GPIO_F2/MMC_D2

KEYI6

SEG10

A16

D10

D10/ATA-D10

A16

GPIO_F3

GPIO_F3/MMC_D3

KEYI7

SEG11

A17

D11

D11/ATA-D11

A17

GPIO_F4

GPIO_F4

KEYI8

SEG12

A18

D12

D12/ATA-D12

A18

GPIO_F5

GPIO_F5

KEYI9

SEG13

A19

D13

D13/ATA-D13

A19

GPIO_F6

GPIO_F6

KEYI10

SEG14

A20

D14

D14/ATA-D14

A20

GPIO_F7

GPIO_F7

KEYI11

SEG15

A21

D15

D15/ATA-D15

A21

GPIO_G0

GPIO_G0

GPIO_G0

GPIO_G0

SDMCS

SDMCS

SDMCS

A4

A4

A4

A4

A5

A5

A5

A5

GPIO_G3

GPIO_G3

IO16-(I)

GPIO_G3

GPIO_G0/SE
G16
GPIO_G1/SE
GPIO_G1

GPIO_G1

GPIO_G1
G17
GPIO_G2/SE

GPIO_G2

GPIO_G2

GPIO_G2
G18
GPIO_G3/SE

GPIO_G3

GPIO_G3

GPIO_G3
G19

GPIO_K0

GPIO_K0

GPIO_K0

GPIO_K0

GPIO_K0

SDMCKE

SDMCKE

SDMCKE

GPIO_K1

GPIO_K1

GPIO_K1

GPIO_K1

GPIO_K1

SDMCLK

SDMCLK

SDMCLK

GPIO_K2

GPIO_K2

GPIO_K2

GPIO_K2

GPIO_K2

GPIOK_2

DMARQ

GPIOK_2

GPIO_K3

GPIO_K3

DMACK

GPIOK_3/DABitclk

IORDY

GPIOK_4/DAMCLK

GPIO_K5

GPIO_K5/DA_Data

GPIO_K6

GPIO_K6/DA_LR

GPIOK_3/DABitc GPIOK_3/DAB GPIOK_3/DABi GPIOK_3/DA

lk

itclk

tclk

Bitclk

GPIOK_4/DAMC GPIOK_4/DA GPIOK_4/DAM GPIOK_4/DA

GPIO_K4

GPIO_K4
LK

MCLK

CLK

MCLK

GPIO_K5/DA_D GPIO_K5/DA_ GPIO_K5/DA_ GPIO_K5/DA_

GPIO_K5

GPIO_K5
ata

Data

Data

Data

GPIO_K6/DA_L GPIO_K6/DA_ GPIO_K6/DA_ GPIO_K6/DA_

GPIO_K6

GPIO_K6
R

LR

LR

LR

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D0

Hi-Z

Sensor_D0

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D1

Hi-Z

Sensor_D1

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D2

Hi-Z

Sensor_D2

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D3

Hi-Z

Sensor_D3

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D4

Hi-Z

Sensor_D4

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D5

Hi-Z

Sensor_D5

Sensor_D
0
Sensor_D
1
Sensor_D
2
Sensor_D
3
Sensor_D
4
Sensor_D
5

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Sensor_D
Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D6

Hi-Z

Sensor_D6

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Sensor_D7

Hi-Z

Sensor_D7

GPIO_K7

Hi-Z

GPIOK_7

GPIOK_7

GPIOK_7

SDR-WE-

SDR-WE-

SDR-WE-

PCLK

Hi-Z

Hi-Z

Hi-Z

Hi-Z

PCLK

IOW-

PCLK

Hsync

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hsync

INTRQ(I)

Hsync

Vsync

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Vsync

IOR-

Vsync

BA0

Hi-Z

Hi-Z

Hi-Z

Hi-Z

BA0

BA0

BA0

BA1

Hi-Z

Hi-Z

Hi-Z

Hi-Z

BA1

BA1

BA1

RAS

Hi-Z

Hi-Z

Hi-Z

Hi-Z

RAS

RAS

RAS

CAS

Hi-Z

Hi-Z

Hi-Z

Hi-Z

CAS

CAS

CAS

DQM

Hi-Z

Hi-Z

Hi-Z

Hi-Z

DQM

DQM

DQM

NFV33S

NFV33S

NFV33S

NFV33S

NFV33S

NFV33S

NFV33S

NFV33S

CS0-

Hi-Z

CS0-

CS0-

CS0-

CS0-

CS0-

CS0-

CS1-

Hi-Z

CS1-

CS1-

CS1-

CS1-

CS1-

CS1-

6
Sensor_D
7

4.EF

RegisterEF--GPIO_B[7:0] and KEYI/O[3:0] Config Register(Back)

If any bit of BIT[3..0] is set , the corresponding bit of regC1h should be set too.
GPIOBCONFIG(GPIO_B[7:0] and KEYI/O[3:0] Config Register, 0EFh)
Bits

Description

Access

Reset

GPIO_B7 and KEYO3 select, 0:GPIO_B7, 1: KEYO3

RW

GPIO_B6 and KEYO2 select, 0:GPIO_B6, 1: KEYO2

RW

GPIO_B5 and KEYO1 select, 0:GPIO_B5, 1: KEYO1

RW

GPIO_B4 and KEYO0 select, 0:GPIO_B4, 1: KEYO0

RW

GPIO_B3 and KEYI3 select, 0:GPIO_B3, 1: KEYI3

RW

GPIO_B2 and KEYI2 select, 0:GPIO_B2, 1: KEYI2

RW

GPIO_B1 and KEYI1 select, 0:GPIO_B1, 1: KEYI1

RW

GPIO_B0 and KEYI0 select, 0:GPIO_B0, 1: KEYI0

RW

Access

Reset

4.F0

RegisterF0--GPIO_B[7:0] Output Enable Register (Back)

GPIOBOUTEN(GPIO_B[7:0] Output Enable Register, 0F0h)

Bits

Description

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ATJ209X PROGRAM GUIDE

7

GPIO_B7 Output enable, 0:disable, 1: enable

RW

GPIO_B6 Output enable, 0:disable, 1: enable

RW

GPIO_B5 Output enable, 0:disable, 1: enable

RW

GPIO_B4 Output enable, 0:disable, 1: enable

RW

GPIO_B3 Output enable, 0:disable, 1: enable

RW

GPIO_B2 Output enable, 0:disable, 1: enable

RW

GPIO_B1 Output enable, 0:disable, 1: enable

RW

GPIO_B0 Output enable, 0:disable, 1: enable

RW

Access

Reset

4.F1

RegisterF1--GPIO_B[7:0] Input Enable Register (Back)

Bits

Description

GPIO_B7 Input enable, 0:disable, 1: enable

RW

GPIO_B6 Input enable, 0:disable, 1: enable

RW

GPIO_B5 Input enable, 0:disable, 1: enable

RW

GPIO_B4 Input enable, 0:disable, 1: enable

RW

GPIO_B3 Input enable, 0:disable, 1: enable

RW

GPIO_B2 Input enable, 0:disable, 1: enable

RW

GPIO_B1 Input enable, 0:disable, 1: enable

RW

GPIO_B0 Input enable, 0:disable, 1: enable

RW

Access

Reset

RW

XXh

Access

Reset

4.F2

RegisterF2--GPIO_B[7:0] Data Output/Input Register (Back)

Bits
7:0

4.F3
Bits

Description
Output/Input Data[7:0]

RegisterF3--GPIO_C[3:0] Output/Input Enable Register (Back)

Description

GPIO_C3 Input enable, 0:disable, 1: enable

RW

GPIO_C2 Input enable, 0:disable, 1: enable

RW

GPIO_C1 Input enable, 0:disable, 1: enable

RW

GPIO_C0 Input enable, 0:disable, 1: enable

RW

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3

GPIO_C3 Output enable, 0:disable, 1: enable

RW

GPIO_C2 Output enable, 0:disable, 1: enable

RW

GPIO_C1 Output enable, 0:disable, 1: enable

RW

GPIO_C0 Output enable, 0:disable, 1: enable

RW

Access

Reset

RW

1111

Access

Reset

4.F4

RegisterF4--GPIO_C[3:0] Data Output/Input Register (Back)

Bits

Description

7:4

Reserved

3:0

Output/Input Data[3:0]

4.F5

RegisterF5--GPIO_D[5:0] Output Enable Register (Back)

Bits

Description

GPIO_D5 multifunctional pin enable.0:disable,1:enable.

RW

GPIO_D4 multifunctional pin enable.0:disable,1:enable.

RW

GPIO_D5 Output enable, 0:disable, 1: enable

RW

GPIO_D4 Output enable, 0:disable, 1: enable

RW

GPIO_D3 Output enable, 0:disable, 1: enable

RW

GPIO_D2 Output enable, 0:disable, 1: enable

RW

GPIO_D1 Output enable, 0:disable, 1: enable

RW

GPIO_D0 Output enable, 0:disable, 1: enable

RW

Access

Reset

4.F6

RegisterF6--GPIO_D[5:0] Input Enable Register (Back)

Bits
7:6

Description
Reserved

GPIO_D5 Input enable, 0:disable, 1: enable

RW

GPIO_D4 Input enable, 0:disable, 1: enable

RW

GPIO_D3 Input enable, 0:disable, 1: enable

RW

GPIO_D2 Input enable, 0:disable, 1: enable

RW

GPIO_D1 Input enable, 0:disable, 1: enable

RW

GPIO_D0 Input enable, 0:disable, 1: enable

RW

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4.F7

RegisterF7--GPIO_D[5:0] Data Output/Input Register(Back)

Bits

Description

7:6
5:0

4.F8

RW

Output/Input Data[5:0]

Reset

Reserved

Access

000000

Access

Reset

RegisterF8--GPIO_E[7:0] Output Enable Register(Back)

Bits

Description

GPIO_E7 Output enable, 0:disable, 1: enable

RW

GPIO_E6 Output enable, 0:disable, 1: enable

RW

GPIO_E5 Output enable, 0:disable, 1: enable

RW

GPIO_E4 Output enable, 0:disable, 1: enable

RW

GPIO_E3 Output enable, 0:disable, 1: enable

RW

GPIO_E2 Output enable, 0:disable, 1: enable

RW

GPIO_E1 Output enable, 0:disable, 1: enable

RW

GPIO_E0 Output enable, 0:disable, 1: enable

RW

Access

Reset

4.F9

RegisterF9--GPIO_E[7:0] Input Enable Register (Back)

Bits

Description

GPIO_E7 Input enable, 0:disable, 1: enable

RW

GPIO_E6 Input enable, 0:disable, 1: enable

RW

GPIO_E5 Input enable, 0:disable, 1: enable

RW

GPIO_E4 Input enable, 0:disable, 1: enable

RW

GPIO_E3 Input enable, 0:disable, 1: enable

RW

GPIO_E2 Input enable, 0:disable, 1: enable

RW

GPIO_E1 Input enable, 0:disable, 1: enable

RW

GPIO_E0 Input enable, 0:disable, 1: enable

RW

Access

Reset

RW

4.FA RegisterFA--GPIO_E[7:0] Data Output/Input Register (Back)

Bits
7:0

Description
Output/Input Data[7:0]

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4.FB RegisterFB--GPIO_F[7:0] Output Enable Register (Back)

Bits

Description

Access

Reset

GPIO_F7 Output enable, 0:disable, 1: enable

RW

GPIO_F6 Output enable, 0:disable, 1: enable

RW

GPIO_F5 Output enable, 0:disable, 1: enable

RW

GPIO_F4 Output enable, 0:disable, 1: enable

RW

GPIO_F3 Output enable, 0:disable, 1: enable

RW

GPIO_F2 Output enable, 0:disable, 1: enable

RW

GPIO_F1 Output enable, 0:disable, 1: enable

RW

GPIO_F0 Output enable, 0:disable, 1: enable

RW

Access

Reset

4.FC

RegisterFC--GPIO_F[7:0] Input Enable Register (Back)

Bits

Description

GPIO_F7 Input enable, 0:disable, 1: enable

RW

GPIO_F6 Input enable, 0:disable, 1: enable

RW

GPIO_F5 Input enable, 0:disable, 1: enable

RW

GPIO_F4 Input enable, 0:disable, 1: enable

RW

GPIO_F3 Input enable, 0:disable, 1: enable

RW

GPIO_F2 Input enable, 0:disable, 1: enable

RW

GPIO_F1 Input enable, 0:disable, 1: enable

RW

GPIO_F0 Input enable, 0:disable, 1: enable

RW

Access

Reset

RW

XXh

Access

Reset

RW

4.FD

RegisterFD--GPIO_F[7:0] Data Output/Input Register (Back)

Bits
7:0

4.FE
Bits
7

Description
Output/Input Data[7:0]

RegisterFE--GPIO_G[3:0] Output/Input Enable Register (Back)

Description
GPIO_G3 Input enable, 0:disable, 1: enable

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ATJ209X PROGRAM GUIDE

6

GPIO_G2 Input enable, 0:disable, 1: enable

RW

GPIO_G1 Input enable, 0:disable, 1: enable

RW

GPIO_G0 Input enable, 0:disable, 1: enable

RW

GPIO_G3 Output enable, 0:disable, 1: enable

RW

GPIO_G2 Output enable, 0:disable, 1: enable

RW

GPIO_G1 Output enable, 0:disable, 1: enable

RW

GPIO_G0 Output enable, 0:disable, 1: enable

RW

Access

Reset

4.FF

RegisterFF--GPIO_G[3:0] Data Output/Input Register (Back)

Bits

Description

GPIO_G3 MFP to SEG19. 0: disable, 1: enable

RW

GPIO_G2 MFP to SEG18. 0: disable, 1: enable

RW

GPIO_G1 MFP to SEG17. 0: disable, 1: enable

RW

GPIO_G0 MFP to SEG16. 0: disable, 1: enable

RW

Output/Input Data[3:0]

RW

xxxx

3:0

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5. Abbreviation
ACKAcknowledgement
ADCAnalog Digital Convert
ATAIRQAdvanced Technology Attachment Interrupt Request
CTCClock/Timer/Counter
DACDigital Analog Convert
DMADirect Memory Address
DRQData Request
DSTDestination
DSTDestination
ECCError Correction Code
EMExternal Memory
FIFOFirst In First Out
HIPHost Interface Port
HOSCHigh Frequency Oscillator
IDMInternal Data Memory
IPMInternal Program Memory
IRQInterrupt Request
IRInfra-red
I2CINTERIC
LOSCLow Frequency Oscillator
MICMicrophone
NAKNegative Acknowledgement
PLLPhase Locked Loop

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RTCReal Time Clock
RBReady/Busy
SIRQSystem Interrupt Request
SPDIFSony/Philips Digital Interface
SPISerial Port Interface
SRCSource
TCTransmit Complete
TPTouch Panel
UARTUniversal Asynchronous Receiver/Transmitter

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ACTIONS SEMICONDUCTOR CO., LTD.

Address: Bldg.15-1, NO.1, HIT Rd., Tangjia, Zhuhai, Guangdong, China
Tel: +86-756-3392353
Fax: +86-756-3392251
Post code: 519085
http://www.actions-semi.com
Business Email: [email protected]
Technical Service Email: [email protected]

Copyright 2005 Actions Semiconductor Co., Ltd. All rights reserved.