ECopyright 1997 by Dallas Semiconductor Corporation.

All Rights Reserved. For important information regarding

patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
DS1985
16K bit AddOnly iButton
TM
DS1985
032497 1/23
SPECIAL FEATURES
16384bits Electrically Programmable Read Only
Memory (EPROM) communicates with the economy
of one signal plus ground
EPROM partitioned into sixtyfour 256bit pages for
randomly accessing packetized data records
Each memory page can be permanently writepro-
tected to prevent tampering
Device is an add only memory where additional data
can be programmed into EPROM without disturbing
existing data
Architecture allows software to patch data by super-
seding an old page in favor of a newly programmed
page
Reduces control, address, data, power, and program-
ming signals to a single data pin
8bit family code specifies DS1985 communications
requirements to reader
Reads over a wide voltage range of 2.8V to 6.0V from
40C to +85C; programs at 11.5V to 12.0V from
40C to +85C
COMMON iButton FEATURES
Unique, factorylasered and tested 64bit registra-
tion number (8bit family code + 48bit serial number
+ 8bit CRC tester) assures absolute traceability
because no two parts are alike
Multidrop controller for MicroLAN
TM
Digital identification and information by momentary
contact
Chipbased data carrier compactly stores informa-
tion
Data can be accessed while affixed to object
Economically communicates to bus master with a
single digital signal at 16.3k bits per second
Standard 16 mm diameter and 1Wire
TM
protocol
ensure compatibility with iButton family
Button shape is selfaligning with cupshaped
probes
Durable stainless steel case engraved with registra-
tion number withstands harsh environments
Easily affixed with selfstick adhesive backing,
latched by its flange, or locked with a ring pressed
onto its rim
Presence detector acknowledges when reader first
applies voltage
Meets UL#913 (4th Edit.); Intrinsically Safe Appara-
tus, Approved under Entity Concept for use in Class
I, Division 1, Group A, B, C and D Locations (applica-
tion pending)
F3 MICROCAN
TM
3.10
GROUND
DATA
0.36
0.51
0B ED
000000FBC52B
YYWW
16.25
17.35
REGISTERED RR
All dimensions shown in millimeters.
F5 MICROCAN
TM
5.89
GROUND
DATA
0.36
0.51
0B 6D
000000FBD8B3
YYWW
16.25
17.35
REGISTERED RR
DS1985
032497 2/23
ORDERING INFORMATION
DS1985F3 F3 MicroCan
DS1985F5 F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P SelfStick Adhesive Pad
DS9101 MultiPurpose Clip
DS9093RA Mounting Lock Ring
DS9093F SnapIn Fob
DS9092 iButton Probe
iButton DESCRIPTION
The DS1985 16k bit AddOnly iButton is a rugged read/
write data carrier that identifies and stores relevant
information about the product or person to which it is
attached. This information can be accessed with mini-
mal hardware, for example a single port pin of a micro-
controller. The DS1985 consists of a factorylasered
registration number that includes a unique 48bit serial
number, an 8bit CRC, and an 8bit Family Code (0BH)
plus 16k bit of EPROM which is userprogrammable.
The power to program and read the DS1985 is derived
entirely from the 1Wire communication line. Data is
transferred serially via the 1Wire protocol which
requires only a single data lead and a ground return. The
entire device can be programmed and then writepro-
tected if desired. Alternatively, the part may be pro-
grammed multiple times with new data being appended
to, but not overwriting, existing data with each subse-
quent programming of the device. Note: Individual bits
can be changed only from a logical 1 to a logical 0, never
from a logical 0 to a logical 1. A provision is also included
for indicating that a certain page or pages of data are no
longer valid and have been replaced with new or
updated data that is now residing at an alternate page
address. This page address redirection allows software
to patch data and enhance the flexibility of the device as
a standalone database. The 48bit serial number that is
factorylasered into each DS1985 provides a guaran-
teed unique identity which allows for absolute traceabil-
ity. The durable MicroCan package is highly resistant to
harsh environments such as dirt, moisture, and shock.
Its compact buttonshaped profile is selfaligning with
cupshaped receptacles, allowing the DS1985 to be
used easily by human operators or automatic equipment.
Accessories permit the DS1985 to be mounted on printed
circuit boards, plastic key fobs, photoID badges, ID
bracelets, and many other objects. Applications include
workinprogress tracking, electronic travelers, access
control, storage of calibration constants, and debit
tokens.
OVERVIEW
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS1985. The DS1985 has three main data compo-
nents: 1) 64bit lasered ROM, 2) 16384bits EPROM
Data Memory, and 3) 704bits EPROM Status Memory.
The device derives its power for read operations entirely
from the 1Wire communication line by storing energy
on an internal capacitor during periods of time when the
signal line is high and continues to operate off of this
parasite power source during the low times of the
1Wire line until it returns high to replenish the parasite
(capacitor) supply. During programming, 1Wire com-
munication occurs at normal voltage levels and then is
pulsed momentarily to the programming voltage to
cause the selected EPROM bits to be programmed. The
1Wire line must be able to provide 12 volts and 10 mil-
liamperes to adequately program the EPROM portions
of the part. Whenever programming voltages are pres-
ent on the 1Wire line a special high voltage detect cir-
cuit within the DS1985 generates an internal logic signal
to indicate this condition. The hierarchical structure of
the 1Wire protocol is shown in Figure 2. The bus mas-
ter must first provide one of the four ROM Function
Commands, 1) Read ROM, 2) Match ROM, 3) Search
ROM, 4) Skip ROM. These commands operate on the
64bit lasered ROM portion of each device and can sin-
gulate a specific device if many are present on the
1Wire line as well as indicate to the bus master how
many and what types of devices are present. The proto-
col required for these ROM Function Commands is
described in Figure 8. After a ROM Function Command
is successfully executed, the memory functions that
operate on the EPROM portions of the DS1985 become
accessible and the bus master may issue any one of the
five Memory Function Commands specific to the
DS1985 to read or program the various data fields. The
protocol for these Memory Function Commands is
described in Figure 5. All data is read and written least
significant bit first.
64BIT LASERED ROM
Each DS1985 contains a unique ROM code that is 64
bits long. The first eight bits are a 1Wire family code.
The next 48 bits are a unique serial number. The last
eight bits are a CRC of the first 56 bits. (See Figure 3.)
The 64bit ROM and ROM Function Control section
allow the DS1985 to operate as a 1Wire device and fol-
low the 1Wire protocol detailed in the section 1Wire
Bus System. The memory functions required to read
PARASITE POWER
1WIRE FUNCTION
CONTROL
64BIT LASERED
ROM
PROGRAM
VOLTAGE
DETECT
MEMORY
FUNCTION
CONTROL
8BIT
SCRATCHPAD
16BIT CRC
GENERATOR
16KBIT EPROM
(64 PAGES OF 32 BYTES)
88 EPROM
STATUS BYTES
DATA 1WIRE
BUS
DS1985
032497 3/23
and program the EPROM sections of the DS1985 are
not accessible until the ROM function protocol has been
satisfied. This protocol is described in the ROM func-
tions flow chart (Figure 8). The 1Wire bus master must
first provide one of four ROM function commands: 1)
Read ROM, 2) Match ROM, 3) Search ROM, or 4) Skip
ROM. After a ROM function sequence has been suc-
cessfully executed, the bus master may then provide
any one of the memory function commands specific to
the DS1985 (Figure 5).
The 1Wire CRC of the lasered ROM is generated using
the polynomial X
8
+ X
5
+ X
4
+ 1. Additional information
about the Dallas Semiconductor 1Wire Cyclic Redun-
dancy Check is available in the Book of DS19xx iButton
Standards. The shift register acting as the CRC accu-
mulator is initialized to zero. Then starting with the least
significant bit of the family code, one bit at a time is
shifted in. After the eighth bit of the family code has been
entered, then the serial number is entered. After the
48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits
of CRC should return the shift register to all zeroes.
DS1985 BLOCK DIAGRAM Figure 1
DS1985
032497 4/23
HIERARCHICAL STRUCTURE FOR 1WIRE PROTOCOL Figure 2
1WIRE ROM FUNCTION
COMMANDS (SEE FIGURE 9)
DS1985SPECIFIC
MEMORY FUNCTION
COMMANDS
(SEE FIGURE 6)
COMMAND
LEVEL:
AVAILABLE
COMMANDS:
DATA FIELD
AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
64BIT ROM
64BIT ROM
64BIT ROM
N/A
WRITE MEMORY 16K BIT EPROM
WRITE STATUS
READ MEMORY
READ STATUS
EXTENDED READ DATA
EPROM STATUS BYTES
16K BIT EPROM
EPROM STATUS BYTES
16K BIT EPROM
BUS
MASTER
1WIRE BUS
OTHER
DEVICES
DS1985
64BIT LASERED ROM Figure 3
8Bit CRC Code 48Bit Serial Number 8Bit Family Code (0BH)
MSB LSB MSB LSB MSB LSB
DS1985
032497 5/23
16384BITS EPROM
The memory map in Figure 4 shows the 16384bits
EPROM section of the DS1985 which is configured as
sixtyfour pages of 32 bytes each. The 8bit scratchpad
is an additional register that acts as a buffer when pro-
gramming the memory. Data is first written to the
scratchpad and then verified by reading an 16bit CRC
from the DS1985 that confirms proper receipt of the data
and address. If the buffer contents are correct, a pro-
gramming voltage should be applied and the byte of
data will be written into the selected address in memory.
This process insures data integrity when programming
the memory. The details for reading and programming
the 16384bits EPROM portion of the DS1985 are given
in the Memory Function Commands section.
EPROM STATUS BYTES
In addition to the 16384 bits of data memory the DS1985
provides 704 bits of Status Memory accessible with
separate commands.
The EPROM Status Bytes can be read or programmed
to indicate various conditions to the software interrogat-
ing the DS1985. The first eight bytes of the EPROM Sta-
tus Memory (addresses 000 to 007H) contain the Write
Protect Page bits which inhibit programming of the cor-
responding page in the 16384bit main memory area if
the appropriate write protection bit is programmed.
Once a bit has been programmed in the Write Protect
Page section of the Status Memory, the entire 32 byte
page that corresponds to that bit can no longer be
altered but may still be read.
The next eight bytes of the EPROM Status Memory
(addresses 020 to 027H) contain the Write Protect bits
which inhibit altering the Page Address Redirection
Byte corresponding to each page in the 16384bit main
memory area.
The following eight bytes within the EPROM Status
Memory (addresses 040 to 047H) are reserved for use
by the iButton operating software TMEX. Their purpose
is to indicate which memory pages are already in use.
Originally, all of these bits are unprogrammed, indicat-
ing that the device does not store any data. As soon as
data is written to any page of the device under control of
TMEX, the bit inside this bitmap corresponding to that
page will be programmed to 0, marking this page as
used. These bits are application flags only and have no
impact on the internal logic of the DS1985.
The next sixtyfour bytes of the EPROM Status Memory
(addresses 100H to 13FH) contain the Page Address
Redirection Bytes which indicate if one or more of the
pages of data in the 16384bits EPROM section have
been invalidated by software and redirected to the page
address contained in the appropriate redirection byte.
The hardware of the DS1985 makes no decisions based
on the contents of the Page Address Redirection Bytes.
These additional bytes of Status EPROM allow for the
redirection of an entire page to another page address,
indicating that the data in the original page is no longer
considered relevant or valid. With EPROM technology,
bits within a page can be changed from a logical 1 to a
logical 0 by programming, but cannot be changed back.
Therefore, it is not possible to simply rewrite a page if the
data requires changing or updating, but with space per-
mitting, an entire page of data can be redirected to
another page within the DS1985 by writing the ones
complement of the new page address into the Page
Address Redirection Byte that corresponds to the origi-
nal (replaced) page.
This architecture allows the users software to make a
data patch to the EPROM by indicating that a particu-
lar page or pages should be replaced with those indi-
cated in the Page Address Redirection Bytes. To leave
an authentic audit trail of data patches, it is recom-
mended to also program the write protect bit of the Page
Address Redirection Byte, after the page redirection is
programmed. Without this protection, it is still possible
to modify the Page Address Redirection Byte, making it
point to a different memory page than the true one.
If a Page Address Redirection Byte has a FFH value, the
data in the main memory that corresponds to that page
is valid. If a Page Address Redirection Byte has some
other hex value, the data in the page corresponding to
that redirection byte is invalid, and the valid data can
now be found at the ones complement of the page
address indicated by the hex value stored in the
associated Page Address Redirection Byte. A value of
FDH in the redirection byte for page 1, for example,
would indicate that the updated data is now in page 2.
The details for reading and programming the EPROM
status memory portion of the DS1985 are given in the
Memory Function Commands section.
The Status Memory address range of the DS1985
extends from 000 to 13FH. The memory locations 008H
to 01FH, 028H to 03FH, 048H to 0FFH and 140H to
RESERVED
RESERVED
000H
007H
008H
01FH
020H
027H
028H
03FH
040H
047H
048H
0FFH
100H
13FH
11 PAGES OF
8 BYTES
EACH
8 BYTES
WRITEPROTECT BITS
DATA MEMORY
WRITEPROTECT BITS
OF REDIRECTION BYTES
BIT MAP OF
USED PAGES
RESERVED FOR
FUTURE EXTENSIONS
REDIRECTION
BYTES

BIT 0 OF ADDRESS 000H=

ADDRESS 100H=PAGE ADDRESS
REDIRECTION BYTE FOR PAGE 0, ETC.
WRITE PROTECT
OF PAGE 0, ETC.
DS1985
032497 6/23
7FFH are physically not implemented. Reading these
locations will usually result in FFH bytes. Attempts to
write to these locations will be ignored. If the bus master
sends a starting address higher than 7FFH, the five
most significant address bits are set to zeros by the
internal circuitry of the chip. This will result in a mis-
match between the CRC calculated by the DS1985 and
the CRC calculated by the bus master, indicating an
error condition.
DS1985 MEMORY MAP Figure 4
32BYTE FINAL STORAGE EPROM PAGE 0
PAGE 1
PAGE 63
8BIT
REDIRECTION
BIT MAP OF
USED PAGES
WRITEPROTECT BITS
REDIRECTION BYTES
WRITEPROTECT BITS
DATA MEMORY
88 BYTES
STATUS MEMORY
SCRATCHPAD
STARTING
ADDRESS
0000H
0020H
0040H
07E0H
16K BIT
EPROM
32BYTE FINAL STORAGE EPROM
32BYTE FINAL STORAGE EPROM
BYTES
STATUS MEMORY MAP
DS1985
032497 7/23
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 5) describes
the protocols necessary for accessing the various data
fields within the DS1985. The Memory Function Control
section, 8bit scratchpad, and the Program Voltage
Detect circuit combine to interpret the commands
issued by the bus master and create the correct control
signals within the device. A threebyte protocol is
issued by the bus master. It is comprised of a command
byte to determine the type of operation and two address
bytes to determine the specific starting byte location
within a data field. The command byte indicates if the
device is to be read or written. Writing data involves not
only issuing the correct command sequence but also
providing a 12V programming voltage at the appropriate
times. To execute a write sequence, a byte of data is first
loaded into the scratchpad and then programmed into
the selected address. Write sequences always occur a
byte at a time. To execute a read sequence, the starting
address is issued by the bus master and data is read
from the part beginning at that initial location and contin-
uing to the end of the selected data field or until a reset
sequence is issued. All bits transferred to the DS1985
and received back by the bus master are sent least sig-
nificant bit first.
READ MEMORY [F0H]
The Read Memory command is used to read data from
the 16384bits EPROM data field. The bus master fol-
lows the command byte with a two byte address
(TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. With every subse-
quent read data time slot the bus master receives data
from the DS1985 starting at the initial address and con-
tinuing until the end of the 16384bits data field is
reached or until a Reset Pulse is issued. If reading
occurs through the end of memory space, the bus mas-
ter may issue sixteen additional read time slots and the
DS1985 will respond with a 16bit CRC of the com-
mand, address bytes and all data bytes read from the
initial starting byte through the last byte of memory. This
CRC is the result of clearing the CRC generator and
then shifting in the command byte followed by the two
address bytes and the data bytes beginning at the first
addressed memory location and continuing through to
the last byte of the EPROM data memory. After the CRC
is received by the bus master, any subsequent read time
slots will appear as logical 1s until a Reset Pulse is
issued. Any reads ended by a Reset Pulse prior to
reaching the end of memory will not have the 16bit
CRC available.
Typically a 16bit CRC would be stored with each page
of data to insure rapid, errorfree data transfers that
eliminate having to read a page multiple times to deter-
mine if the received data is correct or not. (See Book of
DS19xx iButton Standards, Chapter 7 for the recom-
mended file structure to be used with the 1Wire envi-
ronment.) If CRC values are imbedded within the data, a
Reset Pulse may be issued at the end of memory space
during a Read Memory command.
READ STATUS [AAH]
The Read Status command is used to read data from
the EPROM Status data field. The bus master follows
the command byte with a two byte address
(TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. With every subse-
quent read data time slot the bus master receives data
from the DS1985 starting at the supplied address and
continuing until the end of an eightbyte page of the
EPROM Status data field is reached. At that point the
bus master will receive a 16bit CRC of the command
byte, address bytes and status data bytes. This CRC is
computed by the DS1985 and read back by the bus
master to check if the command word, starting address
and data were received correctly. If the CRC read by the
bus master is incorrect, a Reset Pulse must be issued
and the entire sequence must be repeated.
Note that the initial pass through the Read Status flow
chart will generate a 16bit CRC value that is the result
of clearing the CRC generator and then shifting in the
command byte followed by the two address bytes, and
finally the data bytes beginning at the first addressed
memory location and continuing through to the last byte
of the addressed EPROM Status data page. The last
byte of a Status data page always has an ending
address of xx7 or xxFH. Subsequent passes through
the Read Status flow chart will generate a 16bit CRC
that is the result of clearing the CRC generator and then
shifting in the new data bytes starting at the first byte of
the next page of the EPROM Status data field.
This feature is provided since the EPROM Status
information may change over time making it impossible
to program the data once and include an accompanying
CRC that will always be valid. Therefore, the Read Sta-
tus command supplies a 16bit CRC that is based on
and always is consistent with the current data stored in
the EPROM Status data field.
DS1985
032497 8/23
MEMORY FUNCTION FLOW CHART Figure 5
F0h
READ
MEMORY
?
N
BUS MASTER T
X
TA1 (T7:T0)
BUS MASTER T
X
TA2 (T15:T8)
DS1985 SETS MEMORY
ADDRESS = (T15:T0)
Y
BUS MASTER R
X
DATA FROM
DATA MEMORY
BUS MASTER
T
X
RESET
?
END
OF DATA
MEMORY
?
DS1985 INCREMENTS
ADDRESS COUNTER
DS1985 T
X
PRESENCE PULSE
AAh
READ STATUS
?
BUS MASTER T
X
TA1 (T7:T0)
BUS MASTER T
X
TA2 (T15:T8)
DS1985 SETS STATUS
ADDRESS = (T15:T0)
BUS MASTER R
X
DATA FROM
STATUS MEMORY
BUS MASTER
T
X
RESET
?
END OF
PAGE
?
BUS MASTER R
X
CRC16 OF COMMAND,
ADDRESS, DATA
BUS MASTER
T
X
RESET
?
BUS MASTER
R
X
1S
DS1985 INCREMENTS
ADDRESS COUNTER
Y
Y
N
Y
N
Y
N
Y
Y
N
N
Y
N
BUS MASTER
T
X
RESET
?
N
BUS MASTER R
X
CRC16 OF
COMMAND, ADDRESS, DATA
(1ST PASS)
CRC16 OF DATA (SUBSEQUENT
PASSES)
BUS MASTER
T
X
RESET
?
BUS MASTER
R
X
1S
Y
N
END OF
STATUS
MEMORY
?
N
Y
Y
MASTER T
X
MEMORY
FUNCTION COMMAND
Y
CRC
CORRECT
?
BUS MASTER
T
X
RESET
N
Y
BUS MASTER
T
X
RESET
A5h
EXTENDED
READ MEMORY
?
N
BUS MASTER T
X
TA1 (T7:T0)
BUS MASTER T
X
TA2 (T15:T8)
DS1985 SETS MEMORY
ADDRESS = (T15:T0)
Y
BUS MASTER R
X
REDIR. BYTE
CRC
CORRECT
?
DS1985 INCREMENTS
ADDRESS COUNTER
Y
Y
N
BUS MASTER R
X
DATA FROM
DATA MEMORY
BUS MASTER
T
X
RESET
?
END OF
PAGE
?
BUS MASTER R
X
CRC16
OF PRECEDING PAGE OF DATA
END OF
MEMORY
?
BUS MASTER
T
X
RESET
?
BUS MASTER
R
X
1S
Y
N
N
Y
N
Y
Y
N
DS1985 INCREMENTS
ADDRESS COUNTER
DS1985 T
X
PRESENCE PULSE
TO WRITE COMMANDS
LEGEND:
DECISION MADE
BY THE MASTER
DECISION MADE
BY DS1985
BUS MASTER R
X
CRC16 OF
COMMAND, ADDRESS, REDIR. BYTE
(1ST PASS)
CRC16 OF REDIR. BYTE
(SUBSEQUENT PASSES)
BUS MASTER
T
X
RESET
CRC
CORRECT
?
N
DS1985
032497 9/23
MEMORY FUNCTION FLOW CHART (contd) Figure 5
DS1985
032497 10/23
MEMORY FUNCTION FLOW CHART (contd) Figure 5
0Fh
WRITE
MEMORY
?
N
BUS MASTER T
X
TA1 (T7:T0)
BUS MASTER T
X
TA2 (T15:T8)
BUS MASTER R
X
CRC16
OF COMMAND, ADDRESS,
DATA (1
ST
PASS)
CRC16 OF ADDRESS, DATA
(SUBSEQUENT PASSES)
CRC
CORRECT
?
Y
BUS MASTER T
X
DATA BYTE (D7:D0)
BUS MASTER T
X
PROGRAM PULSE
BUS MASTER R
X
BYTE FROM EPROM
END OF
DATA MEMORY
?
DS1985 INCREMENTS
ADDRESS COUNTER
DS1985 LOADS NEW
ADDRESS INTO CRC
GENERATOR
MASTER T
X
RESET
55h
WRITE
STATUS
?
BUS MASTER T
X
TA1 (T7:T0)
BUS MASTER T
X
TA2 (T15:T8)
CRC
CORRECT
?
BUS MASTER T
X
DATA BYTE (D7:D0)
BUS MASTER T
X
PROGRAM PULSE
BUS MASTER R
X
BYTE FROM EPROM
MASTER T
X
RESET
N
Y
Y
N
N
Y
N
Y
Y
EPROM BYTE =
DATA BYTE
?
END OF
STATUS
MEMORY
?
DS1985 INCREMENTS
ADDRESS COUNTER
DS1985 LOADS NEW
ADDRESS INTO CRC
GENERATOR
Y
N
Y
EPROM BYTE =
DATA BYTE
?
BUS MASTER R
X
CRC16
OF COMMAND, ADDRESS,
DATA (1
ST
PASS)
CRC16 OF ADDRESS, DATA
(SUBSEQUENT PASSES)
N N
BUS MASTER
T
X
RESET
DS1985 T
X
PRESENCE PULSE
DS1985 COPIES
SCRATCHPAD
TO STATUS EPROM
DS1985 COPIES
SCRATCHPAD
TO DATA EPROM
DS1985
032497 11/23
After the 16bit CRC of the last EPROM Status data
page is read, the bus master will receive logical 1s from
the DS1985 until a Reset Pulse is issued. The Read Sta-
tus command sequence can be ended at any point by
issuing a Reset Pulse.
EXTENDED READ MEMORY [A5H]
The Extended Read Memory command supports page
redirection when reading data from the 16384bit
EPROM data field. One major difference between the
Extended Read Memory and the basic Read Memory
command is that the bus master receives the Redirec-
tion Byte first before investing time in reading data from
the addressed memory location. This allows the bus
master to quickly decide whether to continue and
access the data at the selected starting page or to termi-
nate and restart the reading process at the redirected
page address. A nonredirected page is identified by a
Redirection Byte with a value of FFH (see description of
EPROM Status Bytes). If the Redirection Byte is differ-
ent than this, the master has to complement it to obtain
the new page number. Multiplying the page number by
32 (20H) results in the new address the master has to
send to the DS1985 to read the updated data replacing
the old data. There is no logical limitation in the number
of redirections of any page. The only limit is the number
of available memory pages within the DS1985.
In addition to page redirection, the Extended Read
Memory command also supports bitoriented applica-
tions where the user cannot store a 16bit CRC with the
data itself. With bitoriented applications the EPROM
information may change over time within a page bound-
ary making it impossible to include an accompanying
CRC that will always be valid. Therefore, the Extended
Read Memory command concludes each page with the
DS1985 generating and supplying a 16bit CRC that is
based on and therefore always consistent with the cur-
rent data stored in each page of the 16384bit EPROM
data field.
After having sent the command code of the Extended
Read Memory command, the bus master follows the
command byte with a two byte address (TA1=(T7:T0),
TA2=(T15:T8)) that indicates a starting byte location
within the data field. By sending eight read data time
slots, the master receives the Redirection Byte
associated with the page given by the starting address.
With the next sixteen read data time slots, the bus mas-
ter receives a 16bit CRC of the command byte,
address bytes and the Redirection Byte. This CRC is
computed by the DS1985 and read back by the bus
master to check if the command word, starting address
and Redirection Byte were received correctly.
If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is cor-
rect, the bus master issues read time slots and receives
data from the DS1985 starting at the initial address and
continuing until the end of a 32byte page is reached. At
that point the bus master will send sixteen additional
read time slots and receive a 16bit CRC that is the
result of shifting into the CRC generator all of the data
bytes from the initial starting byte to the last byte of the
current page.
With the next 24 read data time slots the master will
receive the Redirection Byte of the next page followed
by a 16bit CRC of the Redirection Byte. After this, data
is again read from the 16384bit EPROM data field
starting at the beginning of the new page. This
sequence will continue until the final page and its
accompanying CRC are read by the bus master.
The Extended Read Memory command provides a
16bit CRC at two locations within the transaction flow
chart: 1) after the Redirection Byte and 2) at the end of
each memory page. The CRC at the end of the memory
page is always the result of clearing the CRC generator
and shifting in the data bytes beginning at the first
addressed memory location of the EPROM data page
until the last byte of this page. The CRC received by the
bus master directly following the Redirection Byte, is
calculated in two different ways. With the initial pass
through the Extended Read Memory flow chart the
16bit CRC value is the result of shifting the command
byte into the cleared CRC generator, followed by the two
address bytes and the Redirection Byte. Subsequent
passes through the Extended Read Memory flow chart
will generate a 16bit CRC that is the result of clearing
the CRC generator and then shifting in the Redirection
Byte only.
After the 16bit CRC of the last page is read, the bus
master will receive logical 1s from the DS1985 until a
Reset Pulse is issued. The Extended Read Memory
command sequence can be ended at any point by issu-
ing a Reset Pulse.
DS1985
032497 12/23
WRITE MEMORY [0FH]
The Write Memory command is used to program the
16384bit EPROM data field. The bus master will follow
the command byte with a two byte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a byte of data
(D7:D0). A 16bit CRC of the command byte, address
bytes, and data byte is computed by the DS1985 and
read back by the bus master to confirm that the correct
command word, starting address, and data byte were
received.
The highest starting address within the DS1985 is
07FFH. If the bus master sends a starting address
higher than this, the five most significant address bits
are set to zero by the internal circuitry of the chip. This
will result in a mismatch between the CRC calculated by
the DS1985 and the CRC calculated by the bus master,
indicating an error condition.
If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is cor-
rect, a programming pulse (12 volts on the 1Wire bus
for 480 s) is issued by the bus master. Prior to program-
ming, the entire unprogrammed 16384bit EPROM
data field will appear as logical 1s. For each bit in the
data byte provided by the bus master that is set to a log-
ical 0, the corresponding bit in the selected byte of the
16384bit EPROM will be programmed to a logical 0
after the programming pulse has been applied at that
byte location.
After the 480 s programming pulse is applied and the
data line returns to the idle level, the bus master issues
eight read time slots to verify that the appropriate bits
have been programmed. The DS1985 responds with
the data from the selected EPROM address sent least
significant bit first. This byte contains the logical AND of
all bytes written to this EPROM data address. If the
EPROM data byte contains 1s in bit positions where the
byte issued by the master contained 0s, a Reset Pulse
should be issued and the current byte address should
be programmed again. If the DS1985 EPROM data byte
contains 0s in the same bit positions as the data byte,
the programming was successful and the DS1985 will
automatically increment its address counter to select
the next byte in the 16384bit EPROM data field. The
new twobyte address will also be loaded into the 16bit
CRC generator as a starting value. The bus master will
issue the next byte of data using eight write time slots.
As the DS1985 receives this byte of data into the
scratchpad, it also shifts the data into the CRC genera-
tor that has been preloaded with the current address
and the result is a 16bit CRC of the new data byte and
the new address. After supplying the data byte, the bus
master will read this 16bit CRC from the DS1985 with
sixteen read time slots to confirm that the address
incremented properly and the data byte was received
correctly. If the CRC is incorrect, a Reset Pulse must be
issued and the Write Memory command sequence must
be restarted. If the CRC is correct, the bus master will
issue a programming pulse and the selected byte in
memory will be programmed.
Note that the initial pass through the Write Memory flow
chart will generate a 16bit CRC value that is the result
of shifting the command byte into the CRC generator,
followed by the two address bytes, and finally the data
byte. Subsequent passes through the Write Memory
flow chart due to the DS1985 automatically increment-
ing its address counter will generate a 16bit CRC that
is the result of loading (not shifting) the new (increm-
ented) address into the CRC generator and then shifting
in the new data byte.
For both of these cases, the decision to continue (to
apply a program pulse to the DS1985) is made entirely
by the bus master, since the DS1985 will not be able to
determine if the 16bit CRC calculated by the bus mas-
ter agrees with the 16bit CRC calculated by the
DS1985. If an incorrect CRC is ignored and a program
pulse is applied by the bus master, incorrect program-
ming could occur within the DS1985. Also note that the
DS1985 will always increment its internal address
counter after the receipt of the eight read time slots used
to confirm the programming of the selected EPROM
byte. The decision to continue is again made entirely by
the bus master, therefore if the EPROM data byte does
not match the supplied data byte but the master contin-
ues with the Write Memory command, incorrect pro-
gramming could occur within the DS1985. The Write
Memory command sequence can be ended at any point
by issuing a Reset Pulse.
To save time when writing more than one consecutive
byte of the DS1985s data memory it is possible to omit
reading the 16bit CRC which allows verification of data
and address before the data is copied to the EPROM
memory. This saves 16 time slots or 976 s for every
byte to be programmed. This speedprogramming
DS1985
032497 13/23
mode is accessed with the command code F3H instead
of 0FH. It follows basically the same flow chart as the
Write Memory command, but skips sending the CRC
immediately preceding the program pulse. This com-
mand should only be used if the electrical contact
between bus master and the DS1985 is firm since a
poor contact may result in corrupted data inside the
EPROM memory.
WRITE STATUS [55H]
The Write Status command is used to program the
EPROM Status data field. The bus master will follow the
command byte with a two byte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data
(D7:D0). A 16bit CRC of the command byte, address
bytes, and data byte is computed by the DS1985 and
read back by the bus master to confirm that the correct
command word, starting address, and data byte were
received.
If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is cor-
rect, a programming pulse (12 volts on the 1Wire bus
for 480 s) is issued by the bus master. Prior to program-
ming, the EPROM Status data field will appear as logical
1s. For each bit in the data byte provided by the bus
master that is set to a logical 0, the corresponding bit in
the selected byte of the EPROM Status data field will be
programmed to a logical 0 after the programming pulse
has been applied at that byte location.
After the 480 s programming pulse is applied and the
data line returns to the idle level, the bus master issues
eight read time slots to verify that the appropriate bits
have been programmed. The DS1985 responds with
the data from the selected EPROM Status address sent
least significant bit first. This byte contains the logical
AND of all bytes written to this EPROM Status Byte
address. If the EPROM Status Byte contains 1s in bit
positions where the byte issued by the master contained
0s, a Reset Pulse should be issued and the current byte
address should be programmed again. If the DS1985
EPROM Status byte contains 0s in the same bit posi-
tions as the data byte, the programming was successful
and the DS1985 will automatically increment its address
counter to select the next byte in the EPROM Status
data field. The new twobyte address will also be loaded
into the 16bit CRC generator as a starting value. The
bus master will issue the next byte of data using eight
write time slots.
As the DS1985 receives this byte of data into the
scratchpad, it also shifts the data into the CRC genera-
tor that has been preloaded with the current address
and the result is a 16bit CRC of the new data byte and
the new address. After supplying the data byte, the bus
master will read this 16bit CRC from the DS1985 with
sixteen read time slots to confirm that the address
incremented properly and the data byte was received
correctly. If the CRC is incorrect, a Reset Pulse must be
issued and the Write Status command sequence must
be restarted. If the CRC is correct, the bus master will
issue a programming pulse and the selected byte in
memory will be programmed.
Note that the initial pass through the Write Status flow
chart will generate a 16bit CRC value that is the result
of shifting the command byte into the CRC generator,
followed by the two address bytes, and finally the data
byte. Subsequent passes through the Write Status flow
chart due to the DS1985 automatically incrementing its
address counter will generate a 16bit CRC that is the
result of loading (not shifting) the new (incremented)
address into the CRC generator and then shifting in the
new data byte.
For both of these cases, the decision to continue (to
apply a program pulse to the DS1985) is made entirely
by the bus master, since the DS1985 will not be able to
determine if the 16bit CRC calculated by the bus mas-
ter agrees with the 16bit CRC calculated by the
DS1985. If an incorrect CRC is ignored and a program
pulse is applied by the bus master, incorrect program-
ming could occur within the DS1985. Also note that the
DS1985 will always increment its internal address
counter after the receipt of the eight read time slots used
to confirm the programming of the selected EPROM
byte. The decision to continue is again made entirely by
the bus master, therefore if the EPROM data byte does
not match the supplied data byte but the master contin-
ues with the Write Status command, incorrect program-
ming could occur within the DS1985. The Write Status
command sequence can be ended at any point by issu-
ing a Reset Pulse.
To save time when writing more than one consecutive
byte of the DS1985s status memory it is possible to omit
reading the 16bit CRC which allows verification of data
and address before the data is copied to the EPROM
memory. This saves 16 time slots or 976 s for every
byte to be programmed. This speedprogramming
mode is accessed with the command code F5H instead
of 55H. It follows basically the same flow chart as the
DS1985
032497 14/23
Write Status command, but skips sending the CRC
immediately preceding the program pulse. This com-
mand should only be used if the electrical contact
between bus master and the DS1985 is firm since a
poor contact may result in corrupted data inside the
EPROM status memory.
1WIRE BUS SYSTEM
The 1Wire bus is a system which has a single bus mas-
ter and one or more slaves. In all instances, the DS1985
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, transac-
tion sequence, and 1Wire signalling (signal type and
timing). A 1Wire protocol defines bus transactions in
terms of the bus state during specified time slots that are
initiated on the falling edge of sync pulses from the bus
master. For a more detailed protocol description, refer to
Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive it
at the appropriate time. To facilitate this, each device
attached to the 1Wire bus must have an open drain
connection or 3state outputs. The DS1985 is an open
drain part with an internal circuit equivalent to that
shown in Figure 6. The bus master can be the same
equivalent circuit. If a bidirectional pin is not available,
separate output and input pins can be tied together.
The bus master requires a pullup resistor at the master
end of the bus, with the bus master circuit equivalent to
the one shown in Figures 7a and 7b. The value of the
pullup resistor should be approximately 5k for short
line lengths.
A multidrop bus consists of a 1Wire bus with multiple
slaves attached. The 1Wire bus has a maximum data
rate of 16.3k bits per second. If the bus master is also
required to perform programming of the EPROM por-
tions of the DS1985, a programming supply capable of
delivering up to 10 milliamps at 12 volts for 480 s is
required. The idle state for the 1Wire bus is high. If, for
any reason, a transaction needs to be suspended, the
bus MUST be left in the idle state if the transaction is to
resume. If this does not occur and the bus is left low for
more than 120 s, one or more of the devices on the bus
may be reset.
Transaction Sequence
The sequence for accessing the DS1985 via the 1Wire
port is as follows:
Initialization
ROM Function Command
Memory Function Command
Read/Write Memory/Status
INITIALIZATION
All transactions on the 1Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by a presence pulse(s) transmitted by the slave(s).
The presence pulse lets the bus master know that the
DS1985 is on the bus and is ready to operate. For more
details, see the 1Wire Signalling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can
issue one of the four ROM function commands. All ROM
function commands are eight bits long. A list of these
commands follows (refer to flowchart in Figure 8):
Read ROM [33H]
This command allows the bus master to read the
DS1985s 8bit family code, unique 48bit serial num-
ber, and 8bit CRC. This command can be used only if
there is a single DS1985 on the bus. If more than one
slave is present on the bus, a data collision will occur
when all slaves try to transmit at the same time (open
drain will produce a wiredAND result).
DS1985
032497 15/23
DS1985 EQUIVALENT CIRCUIT Figure 6
5 A
TYP.
100
MOSFET
T
X
R
X
DATA
GROUND
BUS MASTER CIRCUIT Figure 7
BUS MASTER
V
DD
TTLEQUIVALENT
PORT PINS
5k
B) STANDARD TTL
V
DD
5k
PROGRAMMING PULSE
12V
(10 mA min.)
TO DATA CONNECTION
OF DS2505
BUS MASTER
V
DD V
DD
DS5000 OR 8051 EQUIVALENT
OPEN DRAIN
PORT PIN
R
X
T
X
A) OPEN DRAIN
12V
TO DATA CONNECTION
OF DS2505
5k
10k
10k
PGM
D
S
D
S
S
D
D S
2N7000
2N7000
2N7000
470 pF
VP0300L
OR
VP0106N3
OR
BSS110
CAPACITOR ADDED TO REDUCE
COUPLING ON DATA LINE DUE TO
PROGRAMMING SIGNAL SWITCHING
R
X
T
X
DS1985
032497 16/23
ROM FUNCTIONS FLOW CHART Figure 8
N
Y
Y
Y
DS1985 T
X
PRESENCE
PULSE
33h
READ ROM
COMMAND
55h
MATCH ROM
COMMAND
F0h
SEARCH ROM
COMMAND
CCh
SKIP ROM
COMMAND
DS1985 T
X
FAMILY
CODE
1 BYTE
BIT 0
MATCH?
BIT 0
MATCH?
BIT 1
MATCH?
BIT 1
MATCH?
BIT 63
MATCH?
BIT 63
MATCH?
DS1985 T
X

SERIAL NUMBER
6 BYTES
DS1985 T
X
CRC BYTE
N N N
Y Y Y
N N
Y
N N
Y
Y Y
DS1985 T
X
BIT 0
DS1985 T
X
BIT 0
DS1985 T
X
BIT 1
DS1985 T
X
BIT 1
DS1985 T
X
BIT 63
DS1985 T
X
BIT 63
MASTER T
X
BIT 1
MASTER T
X
BIT 0
MASTER T
X
BIT 0
MASTER T
X
BIT 1
MASTER T
X
BIT 63
MASTER T
X
BIT 63
MASTER T
X
RESET PULSE
MASTER T
X
ROM
FUNCTION COMMAND
MASTER T
X
MEMORY
FUNCTION COMMAND
(SEE FIGURE 5)
N N
DS1985
032497 17/23
Match ROM [55H]
The match ROM command, followed by a 64bit ROM
sequence, allows the bus master to address a specific
DS1985 on a multidrop bus. Only the DS1985 that
exactly matches the 64bit ROM sequence will respond
to the subsequent memory function command. All
slaves that do not match the 64bit ROM sequence will
wait for a reset pulse. This command can be used with a
single or multiple devices on the bus.
Skip ROM [CCH]
This command can save time in a single drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64bit ROM code. If
more than one slave is present on the bus and a read
command is issued following the Skip ROM command,
data collision will occur on the bus as multiple slaves
transmit simultaneously (open drain pulldowns will
produce a wiredAND result).
Search ROM [F0H]
When a system is initially brought up, the bus master
might not know the number of devices on the 1Wire
bus or their 64bit ROM codes. The search ROM com-
mand allows the bus master to use a process of elimina-
tion to identify the 64bit ROM codes of all slave devices
on the bus. The ROM search process is the repetition of
a simple 3step routine: read a bit, read the complement
of the bit, then write the desired value of that bit. The bus
master performs this simple, 3step routine on each bit
of the ROM. After one complete pass, the bus master
knows the contents of the ROM in one device. The
remaining number of devices and their ROM codes may
be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive
discussion of a ROM search, including an actual exam-
ple.
1Wire Signalling
The DS1985 requires strict protocols to insure data
integrity. The protocol consists of five types of signalling
on one line: Reset Sequence with Reset Pulse and
Presence Pulse, Write 0, Write 1, Read Data and Pro-
gram Pulse. All these signals except presence pulse are
initiated by the bus master. The initialization sequence
required to begin any communication with the DS1985
is shown in Figure 9. A reset pulse followed by a pres-
ence pulse indicates the DS1985 is ready to accept a
ROM command. The bus master transmits (TX) a reset
pulse (t
RSTL
, minimum 480 s). The bus master then
releases the line and goes into receive mode (RX). The
1Wire bus is pulled to a high state via the pullup resis-
tor. After detecting the rising edge on the data pin, the
DS1985 waits (t
PDH
, 1560 s) and then transmits the
presence pulse (t
PDL
, 60240 s).
Read/Write Time Slots
The definitions of write and read time slots are illustrated
in Figure 10. All time slots are initiated by the master
driving the data line low. The falling edge of the data line
synchronizes the DS1985 to the master by triggering a
delay circuit in the DS1985. During write time slots, the
delay circuit determines when the DS1985 will sample
the data line. For a read data time slot, if a 0 is to be
transmitted, the delay circuit determines how long the
DS1985 will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is a 1, the iButton
will leave the read data time slot unchanged.
PROGRAM PULSE
To copy data from the 8bit scratchpad to the EPROM
Data or Status Memory, a program pulse of 12 volts is
applied to the data line after the bus master has con-
firmed that the CRC for the current byte is correct. Dur-
ing programming, the bus master controls the transition
from a state where the data line is idling high via the
pullup resistor to a state where the data line is actively
driven to a programming voltage of 12 volts providing a
minimum of 10 mA of current to the DS1985. This pro-
gramming voltage (Figure 11) should be applied for 480
s, after which the bus master returns the data line to an
idle high state controlled by the pullup resistor. Note
that due to the high voltage programming requirements
for any 1Wire EPROM device, it is not possible to mul-
tidrop nonEPROM based 1Wire devices with the
DS1985 during programming. An internal diode within
the nonEPROM based 1Wire devices will attempt to
clamp the data line at approximately 8 volts and could
potentially damage these devices.
DS1985
032497 18/23
INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES Figure 9
t
RSTH
t
RSTL
t
R
V
PULLUP
V
PULLUP

MIN
V
IH

MIN
V
IL

MAX
0V
480 s < t
RSTL
< 1 *
480 s < t
RSTH
< 1 (includes recovery time)
15 s < t
PDH
< 60 s
60 s < t
PDL
< 240 s
t
PDH
t
PDL
RESISTOR
MASTER
DS1985
MASTER R
X
PRESENCE PULSE MASTER T
X
RESET PULSE
* In order not to mask interrupt signalling by other devices on the 1Wire bus, t
RSTL
+ t
R
should always be less than
960 s.
READ/WRITE TIMING DIAGRAM Figure 10
Writeone Time Slot
60 s
t
REC
t
LOW1
V
PULLUP
V
PULLUP

MIN
V
IH

MIN
V
IL

MAX
0V
60 s < t
SLOT
< 120 s
1 s < t
LOW1
< 15 s
1 s < t
REC
< 1
15 s
DS1985
SAMPLING WINDOW
t
SLOT
RESISTOR
MASTER
DS1985
>5 s
LINE TYPE LEGEND:
V
PULLUP
GND
V
PP
>5 s
480 s NORMAL 1Wire
COMMUNICATION ENDS
NORMAL 1Wire
COMMUNICATION RESUMES
Bus master active high
(12V @ 10 mA)
t
RP
t
FP
t
DP
t
DV
Resistor pullup
DS1985
032497 19/23
READ/WRITE TIMING DIAGRAM (contd) Figure 10
Writezero Time Slot
V
PULLUP
V
PULLUP

MIN
V
IH

MIN
V
IL

MAX
0V
t
SLOT
t
REC
t
LOW0
60 s < t
LOW0
< t
SLOT
< 120 s
1 s < t
REC
< 1
DS1985
SAMPLING WINDOW
60 s
15 s
Readdata Time Slot
V
PULLUP
V
PULLUP

MIN
V
IH

MIN
V
IL

MAX
0V
t
SLOT
t
REC
t
RDV
t
LOWR
60 s < t
SLOT
< 120 s
1 s < t
LOWR
< 15 s
0 < t
RELEASE
< 45 s
1 s < t
REC
< 1
t
RDV
= 15 s
t
SU
< 1 s
t
RELEASE
MASTER SAMPLING
WINDOW
RESISTOR
MASTER
DS1985
t
SU
PROGRAM PULSE TIMING DIAGRAM Figure 11
DS1985
032497 20/23
CRC GENERATION
With the DS1985 there are two different types of CRCs
(Cyclic Redundancy Checks). One CRC is a 8bit type
and is stored in the most significant byte of the 64bit
ROM. The bus master can compute a CRC value from
the first 56 bits of the 64bit ROM and compare it to the
value stored within the DS1985 to determine if the ROM
data has been received errorfree by the bus master.
The equivalent polynomial function of this CRC is: X
8
+
X
5
+ X
4
+ 1. This 8bit CRC is received in the true (non
inverted) form when reading the ROM of the DS1985. It
is computed once at the factory and lasered into the
ROM.
The other CRC is a 16bit type, generated according to
the standardized CRC16polynomial function X
16
+ X
15
+ X
2
+ 1. This CRC is used to safeguard userdefined
EPROM data when reading data memory or status
memory. It is the same type of CRC as is used with
NVRAM based iButtons to safeguard data packets of
the iButton File Structure. In contrast to the 8bit CRC,
the 16bit CRC is always returned in the complemented
(inverted) form. A CRCgenerator inside the DS1985
chip (Figure 12) will calculate a new 16bit CRC at every
situation shown in the command flow chart of Figure 5.
The DS1985 provides this CRCvalue to the bus mas-
ter to validate the transfer of command, address, and
data to and from the bus master. When reading the data
memory of the DS1985 with the Read Memory com-
mand, the 16bit CRC is only transmitted as the end of
the memory is reached. This CRC is generated by clear-
ing the CRC generator, shifting in the command, low
address, high address and every data byte starting at
the first addressed memory location and continuing until
the end of the implemented data memory is reached.
When reading the status memory with the Read Status
command, the 16bit CRC is transmitted when the end
of each 8byte page of the status memory is reached. At
the initial pass through the Read Status flow chart the
16bit CRC will be generated by clearing the CRC gen-
erator, shifting in the command byte, low address, high
address and the data bytes beginning at the first
addressed memory location and continuing until the last
byte of the addressed EPROM Status data page is
reached. Subsequent passes through the Read Status
flow chart will generate a 16bit CRC that is the result of
clearing the CRC generator and then shifting in the new
data bytes starting at the first byte of the next page of the
EPROM Status data field and continuing until the last
byte of the page is reached.
When reading the data memory of the DS1985 with the
Extended Read Memory command, there are two situa-
tions where a 16bit CRC is transmitted. One 16bit
CRC follows each Redirection Byte, another 16bit
CRC is received after the last byte of a memory data
page is read. The CRC at the end of the memory page is
always the result of clearing the CRC generator and
shifting in the data bytes beginning at the first addressed
memory location of the EPROM data page until the last
byte of this page. With the initial pass through the
Extended Read Memory flow chart the 16bit CRC
value is the result of shifting the command byte into the
cleared CRC generator, followed by the two address
bytes and the Redirection Byte. Subsequent passes
through the Extended Read Memory flow chart will gen-
erate a 16bit CRC that is the result of clearing the CRC
generator and then shifting in the Redirection Byte only.
When writing to the DS1985 (either data memory or sta-
tus memory), the bus master receives a 16bit CRC to
verify the correctness of the data transfer before apply-
ing the programming pulse. With the initial pass through
the Write Memory/Status flow chart the 16bit CRC will
be generated by clearing the CRCgenerator, shifting in
the command, address low, address high and the data
byte. Subsequent passes through the Write Memory/
Status flow chart due to the DS1985 automatically incre-
menting its address counter will generate an 16bit
CRC that is the result of loading (not shifting) the new
(incremented) address into the CRC generator and then
shifting in the new data byte.
The comparison of CRC values and decision to con-
tinue with an operation are determined entirely by the
bus master. There is no circuitry on the DS1985 that pre-
vents a command sequence from proceeding if the CRC
stored in or calculated by the DS1985 does not match
the value generated by the bus master. For more details
on generating CRC values including example imple-
mentations in both hardware and software, see the
Book of DS19xx iButton Standards.
DS1985
032497 21/23
CRC16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure 12
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
5TH
STAGE
6TH
STAGE
7TH
STAGE
8TH
STAGE
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
POLYNOMIAL = X
16
+ X
15
+ X
2
+ 1
9TH
STAGE
10TH
STAGE
11TH
STAGE
12TH
STAGE
13TH
STAGE
14TH
STAGE
15TH
STAGE
16TH
STAGE
X
9
X
10
X
11
X
12
X
13
X
14
X
15
INPUT DATA
X
16
CRC
OUTPUT
DS1985
032497 22/23
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground 0.5V to +12.0V
Operating Temperature 40C to +85C
Storage Temperature 55C to +125C
* This is a stress rating only and functional operation of the device at these or any other conditions outside
those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (V
PUP
=2.8V to 6.0V; 40C to +85C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 V
IH
2.2 V 1, 6
Logic 0 V
IL
-0.3 +0.8 V 1, 10
Output Logic Low @ 4 mA V
OL
0.4 V 1
Output Logic High V
OH
V
PUP
6.0 V 1, 2
Input Load Current I
L
5 A 3
Operating Charge Q
OP
30 nC 7, 8
Programming Voltage @ 10 mA V
PP
11.5 12.0 V
CAPACITANCE (t
A
= 25C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Data (1Wire) C
IN/OUT
800 pF 9
AC ELECTRICAL CHARACTERISTICS (V
PUP
=2.8V to 6.0V; 40C to +85C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Time Slot t
SLOT
60 120 s
Write 1 Low Time t
LOW1
1 15 s
Write 0 Low Time t
LOW0
60 120 s
Read Data Valid t
RDV
exactly 15 s
Release Time t
RELEASE
0 15 45 s
Read Data Setup t
SU
1 s 5
Recovery Time t
REC
1 s
Reset Time High t
RSTH
480 s 4
Reset Time Low t
RSTL
480 s
Presence Detect High t
PDHIGH
15 60 s
Presence Detect Low t
PDLOW
60 240 s
Delay to Program t
DP
5 s
Delay to Verify t
DV
5 s
Program Pulse Width t
PP
480 s
Program Voltage Rise Time t
RP
5 s
Program Voltage Fall Time t
FP
5 s
DS1985
032497 23/23
NOTES:
1. All voltages are referenced to ground.
2. V
PUP
= external pullup voltage.
3. Input load is to ground.
4. An additional reset or communication sequence cannot begin until the reset high time has expired.
5. Read data setup time refers to the time the host must pull the 1Wire bus low to read a bit. Data is guaranteed
to be valid within 1 s of this falling edge and will remain valid for 14 s minimum. (15 s total from falling edge
on 1Wire bus.)
6. V
IH
is a function of the external pullup resistor and V
PUP
.
7. 30 nanocoulombs per 72 time slots @ 5.0V.
8. At V
CC
=5.0V with a 5k pullup to V
CC
and a maximum time slot of 120 s.
9. Capacitance on the data pin could be 800 pF when power is first applied. If a 5k resistor is used to pull up the
data line to V
CC
, 5 s after power has been applied the parasite capacitance will not affect normal communica-
tions.
10. Under certain low voltage conditions V
ILMAX
may have to be reduced to as much as 0.5V to always guarantee
a presence pulse.