INTERRUPTS

Introduction
The word interrupt has its very literal meaning as used in our everyday life. For e.g., you are
sitting at your table and reading a book, and suddenly the phone rings. So, you leave your
table in order to attend the call. However ,just before you do so you earmark the page you
have reached. On the phone now ,suppose somebody reuests you to leave some important
message with one of your neighbours. So, once you replace the telephone receiver back on the
hook, you move out to your neighbour!s place give him the message and come back to your
table. "ou take your book a new turn to the earmarked page and continue the reading.
The p interrupt functions e#actly in the same way. $ program is being e#ecuted, similar to
your sitting and reading a book. $n interrupt is then applied to the p%the phone rings&.The
latter acknowledges the receipt of that interrupt %you pick up the phone& and then moves to
the memory location as directed by the interrupt. This is very similar to the situation you are
confronted with in the above e#ample, i.e you have to leave a message with a particular
neighbour' and in your mind you know e#actly where that particular neighbour resides. Hence
you go there to leave the message.
(n the case of the p however, that address should be specified at the time of interrupt. This is
done using a %RST& instruction , i.e )estart. The latter directs the p to the address where it
should restart its operation. This address is known as the *interrupt address vector* and it
denotes the address at which the service routine starts. $ service routine is a subroutine to
which the up *+umps* when it receives an interrupt reuest. The word *service* is used to
imply that the p services the interrupt by e#ecuting the subroutine.
,ow, when the p is interrupted, before it goes to the service routine, it automatically saves
the content of the program counter on the stack, so that the up can return to the main program
after e#ecuting the service routine. this is similar to earmarking the page you reached on
receiving the call, so that you may proceed with your reading after coming back.
The 8085 interrupt architecture.
The -.-/ up has got / interrupt inputs, namely pin 0, 1, -, 2 and 3.. These interrupts are
identified by the names ' TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR respectively. The fact
that we have more than one interrupt pins on the p chip means that we should have a special
mechanism in order to handle the interrupts from several devices that share these interrupt
lines' especially when 4 or more interrupts are activated at the same instant.
This is done by assigning priorities to these interrupt lines at the very time of designing the up
chip. For the -.-/, TRAP has the highest priority. So, if two or more of these interrupts are
activated simultaneously, the one with the higher priority is serviced first and then the other
interrupt is serviced' if it is still pending.

Masa!"e and Un#asa!"e Interrupt.
5esides having the highest priority, the TRAP is also known to be a non6maskable interrupt.
RST 7.5, RST 6.5, and RST 5.5 are maskable interrupts' 7hile INTR is neither of these.
The term maskable means that the user can enable or disable these interrupts using software.
So, when the interrupt is disabled we say that it has been masked. Then even if the interrupt
pin is activated, the p will not respond. +ust compare this with the e.g. we considered in the
previous section. (f we place the receiver of the phone on6hook, it means that we are enabling
a call to come' but if the receiver is off6hook, even if somebody wants to phone you, you ! re
not going to be interrupted and hence you wont even know if somebody wants to talk to you.
$s if you have masked the call.

The same applies to the p. However, the TRAP is unmaskable, and hence the user has no
control over this interrupt. TRAP is always enabled. For e.g. on the 89: -/;34 kit the
TRAP line is connected to the RESET key. Hence, the user has no control over this interrupt.
Trap is always enabled. For e.g on the 89: -/;34 kit the trap line is connected to the
RESET key. Hence, once the RESET key is pressed, the system will always be interrupted
irrespective of what the p is doing. This is an indication of the highest priority and
unmaskable nature of TRAP.
$i%%erent Interrupt Activities.
&i' INTR.
The -.-/ reuires some initiali<ations prior to its identifying an interrupt reuest and servicing
that interrupt. First, in the main program, we should initia"i(e the stack pointer to some
address found in the user )$9 area. Then, we should ena!"e the interrupt process by
e#ecuting the EI %=nable (nterrupt& command' and after6wards we can write the procedure we
wish to accomplish by our main program.
,ow, in order to send an interrupt to the p, we should send a >/ v %?ogic !3! & to the INTR
%pin 3.& of the p. $s soon as the p senses this signal, it co#p"etes the e)ecution of the
current instruction, saves the content o% pc on the stack, disa!"es the interrupt and
acno*"ed+es the interrupt by sending a logic !.! on the INTA %pin 33& line. This signal is then
used to latch the restart address on the data bus of the p. The restart address %or (nterrupt
address vector& contains the beginning of the subroutine service, that should be e#ecuted. This
restart address can be one of the following eight addresses @6
A ....H , ...-H , ..3.H , ..3-H , ..4.H , ..4-H , ..B.H , ..B-H C
The selection is done via some hardware arrangements.
$fter completing this routine, the p returns back to the main program. (f a further >/v signal
is sent to the INTR pin, the same seuence of events should occur. i.e the up is ready to
accept more interrupts.
&ii' RST 7.5, 6.5, 5.5
These interrupts should be enabled using the EI and SIM instruction. SIM means Set
(nterrupt 9ask. This instruction reads the content of the accumulator and enables or disables
the interrupts according to the content of the accumulator.
RST 7.5 mask
6.5 mask
5.5 mask
0 = enabled
1 = masked
Mask Set Enable
0 = bits 0 - 2 ignored
1 = bits 0 - 2 accepted
1 = RST 7.5 is reset
0 = !on"t care
7 6 5 # $ 2 1 0
R7.5 MSE 7.5 6.5 5.5 %
-This is an additional control on RST 7.5 %i.e it can be reset during a program&.
=.g. (f we wish to enable RST 7.5 , we move the data .5 into the accumulator followed by
the
the SIM instruction.
9O8 $, .5
S(9
=(
$fter the initiali<ation stage, the system is ready to accept any or a combination of these
interrupts. Furthermore, the interrupt address vector in this case is specified by the in6built
software of the system.

RST .ector /ocation
1./ ..B:
0./ ..BD
/./ ..4:
Note@ The user does not have access to the TRAP and RST 5.5 on the VMC 85/12 kit.