Voice Activated Traffic Management System Using Apr 9600 Based On Embedded System
Voice Activated Traffic Management System Using Apr 9600 Based On Embedded System
Sivasankari.S.A
Lavanya.G
Vimal Kumar.M
I.
INTRODUCTION
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B.
Reliability.
Cost effectiveness.
Low power consumption.
Efficient use of processing power.
Efficient use of memory.
Appropriate execution time.
Replace manpower.
PIC
APR 9600
Figure1
C. MICROCONTROLLER BASED SYSTEM
The M7-END pin is used as an indicator that the device
has stopped its current record or playback operation. During
recording a low going pulse indicates that all memory has
been used. During playback a low pulse indicates that the last
message has played. Microcontroller control can also be used
to link several APR9600 devices together in order to increase
the total available recording time. In this application both the
speaker and the microphone signals can be connected in
parallel. The microprocessor will then control which device
currently drives the speaker by enabling or disabling each
device using their respective CE pins. A continuous message
cannot be recorded in multiple devices however because the
transition from one device to the next will incur the delay that
is noticeable upon playback. For this reason it is
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IR SENSORS
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A. TRANSMITTER
APR
960
0
IR
TRANS
MITTE
R
Figure 2: Transmitter
The above diagram shows the basic block diagram of the
transmitter part of the voice activated traffic management
system. Here the stored voice message will be given from the
voice IC to the PIC micro controller. The PIC micro controller
is going to sense the data and gives they signal to the IR
transmitter. The IR transmitter is going to continuously
transmit the signal using IR waves.
PIC
B. RECEIVER
B. HARDWARE DESCRIPTION
PIC
16F877
VOICE
IC APR
9600
LO
UD
SPE
AK
Figure 3: Receiver
ER
The above diagram shows the basic block diagram of the
receiver part of the voice activated traffic management system.
TSOP
1738 IR
RECEIV
ER
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V. IR RECEIVER-TSOP 1738
PIC
denotes
PERIPHERAL
INTERFACE
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B. PIC- FEATURES
The features of the PIC 16F877 PIC micro controllers are
as follows.
Timer 0:8-bit timer/counter with 8-bit prescaler.
Timer1:16-bit timer/counter with prescaler, can be
incremented during sleep via external clock/crystal.
Timer 2:8-bit timer/counter with 8-bit period register,
prescaler and postscaler
Two capture, compare, PWM Modules.
Capture is 16-bit, maximum resolution is 12.5.
Compare is 16-bit, maximum resolution is 200ns.
10-bit multi-channel Analog to Digital Converter.
Synchronous serial port(SSP) with SPI(master mode) and
I2C(master/slave).
Universal
Synchronous
Asynchronous
Receiver
Transmitter(USART/SCI) with 9-bit address detection.
Brown-out detection circuitry for Brown-out Reset(BOR).
VII. ARCHITECTURE
In hardware architecture there are two types of memory as
Data memory
Program memory
Using separate buses can access these two memories.
This improves the bandwidth over Von-Newmann in
which program and data are fetched from same memory
using same bus.
CPU:
It is called as brain of the device and is responsible for
fetching the correct instruction for execution, decoding the
instruction as well as control the program memory, address
bus, data memory address bus and access to the stack.
ALU AND STATUS REGISTER:
It performs arithmetic and boolean function between the
data in the working register and any register file. ALU may
affect the values of carry and zero bits in status register.
It contains arithmetic status of ALU, RESET status and
band select bit for data memory.
PROGRAM COUNTER AND STACK:
It specifies the address to fetch for execution. The lower
byte as PCL register and PCH as higher byte.
The stack contains the written address from this branch in
program execution. It allows the combination up to 8 program
calls and interrupts to occur.
INSTRUCTION BUS AND INSTRUCTION CYCLE:
The bus is used to transfer words from program memory
to CPU. The events for an instruction to execute are: Decode,
Read, Execute and Write. There are four external clock cycles
to make one instruction cycle.
INSTRUCTION FETCH:
Due to the Harvard architecture when one instruction to
be executed the next location in program memory is fetched
and ready to be decoded as soon as currently executing
instruction is completed.
POST SCALER AND PRE SCALER:
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VIII.
B. GENERAL DESCRIPTION
The APR9600 device offers true single-chip voice
recording, non-volatile storage, and playback capability for 40
to 60 seconds. The device supports both random and
sequential access of multiple messages. Sample rates are userselectable, allowing designers to customize their design for
unique quality and storage time needs. Integrated output
amplifier, microphone amplifier, and AGC circuits greatly
simplify system design. The device is ideal for use in portable
voice recorders, toys and many other consumer and industrial
applications. APLUS integrated achieves these high levels of
storage capability by using its proprietary analog/multilevel
storage technology implemented in an advanced Flash nonvolatile memory process, where each memory cell can store
256 voltage levels. This technology enables the APR9600
device to reproduce voice signals in their natural form. It
elimates the need for encoding and compression, which often
introduce distortion.
VOICE IC-APR9600
IX. RESULTS
Single-chip, high-quality voice recording & playback
solution.
No external IC's required.
Minimum external components.
Non-volatile Flash memory technology.
No battery backup required.
User-Selectable messaging options
Random access of multiple fixed-duration
messages.
Sequential access of multiple variable-duration
messages.
User-friendly, easy-to-use operation.
Programming & development systems not
required.
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REFERENCES
[1] PCM remote control system for micro controller based
system.
[2] 8-bit CMOS flash micro controllers for PIC 16XX.
[3] Single chip voice recording and playback based on
APR9600.
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