ME 365 EXPERIMENT 2

INTRODUCTION TO DIGITAL DATA ACQUISITION

Objectives
After completing this experiment, you should be able to
Understand and explain how an analog signal is converted to a digital signal
Explain why clipping occurs and how to prevent it
Explain why aliasing occurs and how to prevent it
Determine the quantization interval for an analog to digital converter and how it is
related to the quantization error
Background
For this experiment a simple "Digital Data Acquisition System" (DDAS) has been
constructed. A simplified block diagram of the system is shown below. A more detailed
diagram is shown in Figure 2 and a circuit diagram is shown in Figure 5. A single input
is digitized with an analog to digital converter (ADC) and then converted back to an
analog signal with a digital to analog converter (D/A), with the option of passing this
output through a low pass filter.
Timing Control

Analog Input

5V

Analog Output

integers
ADC
8 bits

D/A
Zero order
8
Hold
2 -1

Optional
Low pass
filter

5V

Figure 1: Block Diagram of analog to digital back to analog system.

Note that there is no "front end" containing signal conditioning elements (filters and
amplifiers). There are two golden rules for putting signals into analog to digital
converters:
1.

make sure that the signal amplitude is as big as possible but still within the input
range of the analog to digital converter (amplify or attenuate the signal to achieve
this).

2.

make sure that the highest frequency in the signal is less than half the sample rate
of the analog to digital converter (low pass filter the signal to be sure that this is
true and make sure that the filter cut off frequency is much less than half the
sample rate).

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There is only a single input channel in this system. Multichannel systems like the one
used in the PC in the ME365 Lab, have a multiplexer in front of the analog to digital
converter. A multiplexer enables analog to digital conversion to take place on each
channel in sequence. The total sample rate for a digital system is equal to the number of
channels times the sample rate on each channel. So, if you are quoted a maximum sample
rate of 44KHz. for a two channel system, that often means you can sample at 44,000
samples per second if you use 1 channel but you can only sample at 22,000 samples per
second if you wish to use 2 channels.
Most systems would also have a sample and hold in front of the multiplexer. This piece
of hardware holds the signal constant while the analog to digital conversion is taking
place. If the analog to digital conversion is fast, relative to the speed at which the signals
are changing, the system will work acceptably without a sample and hold. If you are
doing multichannel data acquisition, then the sample and hold device becomes very
important. This is because the sample and hold device holds all signals constant while it
converts each signal in turn, and thus eliminates any time delays between samples taken
on different channels.

Figure 2: System Components

(Internal power supplies are not shown.)

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Consider now the function of each block in the above diagram.

System Clock
A clock operating at 0.5 MHz provides the timing signal needed to control system
functions. These clock signals look like square waves. When the square wave changes
from high to low it initiates command. The ADC also requires a clock which is selfcontained in the ADC chip.
System Timing and Control
This provides signals so that different parts of the system can be coordinated.
Trigger Selection Switch
Low frequency signals can be sampled at a slower rate than high frequency signals. To
reduce the amount of data which must be stored, it is desirable to keep the sample rate as
low as possible and still meet the needs for which the data is to be used. In this
experiment, data are not stored, but are converted back into an analog signal. Three
different methods for selecting the sample rate are provided.
a)

Internal Clock: The heart of the internal clock is a 555 timing chip. By changing
the time constant (a capacitor and/or resistor) the frequency can be changed. In
this setup there is a switch one can use to select one of five frequencies. Note
that, in the detailed circuit diagram shown in Figure 5, each resistor is associated
with a potentiometer that is used to make fine adjustments in the frequency.
Because the values of the resistances and capacitors can change with time and
temperature, this method of controlling the frequency is not very stable.

b)

Single Sample: In this mode of operation a pushbutton is provided so that a

sample is taken every time the button is pushed. A pulse shaper and switch
debounce circuit follows the push button. During operation of a mechanical
switch, the contacts will sometimes bounce. Since digital circuits respond very
quickly, the bounce may produce two or more samples when only one should be
executed. Also the shape of the pulse can be important, since many digital circuits
are activated by the edge of a pulse rather than by its magnitude. Thus, "clean"
pulses are required. Rise times can be very short (on the order of 5 nsec). To
observe signals like this, high frequency oscilloscopes are required (100 to 500
MHz).

c)

External Clock: There are times when it is desirable to have an external signal
determine when a sample should be taken. For example, one may want to digitize
a signal when some particular event occurs or set the sample rate to a value not

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available on the internal clock. In the latter case an function generator may be
used to obtain an adjustable sample rate.

Signal Source Switch

The signal sources that can be selected are:
a)

Internal: A ten-turn potentiometer is provided so that a voltage from +5 Volts to 5 Volts can be supplied to the ADC. The output of the potentiometer can be
switched to the output connectors for monitoring during system calibration.

b)

External: This connects the external signal to the input of the ADC.

c)

Ground: The input can be grounded to check the zero offset of the system.

Analog to Digital Converter (ADC)

An analog to digital converter (ADC) converts an incoming voltage to an
integer code that it stores in binary. The formula for conversion is:
Integer Code

Nearest Integer to

Incoming Voltage - minimum input volt age

true input span

2n

where n is the number of bits in the ADC. This ADC has 8 bits. There are 28 = 256
states: 128 for zero volts and above and 128 for negative voltages. The true input span of
this ADC is 5.00 volts to + 4.96 volts, and a single bit represents an input change of
39.1 milliVolts = 9.96 volts (input range) divided by (28 -1). This is sometimes called the
quantization interval (Q), and it is also the resolution of the ADC,
Q

true input span

2n 1

Note: the input range of this device is often quoted to be +/-5 Volts,
and the quantization interval is calculated by using:
Q

nominal input span

2n

where the nominal input range in this case is 10 Volts. You will notice that both of these
formulae give the same value for Q.

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Binary Output

1000 0010
1000 0001

-100

-60

-20
20

60

100

Input Voltage (mV)

0111 1111
0111 1110
Figure 3: Calibration curve for the ADC (resolution is 39.1 mV).

The result of an analog to digital conversion is usually stored on a computer. To relate the
integer codes back to the incoming voltages we use:
Stored Voltage

minimum input volt age of ADC

integer code
2n 1

true input span

You will notice that the Stored Voltage and the Incoming Voltage are usually not equal.
The maximum difference is +/- half the quantization interval which equals 19.5 mV in
this system. This is called the maximum quantization error and = +/-Q/2 Volts.
In summary here is a table of the characteristics of this ADC plus buffer, and the PC ADC
you will use in future Labs.
Table 1: ADC Characteristics

This Lab.

true input span

-5.00 to 4.96 V

nominal input span

minimum input voltage
number of bits (n)
quantization interval (Q)
= resolution
max. quantization error (Q/2)
max. quantization error
as a % of full input range
= 50/(28 -1)

5.00 V
-5.00 V
8
39.1mV
19.5mV
.196%

Output Latches
Holding the output constant during the convert cycle requires a latch placed between the
ADC and D/A. The latch also provides sufficient current to operate the light emitting
diodes (LEDs) which indicate the binary state of the ADC output.
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CU Digital to Analog Converter (D/A)

The D/A converts the digital output from the ADC back to an analog signal. The type of
D/A used here is called a zero order hold because it converts its integer code back to a
voltage:
Voltage

minimum output voltage

integer code
true output range of D/A
2n 1

The D/A holds this voltage constant until it is time to output the next sample. The output
of the D/A when a sinusoidal signal is fed into the box is shown in Figure 4.
D/A Output (volts)

1.00

0.00

-1.00

0.05

0.10

0.15

0.20

Time (seconds)
Figure 4: The output of the zero hold D/A when a sine wave is input into the system.

During switching, spikes may appear on the analog output. The D/A requires a reference
voltage. It is usual to low-pass filter the output of a D/A to eliminate the stepped effect
of the zero order hold. The cut-off frequency of the filter is often set to frequencies
between one-tenth of and one-third of the sample rate of the D/A. The choice is a function
of the characteristics of the filter you are using.
Op-Amp Current to Voltage Converter-Filter
The output of the D/A converter is a current which must be converted to a voltage.
Because of the high frequency switching spikes and the fact that the D/A output looks
like a staircase, it may be desirable to filter the output signal. A three position switch
allows the output to pass through single pole filters with cutoff frequencies of 5 kHz and
10 kHz or to pass through unfiltered ( ).

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Figure 5: Clock diagram for the ADC D/A Box.

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Figure 6: ADC D/A Diagram for the ADC D/A Box.

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Figure 7: Power Diagram for the ADC D/A Box.

Figure 8: Schematic of the ADC - D/A Box.

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EXPERIMENT PROCEDURE
Note the switch names will be capitalized and underlined while switch positions will just
be underlined.
1.

Plug unit in and turn POWER to On.

(This is the switch on right of front panel.)

2.

Check Power Supply Voltages

Nominal
Value

OUTPUT 1 and OUTPUT 2 on the front panel are

controlled by the OUTPUT SELECT switch. They
can be connected to the Input ,Output, or Test Lead
voltages. Connect one OUTPUT to the DMM and
set OUTPUT SELECT to Test Lead. Then touch
the probe to the three power supply voltage test
points (TP).

3.

Actual
Value

+ 15 V
- 15 V
+5V
-5V

______

GND

______

Evaluate the ADC

Set the TRIGGER SELECT to Internal, the OUTPUT SELECT to Input, and the
RATE SELECT to 20 kHz and adjust VOLTAGE CONTROL so that the ADC
state is at zero bits (i.e. so that none of the LED lights are illuminated).
Slowly increase the input voltage and observe the voltage at which the output of
the ADC changes. The most significant bit (MSB) is the left LED and the least
significant bit (LSB) is the right LED. Adjust the voltage to the point at which the
LED representing the LSB "twitches." Note that you may not be able to get all of
the lights to go on or off at the extreme ends of the range.

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Table 3: ADC Evaluation

ADC

Theoretical

Theoretical

Measured

Measured Voltage

State

No Error Voltage
(Volts)

Range of
Voltages
with this Code
(Volts)

Range of
Voltages
for this Code
(Volts)

Span
(Volts)
(+/-19.5mV?)

0000 0010
0000 0011
0000 0100

0111 1101
0111 1110
0111 1111

1000 0000
1000 0001
1000 0010

1111 1001
1111 1010
1111 1011

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Evaluate the Static Response of the D/A Converter

Set TRIGGER SELECT to Manual and INPUT SELECT to Internal.
Adjust the input voltage as indicated below and observe the input. After the input
voltage is set, push the trigger button. Then observe the output voltage by
connecting the meter to the OUTPUT. The input and output can be measured by
switching the OUTPUT SELECT between Input and Output. Note that the
limiting voltages below may not be obtainable due to power supply drift.
Table 4: Static Response

Input Voltage (V)

Output Voltage (V)

Error (mV)

5.00
3.75
2.50
1.25
0
-1.25
-2.50
-3.75
-5.00

Is the maximum error less than 1/2 LSB (least significant bit)?

5.

Dynamic Response of System

Set the function generator to a sine wave with amplitude of 10 Volts peak to peak
and a frequency above 100 Hz (REMEMBER High Z Setting). Connect the
function generator to the INPUT jack on the front panel and to channel 1 on the
oscilloscope. [NOTE: Never connect an external voltage source to OUTPUT 1 or
2 !!!]
Set
INPUT SELECT to External
TRIGGER SELECT to Internal
RATE SELECT to 20 kHz.
FILTER SELECT to OFF (bypass)
OUTPUT SELECT to OUTPUT.
Connect the OUTPUT to channel 2 on the oscilloscope.
Set RATE SELECT to 20kHz, 10 kHz, 5 kHz, 1 kHz, and .5 kHz. Observe the
OUTPUT at each setting.

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Now, with RATE SELECT at 1 kHz, set the function generator to about 1100 Hz
and manually lower the frequency of the function generator by small
(approximately 1 Hz) increments. Note that the signal you see on the scope has a
very low frequency (can be made to approach D.C.). This is because the Nyquist
criterion is not satisfied (less than 2 samples/cycle) and the output is "aliased".
Sketch the waveforms on Channels 1 and 2 of the oscilloscope below on the same
graph.

Channel 1 and Channel 2 waveform

6.

Filter Effects
Set the function generator frequency to 100 Hz.
Set RATE SELECT to 20 kHz and observe the OUTPUT with the FILTER
SELECT set at the 10 kHz cutoff.
Repeat with the FILTER SELECT set at the 5 kHz cutoff.
Observe the OUTPUT at various sample rate and filter cutoff frequency
combinations. Note that at the lowest filter setting the OUTPUT will be attenuated
and there will be a phase shift.
Now change the function generator OUTPUT to a square wave at 1 kHz and
observe the OUTPUT for the various combinations.

7.

Small Amplitude Effects

Set the function generator back to a 1 kHz sine wave and adjust its amplitude to
0.05 Volts peak to peak (0.04 Volts RMS).
How well does the OUTPUT represent the INPUT under the best selection of
sample rate and filter setting?
Reduce the input voltage further to about 0.02 Volts RMS.
What is the main problem?
Illustrate your results with a sketch.

8.

Demonstration of the effects of Analog to Digital and Digital to Analog

Conversion using CD player.

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