Institut f

ur Integrierte Systeme
Integrated Systems Laboratory

Analog Integrated Circuits

Exercise 2: Introduction to Cadence
Philipp Schonle J64.2, Luca Bettini J93, Rene Blattmann J93
Hand out: 18.10.2013
Hand in: 01.11.2013

The exercise takes place in room ETZ D96. The exercise starts at 13:15 and ends at 15:00.

1 Introduction
Analog integrated circuit design is usually done by paper and pencil with very simple models in a
first stage. In a second stage, the behavior of the circuit is verified by a simulation software tool with
more precise models and the circuit is then modified based on these results. However, the results from
the simulation software should more or less agree with the considerations made in the first stage, when
all components have been dimensioned. Currently, the most sophisticated and wide-spread software
package for the analysis and synthesis of analog and digital integrated circuits is the Design Framework
II (DFII) of Cadence Inc., which is referred to as Cadence in the following. The purpose of this exercise
is to become familiar with the schematic entry and simulation environment of Cadence. You are going
to perform the most important analyses on the basis of simple analog integrated circuits. Note that the
material conveyed in this exercise forms the basis for all subsequent labs and is a prerequisite for their
successful completion. We therefore suggest that you keep this exercise within reach in the future labs.

2 Getting Started
Open a terminal session and enter the following commands:
cd
mkdir uebung2
cd uebung2
icdesign ams-hk4.10 &
The last command starts after approving the creation of a new cockpit structure the DZ-cockpit1
(Fig. 1) for different processes of the Austrian chip foundry AMS (Austria Micro Systems2 ). We will
1
2

DZ stands for Mikroelektronik Designzentrum: www.dz.ee.ethz.ch

see http://www.ams.co.at

use the C35B4M3 0.35 m 2P3M CMOS process throughout the AIC labs. The nominal supply voltage
for this process is 3.3 V. The process specific parameters for Cadence are provided by the chip foundry
as design kits. However, AMS calls its design kit AMS Hit Kit.
Click on Design Framework II to start Cadence DFII.

Figure 1: DZ cockpit window.

When starting Cadence, multiple windows appear on the screen. Ignore and close the Whats New?
windows. Fig. 2 shows the Command Interpreter Window (CIW) of Cadence. In this window, tools
and functions may be invoked either through the menu or by typing a SKILL command in the command
line. SKILL is a Cadence proprietary dialect of the programming language LISP. Note that the tools
display important messages in the area above the command line! Therefore it is a good idea to enlarge
this window a litte bit.

Figure 2: Command Interpreter Window (CIW).

The window of Fig. 3 entitled Library Manager is Cadences file manager that manages libraries
and cells. The Library Manager may be invoked from the Command Interpreter Window by clicking
Tools.Library Manager 3 .
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Command1.Command2 means you should click Command2 in the menu Command1.

Figure 3: Library Manager.

3 The Library and Cell Hierarchy

Have a look at Fig. 3: the column to the far right shows the different views of the transistor nmos4.
At the moment only the schematic view, needed to draw a circuit representation, and maybe the layout
view with the physical layout of the transistor are relevant to us.
Generally, circuits may become large and complex. Therefore, it makes sense to sum up self-contained
parts of a circuit as blocks - especially if these blocks are to be used more than once in the overall circuit.
A hierarchy level above, only a graphical representation of the block is necessary, which is called the
symbol view. This concept allows to structure circuits in a hierarchical way.
Different cells may be arranged in categories for the sake of more clarity. The cells that have not been
assigned to a certain category appear in the category Uncategorized. The category display may be
enabled and disabled with the tick box Show Categories in the upper left corner of the Library Manager.
Note that a cell may belong to more than one category. Therefore, the category does not constitute a
hierarchical structure.
Cells and categories are assigned to a library. At the moment, the libraries analogLib and PRIMLIB
are relevant to us. PRIMLIB is an AMS library and contains the components (MOSFETs, resistors,
capacitors, etc.) of the selected technology.

Generate your own library for this exercise by clicking File.New.Library in the Library Manager.
Enter MyLibrary for Name and click OK. A technology file has to be assigned to your library. Accept the default Attach to an existing technology library and select TECH C35B4
as Technology Library in the subsequent dialog box. The generated library MyLibrary should
now appear in the Library Manager.
Now generate a cell called nmos dc and its schematic view. To do this, first select MyLibrary in
the Library Manager. Then click File.New.Cell View and choose nmos dc for Cell Name,
schematic for both, View Name and Type, and Schematics XL for Application. After clicking
OK the schematic entry window pops up and we are ready to assemble our circuit.

4 Schematic Entry in Virtuoso Composer

The composer serves as graphical schematic entry tool. This section introduces the most relevant commands by means of a simple example.

Figure 4: Composer Window.

If you followed the tutorial correctly so far, then you should have the window displayed in Fig. 4 on your
screen now. Buttons for frequently used commands can be found in the toolbars. Moving the mouse
cursor over a button allows you to get a short help text such as Check and Save for the third button from
the left.
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Further help for the active command is provided in the status line of the composer window, where at
the moment HIT-Kit: ams4.10 is displayed. By pressing ESC you can terminate the active command
before completion4 .

Figure 5: Schematic for the NMOS DC characteristics.

The schematic of your first circuit is depicted in Fig. 5. At first, place the transistor by clicking Create
Instance i 5 . In the dialog box, you can specify the wanted component either by filling in the fields
Library, Cell, and View by hand, or by using the browser. Now press Browse and look for nmos4 in
the library PRIMLIB and select the symbol view.
Move the mouse cursor over the composer window. The mouse cursor now shows the symbol of the
NMOS transistor. Before you place the transistor, enter 0.7u for Width and 0.35u for Length in
the Add Instance window. Use the same value for WidthStripe as for Width. Note that no
space is allowed between the value and the factor u! Before you place the component it may be rotated
in 90 steps by pressing r . You may now finally place the transistor with the left mouse button.
In order to edit the parameters select the component with the left mouse button. Then either click on the
Property q button in the toolbar or choose Edit.Properties.Objects from the menu. As an
alternative the Property Editor (usually on the left) can be used. For working efficiently with Cadence
it pays to memorize the shortcuts of the most often used commands. The shortcuts are shown in the
pertaining menu entries, e.g. [Objects...
q]. Have a look at the menus Edit and Create to
get an overview of the most important commands for drawing a circuit!
From the analogLib, place the ground connection gnd and a voltage source vdc for both the gate and
drain voltage according to Fig. 5. Use the symbol view here as well. For both voltage sources enter 3
V for the DC voltage.
Note: the gnd connection is absolutely needed by the simulator in order to define a reference
potential and therefore has to be included in each circuit!!!
The ports of the components may be connected with the command Create.Wire (narrow) w .
If this command is active, the composer suggests a connection with the symbol near the mouse cursor.
Pressing s (for snap) accepts the proposal and allows to connect the various components in a convenient
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Since uncompleted commands are stacked a stack overflow may occur. Press ESC a couple of times in such situations possibly in different windows - in order to clear the stack. Nest Limit and the number of Undos may be set in the Command
Interpreter Window in Options.User Preferences.
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Shortcut Keys are given in frames. An uppercase letter X denote shift+X

manner.
Usually a net is assigned a name automatically, e.g. net2. With the button Create Wire Name l
you may assign names explicitly, e.g. vds and vgs as in Fig. 5. Enter the desired label in the Names
field of the corresponding dialog box and position the label on the wire you would like to name.
Like wires, components are designated automatically as well, e.g. V0 in case of a voltage source. To
change the name select the corresponding component and press q . You may now change the field
Instance Name accordingly.
Now change all the net and instance names in your circuit according to Fig. 5 and save your design with
File.Check and Save X .

5 Simulation with Analog Design Environment

The circuit may now be simulated directly from the Composer Window. There are different kinds of
simulations. One of them is the DC analysis. The DC analysis returns the DC operating points of the
circuit components. Additionally, a parameter such as the voltage of a voltage source or the temperature
may be varied to determine the DC operating points for each condition.
The transient analysis determines the behavior of the circuit in the time domain, e.g. the step response
for a low pass filter.
The AC analysis linearizes the circuit around the specified operating point and then determines the
behavior of the circuit in the frequency domain in steady state for a sinusoidal source. It can e.g. return
the amplitude and phase response of an amplifier. The AC analysis is a small signal analysis which
means that the nonlinear components are linearized in their bias points first. Only then is the actual
frequency analysis performed by the simulator.
Besides the mentioned analyses there are many others. However, these are not in our interest at the
moment.
Now start the simulation tool Analog Design Environment (ADE) from the Composer with the command
Launch.ADE L. If dialogs appear asking for permission to check for a (G)XL licence, click O.K.. The
window depicted in Fig. 6 will appear on your screen.
The menu entry Setup.Simulator/Directory/Host allows you to select the simulator (we are
going to use spectre) and to specify the directory in Project Directory where the simulation
data should be written to. Accept the defaults here.
The file path to the simulation models may be specified with Setup.Model Libraries. Again,
accept the defaults.

5.1 The DC Analysis

Select Analyses.Choose in the Analog Environment and click on dc in the following dialog box.
Make sure to tick Save DC Operation Point and click OK. Now run the simulation by clicking Simulation.Netlist and Run. First, the netlist is generated which is then passed to the
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Figure 6: Analog Design Environment.

simulator along with the model parameters and simulation settings. Finally, the simulator is invoked.
After the simulation has completed you can have the DC bias values printed by first clicking
Results.Print.DC Operating Points and then selecting the NMOS transistor symbol.
5.1.1

The DC Sweep

Now we want to simulate the steady state behavior of the NMOS transistor when the drain source
voltage is rising from 0 to 3.6 V. Select Analyses.Choose dc Component Parameter
Select Component and select the voltage source V1 in the composer (see Fig. 7). A dialog box
with a selection of parameters pops up. Choose DC voltage and click OK. For the Sweep Range
use 0-3.6 and proceed with OK. With these settings, a DC analysis is performed for each relevant value
of VDS within the given range. Before you start the simulation, you have to define which voltages
and currents should be saved. Choose Outputs.Save All in the Analog Design Environment and
make sure that allpub is ticked for Select signals to output (save) and that all is
ticked for Select device currents (currents). Set the subcircuit probe level
to 1. Proceed with OK and start the simulation.
After the simulation has completed, open the window shown in Fig. 8 with Tools.Calculator.
Have a look at the second toolbar from the top (vt, vf, . . . ). The first letter stands for voltage and the
second one denotes the type of analysis: t for transient analysis, f for frequency analysis, s for DC
sweep, and dc for DC analysis. The second row of the toolbar contains the same analyses pertaining to
currents.
In order to plot the drain current IDS as a function of the drain source voltage VDS , click is in the
calculator and then on the drain port (marked by a red square) of the transistor in the Composer Window.
Now the display line of the calculator reads IS("/M1/D"). If so, use the Tools.Plot function to
get the characteristic shown on the left of Fig. 9.
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Figure 7: DC Sweep.

Instead of using the calculator you may plot the simulation results directly from the Analog Environment
with help of the command Results.Direct Plot.DC and by selecting the port or net of interest
with the mouse in the schematic. Press ESC to terminate the selection and to plot the curve.
A third possibility is to use the results browser (Fig. 9) which you start from the ADE with Tools.Results
Browswer. It gives direct access to all saved signals, operating points et.c. Click on the dc folder to
show the saved results of the DC (sweep) analysis. A double-click on a signal directly plots it in the
window on the right. More options can be accessed with the right mouse button, such as using the
selected signal in the calculator or exporting the simulation results as a .csv file.

Figure 8: Calculator.

Figure 9: Results Browser and output characteristic of the NMOS transistor.

5.1.2

The Parametric Analysis

The parametric analysis allows you to simulate the IDS (VDS ) characteristic for various VGS in a single
pass. For this, replace the DC voltage value of the source V0 with the variable vgs and save the changes
with File.Check and Save. Now click Variables.Copy from Cellview in the ADE in
order to import your variable. The command Tools.Parametric Analysis brings the window
depicted in Fig. 10 to your screen.

Figure 10: Input window for the parametric analysis.

Type or select vgs for Variable, set the Range Type to From/To and choose a range of 1 to
3.5. Set Step Mode to Linear Steps and enter 0.5 for Step Size. Make sure that Sweep? is
checked. Now start the simulation with Analysis.Start Selected.
The plot may be produced the same ways as for the DC sweep analysis, e.g. choose is in the calculator,
click on the drain port, and hit Tools.Plot afterwards. This should result in the IDS (VDS , VGS )
characteristic of Fig. 11. However, if you have kept the plot window from the DC sweep open, the new
graphs will be added without removing the old one. You can hide a graph with the eye button or delete
it by first selecting and then pressing Del .

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Figure 11: IDS (VDS , VGS ) characteristic.

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Problems:
DC Analysis of a MOSFET
1.

(a) The range where the output characteristic is almost flat may be interpreted as a finite outputresistance source controlled by its VGS voltage. What kind of source is this?
(b) What is the value of this resistance

dVDS
dIDS

at VGS = 3 V and VDS = 3 V?

Use the following two procedures to determine the resistance:

i. Determine the operating points of the transistor. Use the command Results.Print.DC
Operating Points and click on the transistor in the composer. Determine the
wanted resistance with the help of the parameter gds.
ii. Calculate the resistance from the slope of the corresponding characteristic. Select
Special Functions in the Function Panel and click on deriv (for derivation). The display line of the calculator now reads deriv(IS("/M1/D")). Pressing
Tools.Plot (without deleting the former plot) results in the the wanted set of curves
that are shown together with the IDS (VDS , VGS ) characteristics in the same plot. You
can rearange the curves by drag & drop to separate plots. A new set of axis can be created with the commands File.New Window and File.New Subwindow. Zoom
in on the area around VDS = 3 V:
Zoom In: Draw a rectangle with the right mouse button pressed
X-Axis Zoom: Shift + mouse wheel
Y-Axis Zoom: Ctrl + mouse wheel
Fit: f
Set a marker to read out the slope at a certain point. Use the dialog Marker.Create
Marker or:
Horizontal Marker: h
Vertical Marker: v
Point Marker: m
A marker can be deleted by selecting it and then press Del .
2. In the following three problems you are going to simulate the output characteristic of various
transistor channel lengths and widths. We are going to use variables for these parameters so we
do not have to adjust the quantities in the composer each time.
First close the Plot Window and the parametric analysis window. Select the transistor in the composer and open the Edit Object Property window by pressing q. If you get the wrong
window here, press ESC and try again. Now enter the variable w for Width and Width Stripe
and use the variable l for Length. Make sure that the factor u does not stay there undeliberately.
Click OK and File.Check and Save X .
Remember that you have to copy the new variables from the composer with Variables.Copy
From Cellview into the ADE. The variables may now be edited with. Choose vgs=3,
w=0.7u, l=0.35u and start the simulation with Simulation.Netlist and Run. Plot
the IDS (VDS ) characteristic. Now double the channel width W and simulate again!
(a) How did the current IDS change in response to the new channel width W?
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3. Now also double the channel length L! Compare the output characteristic for W = 0.7 m,
L = 0.35 m to the characteristic for W = 1.4 m, L = 0.7 m!
(a) How did the controlled source change?
(b) How did its resistance change?
4. Set W = 50 m, L = 2 m and repeat the parametric analysis from the beginning of this section.
Choose a range of 0.8-1.8 V for the variable vgs and set the Step Control to Linear. Enter
11 for Total Steps and start the simulation with Analysis.Start Selected.
After you have plotted the characteristics, print the curves to a file and send it through the VPP
homepage to the prefered printer.
Close the Analog Environment with Session.Quit. A dialog box will ask you whether you
want to save the current state. Answer Yes. Next, options on what to save are presented. Accept the default by pressing OK. You could also save the current state without quitting Analog
Environment with Session.Save State. At a later point in time, you may load the simulation settings again with Session.Load State. Now close all windows except the Command
Interpreter Window and the Library Manager.
Simple Amplifier Circuit
A simple single-stage amplifier is to be built with a n-channel MOSFET as shown in Fig. 12. VDD is 3.3
V and the n-channel MOSFET has the following dimensions: W = 50 m, L = 2 m. The MOSFET
should operate at a gate source bias of VGS = 1.4 V and a drain source bias of VDS = 2.3 V.

VDD

VIN

VOUT

Figure 12: Simple NMOS amplifier.

1. Mark the operating point on your characteristics sheet obtained before!

2. Draw the load line! How large is the load resistance?
3. Create a new cell amplifier in your library MyLibrary. Open the schematic view for this
cell and draw the amplifier circuit of Fig. 12 in the same manner as in section 4. Use the cell res
of analogLib to model the resistor R.

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Simulate the output voltage VOUT as a function of VIN with the help of the DC sweep analysis.
Choose the range 0-3.3 V for VIN . After the simulation, click on vs in the calculator window and
then on the net representing VOUT in the composer.
(a) Based upon your VOUT = f (VIN ) plot, specify the range of VIN in which the circuit works
as an amplifier!
(b) Is this range also visible on your sheet with the load line? Mark the range on this sheet!
(c) Determine the gain

dVOUT
dVIN

in a couple of operating points with help of VOUT = f (VIN ) plot!

4. As you may see, the gain is fairly small.

(a) How must the load resistance or the load line be changed in order to achieve a higher gain?
(b) Is it reasonable to replace the load R with an ideal current source? Draw the load line of an
ideal current source in a qualitative manner!
Now quit the Analog Environment with Session.Quit and close all windows except the Command
Interpreter Window and the Library Manager.

5.2 The AC Analysis

In this section, you are going to simulate the amplitude and phase response of a RLC network.
Create a new schematic cell view named RLC net in your library MyLibrary and draw the circuit
shown in Fig. 13 using the components vdc, ind, cap, res and gnd of the analogLib library.

Figure 13: RLC network.

Select the voltage source and press q (or use the Property Editor subwindow). Set AC Magnitude to
1 V. Save the design and start the Analog Environment. Click Analyses.Choose and select ac. For
Sweep Range choose 1K for the start frequency and 1G for the stop frequency. Pick Logarithmic
as Sweep Type and set the number of points per decade to 100. Proceed with OK and start the
simulation.
In order to plot the amplitude response of the circuit, press the vf button in the calculator and select the
VOUT net in the composer. Now click onto dB20 (is found in the Modifier functions set) and then
Tools.Plot. Repeat the procedure for the phase response but use phase instead of db20 this time.
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5.3 The Transient Analysis

Now we would like to simulate the step response for the RLC network. Replace the voltage source V0
with the cell vpulse from the library analogLib and set the following values:
Voltage1
Voltage2
Delay time
Rise time
Fall time
Pulse Width
Period

:=0V
:=5V
:=500ns
:=20ns
:=20ns
:=5us
:=10us

Save the design and click Analyses.Choose in the Analog Environment. Now pick the tran
analysis and enter 9u for Stop Time. Make sure that Enabled in the lower left corner of the window
is ticked and proceed with OK. Delete the contents of the Waveform Window and start the simulation.
Now plot the input voltage by pressing vt in the calculator and clicking on the net V IN in the composer.
Press Tools.Plot afterwards. Use the same procedure to plot the output voltage V OUT. Measure
the peak of over- and undershoot with help of point markers m .
Now conduct the same analysis with the initial conditions VC(t=0) = 5 V and IL(t=0) = 400 mA. For
this, select the capacitor and press q (or use the Property Editor subwindow). You may now specify
the initial voltage in the field Initial condition. The same procedure applies to the inductor.
Save the design and start the simulation. Use the command File.Reload.Current Subwindow
Ctrl + r of the Waveform Window to refresh the input and output voltage plots. Again, measure the
peak of over- and undershoot.
This completes the introduction to Cadence. You may now close the Analog Environment and quit
Cadence with the command File.Exit of the Command Interpreter Window.

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