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ARM
is a family of instruction
Variants
set architectures for computer
Contents
Featured content
processors
based on a reduced instruction set computing
Current events
(RISC) architecture developed by British company ARM
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Holdings.
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A RISC-based computer design approach means ARM

Interaction require significantly fewer transistors than typical
processors
Help
CISC x86 processors in most personal computers. This
About Wikipedia
approach
reduces
Community
portal costs, heat and power use. Such reductions
changes
areRecent
desirable
traits for light, portable, battery-powered devices
Contact page
including
smartphones, laptops, tablet and notepad
Tools
computers,
and other embedded systems. A simpler design
What links here
facilitates more efficient multi-core CPUs and higher core
Related changes
counts
atfile
lower cost, providing improved energy efficiency for
Upload
[3][4][5]
servers.
Special pages
Permanent link

ARM
Holdings develops the instruction set and architecture for
Page information
ARM-based
products, but does not manufacture products. The
Wikidata item
Cite this periodically
page
company
releases updates to its cores. Current
cores
Print/export
from ARM Holdings support a 32-bit address space and
Create
a book
32-bit
arithmetic;
the ARMv8-A architecture, announced in
Download as PDF
[6]
October 2011, adds support for a 64-bit address space and
Printable version
64-bit arithmetic. Instructions for ARM Holdings' cores have
Languages
32bits
wide fixed-length instructions, but later versions of the

architecture
also support a variable-length instruction set that
()
provides both 32 and 16bits wide instructions for improved
Catal
code
density. Some cores can also provide hardware execution
etina
Dansk bytecodes.
of Java
Deutsch

ARM
Holdings licenses the chip designs and the ARM
Eesti
instruction
set architectures to third parties, who design their
ownEspaol
products that implement one of those architectures

including systems-on-chips (SoC) that incorporate memory,

Franais
interfaces,
radios, etc. Currently, the widely used Cortex cores,

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Go

Designer

ARM Holdings

Bits

32-bit, 64-bit

Introduced

1985

Design

RISC

Type

Register-Register

Branching

Condition code

Open

Proprietary

64/32-bit architecture
Introduced 2011
Version

ARMv8-A, ARMv8.1-A

Encoding

AArch64/A64 and AArch32/A32

use 32-bit instructions, T32
(Thumb-2) uses mixed 16- and
32-bit instructions. ARMv7 userspace compatibility[1]

Endianness Bi (little as default)

Extensions All mandatory: Thumb-2, NEON,
Jazelle, VFPv4-D16, VFPv4
Registers
General
purpose

31x64-bit integer registers[1]

Floating
point

32128-bit registers[1] for

scalar 32- and 64-bit FP or SIMD
FP or integer; or cryptography

plus PC and SP, ELR, SPSR for

exception levels

ARM architecture - Wikipedia, the free encyclopedia

Bahasa
Indonesia
older
"classic"
cores, and specialized SecurCore cores variants
Italiano
are available for each of these to include or exclude optional

capabilities. Companies that make chips that implement an

ARM
architecture include Apple, AppliedMicro, Atmel,
Latvieu
Magyar
Broadcom,
Cypress Semiconductor, Freescale Semiconductor,
Nvidia, NXP, Qualcomm, Samsung Electronics, ST
Nederlands
Microelectronics and Texas Instruments. Qualcomm introduced

newNorsk
three-layer
3D chip stacking in their 2014-15 ARM SoCs
bokml
Polski
such
as in their first 20nm 64-bit octa-core.[7]
Portugus

Globally
ARM is the most widely used instruction set
architecture
in terms of quantity produced.[8][9][10][11][12] The
Shqip
English
lowSimple
power
consumption of ARM processors has made them
Slovenina
very popular: over 50 billion ARM processors have been
Slovenina
produced
of 2014, of which 10 billion were produced in
/ as
srpski
[13]
Srpskohrvatski
/
2013
and "ARM-based
chips are found in nearly 60 percent

of the
worlds mobile devices". The ARM architecture (32-bit)
Suomi
is the
most widely used architecture in mobile devices, and
Svenska
Trke
most
popular 32-bit one in embedded systems. [14] In 2005,

about
98% of all mobile phones sold used at least one ARM
Ting Vit
[15] According to ARM Holdings, in 2010 alone,
processor.

producers ofEdit
chips
linksbased on ARM architectures reported
shipments of 6.1billion ARM-based processors, representing
95% of smartphones, 35% of digital televisions and set-top
boxes and 10% of mobile computers.
Contents [hide]
1 History
1.1 Acorn RISC Machine: ARM2
1.2 Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale
2 Licensing
2.1 Core licence
2.2 Architectural licence
3 Cores
3.1 Example applications of ARM cores
4 32-bit architecture
4.1 CPU modes
4.2 Instruction set
4.2.1 Arithmetic instructions
4.2.2 Registers
4.2.3 Conditional execution

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32-bit architectures (Cortex)

Version

ARMv8-R, ARMv7-A, ARMv7-R,

ARMv7E-M, ARMv7-M, ARMv6-M

Encoding

32-bit except Thumb-2

extensions use mixed 16- and
32-bit instructions.

Endianness Bi (little as default)

Extensions Thumb-2 (mandatory since
ARMv7), NEON, Jazelle, FPv4-SP
Registers
General
purpose

16x32-bit integer registers

including PC and SP

Floating
point

Up to 3264-bit registers, [2]

SIMD/floating-point (optional)

32-bit architectures (legacy)

Version

ARMv6, ARMv5, ARMv4T, ARMv3,

ARMv2

Encoding

32-bit except Thumb extension

uses mixed 16- and 32-bit
instructions.

Endianness Bi (little as default) in ARMv3 and

above
Extensions Thumb, Jazelle
Registers
General
purpose

16x32-bit integer registers

including PC (26-bit addressing in
older) and SP

ARM architecture - Wikipedia, the free encyclopedia

4.2.4 Other features

4.2.5 Pipelines and other implementation issues
4.2.6 Coprocessors
4.3 Debugging
4.4 DSP enhancement instructions
4.5 SIMD extensions for multimedia
4.6 Jazelle
4.7 Thumb
4.8 Thumb-2
4.9 Thumb Execution Environment (ThumbEE)
4.10 Floating-point (VFP)
4.11 Advanced SIMD (NEON)
4.12 Security extensions (TrustZone)
4.13 No-execute page protection
4.14 Large Physical Address Extension
4.15 ARMv8-R
5 64/32-bit architecture
5.1 ARMv8-A
5.1.1 ARMv8.1-A
5.1.2 AArch64 features
6 Operating system support
6.1 32-bit operating systems
6.2 64-bit operating systems
7 See also
8 Further reading
9 External links
10 References

History

[edit]

The British computer manufacturer Acorn Computers first

developed ARM (Acorn RISC Machines, later called Advanced
RISC Machines) in the 1980s to use in its personal
computers. Its first ARM-based products were coprocessor
modules for the BBC Micro series of computers. After the
successful BBC Micro computer, Acorn Computers considered
how to move on from the relatively simple MOS Technology
6502 processor to address business markets like the one that
was soon dominated by the IBM PC, launched in 1981. The

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ARM architecture - Wikipedia, the free encyclopedia

Acorn Business Computer (ABC) plan required that a number

of second processors be made to work with the BBC Micro
platform, but processors such as the Motorola 68000 and
National Semiconductor 32016 were considered unsuitable,
and the 6502 was not powerful enough for a graphics based
user interface. [16]
After testing all available processors and finding them
Microprocessor-based system on a chip
lacking, Acorn decided it needed a new architecture. Inspired
by white papers on the Berkeley RISC project, Acorn
considered designing its own processor.[17] A visit to the Western
Design Center in Phoenix, where the 6502 was being updated by what
was effectively a single-person company, showed Acorn engineers Steve
Furber and Sophie Wilson they did not need massive resources and
state-of-the-art research and development facilities. [18]
Wilson developed the instruction set, writing a simulation of the
The ARM1 second processor for
processor in BBC BASIC that ran on a BBC Micro with a second 6502
the BBC Micro
processor. This convinced Acorn engineers they were on the right track.
Wilson approached Acorn's CEO, Hermann Hauser, and requested more
resources. Once he had approval, he assembled a small team to implement Wilson's model in hardware.

Acorn RISC Machine: ARM2

[edit]

The official Acorn RISC Machine project started in October 1983. They chose VLSI Technology as the silicon
partner , as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design.
They implemented it with a similar efficiency ethos as the 6502.[19] A key design goal was achieving lowlatency input/output (interrupt) handling like the 6502. The 6502's memory access architecture had let
developers produce fast machines without costly direct memory access hardware.
The first samples of ARM silicon worked properly when first received and tested on 26 April 1985.[3]
The first ARM application was as a second processor for the BBC Micro, where it helped in developing
simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the CAD
software used in ARM2 development. Wilson subsequently rewrote BBC BASIC in ARM assembly language.

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The in-depth knowledge gained from designing the instruction set enabled the code to be very dense,
making ARM BBC BASIC an extremely good test for any ARM emulator. The original aim of a principally
ARM-based computer was achieved in 1987 with the release of the Acorn Archimedes.[20] In 1992, Acorn
once more won the Queen's Award for Technology for the ARM.
The ARM2 featured a 32-bit data bus, 26-bit address space and 2732-bit registers. Eightbits from the
program counter register were available for other purposes; the top sixbits (available because of the 26-bit
address space), served as status flags, and the bottom twobits (available because the program counter
was always word-aligned), were used for setting modes. The address bus was extended to 32bits in the
ARM6, but program code still had to lie within the first 64MB of memory in 26-bit compatibility mode, due
to the reserved bits for the status flags.[21] The ARM2 had a transistor count of just 30,000, compared to
Motorola's six-year-older 68000 model with around 40,000. [22] Much of this simplicity came from the lack of
microcode (which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the
day) not including any cache. This simplicity enabled low power consumption, yet better performance than
the Intel 80286. A successor, ARM3, was produced with a 4KB cache, which further improved
performance.[23]

Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale

[edit]

In the late 1980s Apple Computer and VLSI Technology started working
with Acorn on newer versions of the ARM core. In 1990, Acorn spun off
the design team into a new company named Acorn RISC Machines Ltd.,
which became ARM Ltd when its parent company, ARM Holdings plc,
floated on the London Stock Exchange and NASDAQ in 1998.[24]
The new Apple-ARM work would eventually evolve into the ARM6, first
released in early 1992. Apple used the ARM6-based ARM610 as the
basis for their Apple Newton PDA. In 1994, Acorn used the ARM610 as
the main central processing unit (CPU) in their RiscPC computers. DEC
licensed the ARM6 architecture and produced the StrongARM. At
Die of an ARM610
microprocessor
233MHz, this CPU drew only one watt (newer versions draw far less).
This work was later passed to Intel as a part of a lawsuit settlement,
and Intel took the opportunity to supplement their i960 line with the
StrongARM. Intel later developed its own high performance implementation named XScale, which it has
since sold to Marvell. Transistor count of the ARM core remained essentially the same size throughout these
changes; ARM2 had 30,000transistors, while ARM6 grew only to 35,000. [citation needed ]

Licensing

[edit]

See also: ARM Holdings Licensees

Core licence

[edit]

ARM Holdings' primary business is selling IP cores, which licensees use

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ARM architecture - Wikipedia, the free encyclopedia

to create microcontrollers (MCUs) and CPUs based on those cores. The

original design manufacturer combines the ARM core with other parts to
produce a complete CPU, typically one that can be built in existing
semiconductor fabs at low cost and still deliver substantial performance.
The most successful implementation has been the ARM7TDMI with
hundreds of millions sold. Atmel has been a precursor design center in
the ARM7TDMI-based embedded system.
The ARM architectures used in smartphones, PDAs and other mobile
devices range from ARMv5, used in low-end devices, through ARMv6, to
ARMv7 in current high-end devices. ARMv7 includes a hardware floatingpoint unit (FPU), with improved speed compared to software-based
floating-point.

Die of a STM32F103VGT6 ARM

Cortex-M3 microcontroller with
1megabyte flash memory by
STMicroelectronics

In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition
with netbooks based on Intel Atom.[25] According to analyst firm IHS iSuppli, by 2015, ARM ICs may be in
23% of all laptops.[26]
ARM Holdings offers a variety of licensing terms, varying in cost and deliverables. ARM Holdings provides to
all licensees an integratable hardware description of the ARM core as well as complete software
development toolset (compiler, debugger, software development kit) and the right to sell manufactured
silicon containing the ARM CPU.
SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's
Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's
OMAP products, Samsung's Hummingbird and Exynos products, Apple's A4, A5, and A5X, and Freescale's
i.MX.
Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested
in acquiring a ready-to-manufacture verified IP core. For these customers, ARM Holdings delivers a gate
netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to
aid design integration and verification. More ambitious customers, including integrated device manufacturers
(IDM) and foundry operators, choose to acquire the processor IP in synthesizable RTL (Verilog) form. With
the synthesizable RTL, the customer has the ability to perform architectural level optimisations and
extensions. This allows the designer to achieve exotic design goals not otherwise possible with an
unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While
ARM Holdings does not grant the licensee the right to resell the ARM architecture itself, licensees may
freely sell manufactured product such as chip devices, evaluation boards and complete systems. Merchant
foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they
generally hold the right to re-manufacture ARM cores for other customers.
ARM Holdings prices its IP based on perceived value. Lower performing ARM cores typically have lower
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ARM architecture - Wikipedia, the free encyclopedia

licence costs than higher performing cores. In implementation terms, a synthesizable core costs more than
a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an ARM licence,
such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the
ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of
ARM's upfront licence fee.
Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design
services, Fujitsu/Samsung charge two- to three-times more per manufactured wafer.[citation needed ] For low
to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of
the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through
lower wafer pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the
dedicated foundry a better choice.

Architectural licence

[edit]

Companies can also obtain an ARM architectural licence for designing their own CPU cores using the ARM
instruction sets. These cores must comply fully with the ARM architecture.

Cores

[edit]

Main article: List of ARM cores

Architecture Bit
width
ARMv1

Cores designed by ARM Holdings

Cortex
profile

32/26 ARM1

ARMv2

32/26 ARM2, ARM3

ARMv3

32/26 ARM6, ARM7

ARMv4

32/26 ARM8

ARMv4T

Cores
designed
by third
parties

32

Amber,
STORM
Open Soft
Core [27]
StrongARM,
FA526

ARM7TDMI, ARM9TDMI

ARMv5

32

ARM7EJ, ARM9E, ARM10E

ARMv6

32

ARMv6-M

32

ARM11
ARM Cortex-M0, ARM Cortex-M0+,
ARM Cortex-M1

ARMv7-M
ARMv7E-M

32
32

ARMv7-R

32

ARM
ARM
ARM
ARM

Cortex-M3
Cortex-M4, ARM Cortex-M7
Cortex-R4, ARM Cortex-R5,
Cortex-R7

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XScale,
FA626TE,
Feroceon,
PJ1/Mohawk
Microcontroller
Microcontroller
Microcontroller
Real-time

References

ARM architecture - Wikipedia, the free encyclopedia

ARMv7-A

ARMv8-A

32

64/32

ARM
ARM
ARM
ARM

Cortex-A5, ARM Cortex-A7,

Cortex-A8, ARM Cortex-A9,
Cortex-A12, ARM Cortex-A15,
Cortex-A17

ARM Cortex-A53, ARM Cortex-A57,[28]

ARM Cortex-A72 [29]

Krait,
Scorpion,
PJ4/Sheeva,
Apple
A6/A6X
X-Gene,
Nvidia
Project
Denver,
AMD K12,
Apple
A7/A8/A8X,
Cavium
Thunder X

Application

Application

[33][34]

[30][31][32]

ARMv8.1-A
ARMv8-R

64/32 No announcements yet

32

Application

No announcements yet

Real-time

[35][36]

A list of vendors who implement ARM cores in their design (application specific standard products (ASSP),
microprocessor and microcontrollers) is provided by ARM Holdings. [37]

Example applications of ARM cores

[edit]

Main article: List of applications of ARM cores

ARM cores are used in a number of products, particularly PDAs and
smartphones. Some computing examples are the Microsoft Surface,
Apple's iPad and ASUS Eee Pad Transformer tablet computers. Others
include Apple's iPhone smartphone and iPod portable media player,
Canon PowerShot digital cameras, Nintendo DS handheld game consoles
and TomTom turn-by-turn navigation systems.
In 2005, ARM Holdings took part in the development of Manchester
University's computer, SpiNNaker, which used ARM cores to simulate the
human brain.[38]
ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone,
PandaBoard and other single-board computers, because they are very
small, inexpensive and consume very little power.

32-bit architecture

Tronsmart MK908, a Rockchipbased quad-core Android "mini

PC", with a microSD card next to it
for a size comparison

[edit]

See also: Comparison of ARMv7-A cores

The 32-bit ARM architecture, such as ARMv7-A, is the most widely used architecture in mobile devices.[14]
From 1995, the ARM Architecture Reference Manual has been the primary source of documentation on
the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are
required to support (such as instruction semantics) from implementation details that may vary. The

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architecture has evolved over time, and version seven of the architecture, ARMv7, that defines the
architecture for the first of the Cortex series of cores, defines three architecture "profiles":
A-profile, the "Application" profile: Cortex-A series
R-profile, the "Real-time" profile: Cortex-R series
M-profile, the "Microcontroller" profile: Cortex-M series
Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M
architecture (used by the Cortex M0/M0+/M1) as a subset of the ARMv7-M profile with fewer instructions.

CPU modes

[edit]

Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the
implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can
switch modes due to external events (interrupts) or programmatically. [39]

User mode: The only non-privileged mode.

FIQ mode: A privileged mode that is entered whenever the processor accepts an FIQ interrupt.
IRQ mode: A privileged mode that is entered whenever the processor accepts an IRQ interrupt.
Supervisor (svc) mode: A privileged mode entered whenever the CPU is reset or when an SVC
instruction is executed.

Abort mode: A privileged mode that is entered whenever a prefetch abort or data abort exception
occurs.

Undefined mode: A privileged mode that is entered whenever an undefined instruction exception occurs.
System mode (ARMv4 and above): The only privileged mode that is not entered by an exception. It can
only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR.

Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3): A monitor mode is introduced to
support TrustZone extension in ARM cores.

Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2): A hypervisor mode that supports Popek and
Goldberg virtualization requirements for the non-secure operation of the CPU.[40][41]

Instruction set

[edit]

The original (and subsequent) ARM implementation was hardwired without microcode, like the much
simpler 8-bit 6502 processor used in prior Acorn microcomputers.
The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC
features:
Load/store architecture.
No support for unaligned memory accesses in the original version of the architecture. ARMv6 and later,
except some microcontroller versions, support unaligned accesses for half-word and single-word
load/store instructions with some limitations, such as no guaranteed atomicity.[42][43]

Uniform 16 32-bit register file (including the Program Counter, Stack Pointer and the Link Register).

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Fixed instruction width of 32bits to ease decoding and pipelining, at the cost of decreased code density.
Later, the Thumb instruction set added 16-bit instructions and increased code density.
Mostly single clock-cycle execution.
To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020,
some additional design features were used:
Conditional execution of most instructions reduces branch overhead and compensates for the lack of a
branch predictor.
Arithmetic instructions alter condition codes only when desired.
32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and
address calculations.
Has powerful indexed addressing modes.
A link register supports fast leaf function calls.
A simple, but fast, 2-priority-level interrupt subsystem has switched register banks.

Arithmetic instructions

[edit]

ARM includes integer arithmetic operations for add, subtract, and multiply; some versions of the architecture
also support divide operations.
ARM supports 32-bit x 32-bit multiplies with either a 32-bit result or 64-bit result, though Cortex-M0 / M0+
/ M1 cores don't support 64-bit results. [44] Some ARM cores also support 16-bit x 16-bit and 32-bit x 16-bit
multiplies.
The divide instructions are only included in the following ARM architectures:
ARMv7-M and ARMv7E-M architectures always include divide instructions.[45]
ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in
its 32-bit instruction set.[46]

ARMv7-A architecture optionally includes the divide instructions. The instructions might not be
implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and
ARM instruction sets, or implemented if the Virtualization Extensions are included.[46]

Registers

[edit]

Registers R0 through R7 are the same

across all CPU modes; they are never
banked.
R13 and R14 are banked across all
privileged CPU modes except system mode.
That is, each mode that can be entered
because of an exception has its own R13
and R14. These registers generally contain
the stack pointer and the return address
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usr sys

Registers across CPU modes

svc
abt
und
irq
R0
R1
R2
R3
R4
R5
R6
R7

fiq

ARM architecture - Wikipedia, the free encyclopedia

from function calls, respectively.

Aliases:
R13 is also referred to as SP, the Stack
Pointer.
R14 is also referred to as LR, the Link
Register.
R15 is also referred to as PC, the

R13
R14

Program Counter.
The Current Program Status Register
(CPSR) has the following 32bits.[47]

R8
R8_fiq
R9
R9_fiq
R10
R10_fiq
R11
R11_fiq
R12
R12_fiq
R13_svc R13_abt R13_und R13_irq R13_fiq
R14_svc R14_abt R14_und R14_irq R14_fiq
R15
CPSR
SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq

M (bits 04) is the processor mode bits.

T (bit 5) is the Thumb state bit.
F (bit 6) is the FIQ disable bit.
I (bit 7) is the IRQ disable bit.
A (bit 8) is the imprecise data abort disable bit.
E (bit 9) is the data endianness bit.
IT (bits 1015 and 2526) is the if-then state bits.
GE (bits 1619) is the greater-than-or-equal-to bits.
DNM (bits 2023) is the do not modify bits.
J (bit 24) is the Java state bit.
Q (bit 27) is the sticky overflow bit.
V (bit 28) is the overflow bit.
C (bit 29) is the carry/borrow/extend bit.
Z (bit 30) is the zero bit.
N (bit 31) is the negative/less than bit.

Conditional execution

[edit]

Almost every ARM instruction has a conditional execution feature called predication, which is implemented
with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit
codes causes the instruction to be always executed. Most other CPU architectures only have condition codes
on branch instructions.
Though the predicate takes up four of the 32bits in an instruction code, and thus cuts down significantly
on the encoding bits available for displacements in memory access instructions, it avoids branch instructions
when generating code for small if statements. Apart from eliminating the branch instructions themselves,
this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.
The standard example of conditional execution is the subtraction-based Euclidean algorithm:
In the C programming language, the loop is:
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while (i != j)
{
if (i > j)
{
i -= j;
}
else /* i < j (since i != j in while condition) */
{
j -= i;
}
}

In ARM assembly, the loop is:

loop:

CMP

Ri, Rj

SUBGT Ri, Ri, Rj

SUBLT Rj, Rj, Ri
BNE loop

;
;
;
;
;
;

set condition "NE" if (i != j),

"GT" if (i > j),
or "LT" if (i < j)
if "GT" (Greater Than), i = i-j;
if "LT" (Less Than), j = j-i;
if "NE" (Not Equal), then loop

which avoids the branches around the then and else clauses. If Ri and Rj are equal then neither of
the SUB instructions will be executed, eliminating the need for a conditional branch to implement the
while

check at the top of the loop, for example had SUBLE (less than or equal) been used.

One of the ways that Thumb code provides a more dense encoding is to remove the four bit selector from
non-branch instructions.

Other features

[edit]

Another feature of the instruction set is the ability to fold shifts and rotates into the "data processing"
(arithmetic, logical, and register-register move) instructions, so that, for example, the C statement
a += (j << 2);

could be rendered as a single-word, single-cycle instruction: [48]

ADD

Ra, Ra, Rj, LSL #2

This results in the typical ARM program being denser than expected with fewer memory accesses; thus the
pipeline is used more efficiently.
The ARM processor also has features rarely seen in other RISC architectures, such as PC-relative addressing
(indeed, on the 32-bit[1] ARM the PC is one of its 16registers) and pre- and post-increment addressing
modes.
The ARM instruction set has increased over time. Some early ARM processors (before ARM7TDMI), for
example, have no instruction to store a two-byte quantity.

Pipelines and other implementation issues

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The ARM7 and earlier implementations have a three-stage pipeline; the stages being fetch, decode and
execute. Higher-performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen
stages. Additional implementation changes for higher performance include a faster adder and more
extensive branch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example,
was an improved multiplier; hence the added "M".

Coprocessors

[edit]

The ARM architecture (pre-ARMv8) provides a non-intrusive way of extending the instruction set using
"coprocessors" that can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The
coprocessor space is divided logically into 16coprocessors with numbers from 0 to 15, coprocessor15
(cp15) being reserved for some typical control functions like managing the caches and MMU operation on
processors that have one.
In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical
registers into ARM memory space, into the coprocessor space, or by connecting to another device (a bus)
that in turn attaches to the processor. Coprocessor accesses have lower latency, so some peripheralsfor
example an XScale interrupt controllerare accessible in both ways: through memory and through
coprocessors.
In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an
image processing engine might be a small ARM7TDMI core combined with a coprocessor that has
specialised operations to support a specific set of HDTV transcoding primitives.

Debugging

[edit]

This section needs additional citations for verification. Please help

improve this article by adding citations to reliable sources. Unsourced
material may be challenged and removed. (March 2011)
All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform
operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built
using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In
ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an
"EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de
facto debug standard, though not architecturally guaranteed.
The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints,
watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with
EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport
mechanism used to access the debug facilities is not architecturally specified, but implementations generally
include JTAG support.
There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7
processors.

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DSP enhancement instructions

[edit]

To improve the ARM architecture for digital signal processing and multimedia applications, DSP instructions
were added to the set.[49] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ
architectures. E-variants also imply T, D, M and I.
The new instructions are common in digital signal processor architectures. They include variations on signed
multiplyaccumulate, saturated add and subtract, and count leading zeros.

SIMD extensions for multimedia

[edit]

Introduced in ARMv6 architecture and known as NEON.[50]

Jazelle

[edit]

Main article: Jazelle

Jazelle DBX (Direct Bytecode eXecution) is a technique that allows Java Bytecode to be executed directly in
the ARM architecture as a third execution state (and instruction set) alongside the existing ARM and
Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S
and ARM7EJ-S core names. Support for this state is required starting in ARMv6 (except for the ARMv7-M
profile), though newer cores only include a trivial implementation that provides no hardware acceleration.

Thumb

[edit]

To improve compiled code-density, processors since the ARM7TDMI (released in 1994[51]) have featured
the Thumb instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.)
When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a
subset of the ARM instruction set.[52] Most of the Thumb instructions are directly mapped to normal ARM
instructions. The space-saving comes from making some of the instruction operands implicit and limiting the
number of possibilities compared to the ARM instructions executed in the ARM instruction set state.
In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and
many opcodes are restricted to accessing only half of all of the CPU's general-purpose registers. The
shorter opcodes give improved code density overall, even though some operations require extra
instructions. In situations where the memory port or bus width is constrained to less than 32bits, the
shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program
code may need to be loaded into the processor over the constrained memory bandwidth.
Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with
a full 32-bit datapath; the majority is accessed via a 16-bit or narrower secondary datapath. In this
situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPUintensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus
accessible memory.
The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families,
including XScale, have included a Thumb instruction decoder.

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Thumb-2

[edit]

Thumb-2 technology was introduced in the ARM1156core , announced in 2003. Thumb-2 extends the
limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more
breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code
density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory. In ARMv7
this goal can be said to have been met. [citation needed ]
Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional
execution. At the same time, the ARM instruction set was extended to maintain equivalent functionality in
both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or
ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially
as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and
use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on
a tested condition, or on its inverse. When compiling into ARM code, this is ignored, but when compiling
into Thumb it generates an actual instruction. For example:
; if (r0 == r1)
CMP r0, r1
ITE EQ
; ARM: no code ... Thumb: IT instruction
; then r0 = r2;
MOVEQ r0, r2 ; ARM: conditional; Thumb: condition via ITE 'T' (then)
; else r0 = r3;
MOVNE r0, r3 ; ARM: conditional; Thumb: condition via ITE 'E' (else)
; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE"

All ARMv7 chips support the Thumb instruction set. All chips in the Cortex-A series, Cortex-R series, and
ARM11 series support both "ARM instruction set state" and "Thumb instruction set state", while chips in the
Cortex-M series support only the Thumb instruction set.[53][54][55]

Thumb Execution Environment (ThumbEE)

[edit]

ThumbEE (erroneously called Thumb-2EE in some ARM documentation), marketed as Jazelle RCT
(Runtime Compilation Target), was announced in 2005, first appearing in the Cortex-A8 processor.
ThumbEE is a fourth Instruction set state, making small changes to the Thumb-2 extended Thumb
instruction set. These changes make the instruction set particularly suited to code generated at runtime
(e.g. by JIT compilation) in managed Execution Environments . ThumbEE is a target for languages such as
Java, C#, Perl, and Python, and allows JIT compilers to output smaller compiled code without impacting
performance.
New features provided by ThumbEE include automatic null pointer checks on every load and store
instruction, an instruction to perform an array bounds check, and special instructions that call a handler. In
addition, because it utilises Thumb-2 technology, ThumbEE provides access to registers r8-r15 (where the
Jazelle/DBX Java VM state is held).[56] Handlers are small sections of frequently called code, commonly
used to implement high level languages, such as allocating memory for a new object. These changes come
from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE Instruction set state.
On 23 November 2011, ARM Holdings deprecated any use of the ThumbEE instruction set,[57] and ARMv8

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removes support for ThumbEE.

Floating-point (VFP)

[edit]

VFP (Vector Floating Point) technology is an FPU (Floating-Point Unit) coprocessor extension to the ARM
architecture[58] (implemented differently in ARMv8 - coprocessors not defined there). It provides low-cost
single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std
754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for
a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, threedimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP
architecture was intended to support execution of short "vector mode" instructions but these operated on
each vector element sequentially and thus did not offer the performance of true single instruction, multiple
data (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction,[59] to
be replaced with the much more powerful NEON Advanced SIMD unit.
Some devices such as the ARM Cortex-A8 have a cut-down VFPLite module instead of a full VFP module,
and require roughly ten times more clock cycles per float operation.[60] Pre-ARMv8 architecture
implemented floating-point/SIMD with the coprocessor interface. Other floating-point and/or SIMD units
found in ARM-based processors using the coprocessor interface include FPA, FPE, iwMMXt, some of which
where implemented in software by trapping but could have been implemented in hardware. They provide
some of the same functionality as VFP but are not opcode-compatible with it.
VFPv1
Obsolete
VFPv2
An optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures.
VFPv2 has 16 64-bit FPU registers.
VFPv3 or VFPv3-D32
Implemented on the Cortex-A8 and A9 ARMv7 processors. It is backwards compatible with VFPv2,
except that it cannot trap floating-point exceptions. VFPv3 has 32 64-bit FPU registers as standard, adds
VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such
that constants can be loaded into FPU registers.
VFPv3-D16
As above, but with only 16 64-bit FPU registers. Implemented on Cortex-R4 and R5 processors.
VFPv3-F16
Uncommon; it supports IEEE754-2008 half-precision (16-bit) floating point.
VFPv4 or VFPv4-D32
Implemented on the Cortex-A12 and A15 ARMv7 processors, Cortex-A7 optionally has VFPv4-D32 in the
case of an FPU with NEON. [61] VFPv4 has 32 64-bit FPU registers as standard, adds both half-precision

extensions and fused multiply-accumulate instructions to the features of VFPv3.

VFPv4-D16
As above, but it has only 16 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors (in case
of an FPU without NEON[61]).
VFPv5-D16-M

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Implemented on Cortex-M7 when single and double-precision floating point core option exist.
In Debian Linux and derivatives armhf (ARM hard float) refers to the ARMv7 architecture including the
additional VFP3-D16 floating-point hardware extension (and Thumb-2) above.
Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate. [62]

Advanced SIMD (NEON)

[edit]

The Advanced SIMD extension (aka NEON or "MPE" Media Processing Engine) is a combined 64- and 128bit SIMD instruction set that provides standardized acceleration for media and signal processing
applications. NEON is included in all Cortex-A8 devices but is optional in Cortex-A9 devices.[63] NEON can
execute MP3 audio decoding on CPUs running at 10MHz and can run the GSM adaptive multi-rate (AMR)
speech codec at no more than 13MHz. It features a comprehensive instruction set, separate register files
and independent execution hardware. [64] NEON supports 8-, 16-, 32- and 64-bit integer and singleprecision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well
as graphics and gaming processing. In NEON, the SIMD supports up to 16operations at the same time. The
NEON hardware shares the same floating-point registers as used in VFP. Devices such as the ARM CortexA8 and Cortex-A9 support 128-bit vectors but will execute with 64bits at a time,[60] whereas newer CortexA15 devices can execute 128bits at a time.
ProjectNe10
is ARM's first open source project (from its inception). The Ne10 library is a set of common, useful
functions written in both NEON and C (for compatibility). The library was created to allow developers to use
NEON optimizations without learning NEON but it also serves as a set of highly optimized NEON intrinsic
and assembly code examples for common DSP, arithmetic and image processing routines. The code is
available on GitHub .

Security extensions (TrustZone)

[edit]

The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ and later application profile
architectures. It provides a low-cost alternative to adding another dedicated security core to an SoC, by
providing two virtual processors backed by hardware based access control. This lets the application core
switch between two states, referred to as worlds (to reduce confusion with other names for capability
domains), in order to prevent information from leaking from the more trusted world to the less trusted
world. This world switch is generally orthogonal to all other capabilities of the processor, thus each world
can operate independently of the other while using the same core. Memory and peripherals are then made
aware of the operating world of the core and may use this to provide access control to secrets and code on
the device.[65]
Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world,
and smaller security-specialized code in the more trusted world (named TrustZone Software, a TrustZone
optimised version of the Trusted Foundations Software developed by Trusted Logic Mobility
), allowing much tighter digital rights management for controlling the use of media on ARM-based
devices,[66] and preventing any unapproved use of the device. Trusted Foundations Software was acquired
by Gemalto. Giesecke & Devrient developed a rival implementation named Mobicore. In April 2012 ARM

[67][68]

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Gemalto and Giesecke & Devrient combined their TrustZone portfolios into a joint venture Trustonic.
Open Virtualization [69] and T6 [70] are open source implementations of the trusted world architecture for
TrustZone.
In practice, since the specific implementation details of TrustZone are proprietary and have not been
publicly disclosed for review, it is unclear what level of assurance is provided for a given threat
model.[citation needed ]

No-execute page protection

[edit]

As of ARMv6, the ARM architecture supports no-execute page protection, which is referred to as XN, for
eXecute Never .[71]

Large Physical Address Extension

[edit]

The Large Physical Address Extension, which extends the physical address size from 32 bits to 40 bits, was
added to the ARMv7-A architecture in 2011.[72]

ARMv8-R

[edit]

The ARMv8-R sub-architecture, announced after the ARMv8-A, shares some features except that it is not
64-bit.

64/32-bit architecture
ARMv8-A

[edit]

[edit]

Announced in October 2011,[6] ARMv8-A (often called ARMv8 although not all variants are 64-bit such as
ARMv8-R) represents a fundamental change to the ARM architecture. It adds a 64-bit architecture, named
"AArch64", and a new "A64" instruction set. AArch64 provides user-space compatibility with ARMv7-A ISA,
the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named
"A32". The Thumb instruction sets are referred to as "T32" and have no 64-bit counterpart. ARMv8-A allows
32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit
hypervisor.[1] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[28] Apple was
the first to release an ARMv8-A compatible core (Apple A7) in a consumer product (iPhone 5S).
AppliedMicro, using an FPGA, was the first to demo ARMv8-A. [73] The first ARMv8-A SoC from Samsung is
the Exynos 5433 in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores
in a big.LITTLE configuration; but it will run only in AArch32 mode. [74]
To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD (NEON) standard. It also
adds cryptography instructions supporting AES and SHA-1/SHA-256.

ARMv8.1-A

[edit]

In December 2014, ARMv8.1-A, [75] an update with "incremental benefits over v8.0", was announced. The
enhancements fall into two categories:

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Changes to the instruction set

Changes to the exception model and memory translation
Expected "product introductions mid-2015" with server CPU makers likely to adopt and Apple "will likely
jump to the new architecture". [76] "The incremental updates in ARMv8.1-A revolve around memory
addressing, security, virtualization and throughput. ARMv8-A code will run on v8.1 cores."

AArch64 features

[edit]

New instruction set, A64

Has 31 general-purpose 64-bit registers.
Has dedicated SP or zero register.
The program counter (PC) is no longer accessible as a register
Instructions are still 32bits long and mostly the same as A32 (with LDM/STM instructions and most
conditional execution dropped).
Has paired loads/stores (in place of LDM/STM).
No predication for most instructions (except branches).
Most instructions can take 32-bit or 64-bit arguments.
Addresses assumed to be 64-bit.
Advanced SIMD (NEON) enhanced
Has 32 128-bit registers (up from 16), also accessible via VFPv4.
Supports double-precision floating point.
Fully IEEE 754 compliant.
AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
A new exception system
Fewer banked registers and modes.
Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension
(LPAE), which was designed to be easily extended to 64-bit.

Operating system support

32-bit operating systems

[edit]

[edit]

Historical operating systems

The first ARM-based personal computer, the Acorn Archimedes, ran an
interim operating system called Arthur, which evolved into RISC OS, used
on later ARM-based systems from Acorn and other vendors. Some Acorn
machines also had a Unix port called RISC iX.
Embedded operating systems
The ARM architecture is supported by a large number of embedded and
real-time operating systems, including Linux, Windows CE, Symbian,
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ChibiOS/RT, FreeRTOS, eCos, Integrity, Nucleus PLUS, MicroC/OS-II,

PikeOS,[77] QNX, RTEMS, RTXC Quadros, ThreadX, VxWorks, DRYOS, MQX,

T-Kernel, OSE, SCIOPTA,[78] OS-9[79] and RISC OS.

Mobile device operating systems

The ARM architecture is the primary hardware environment for most mobile
device operating systems such as iOS, Android, Windows Phone, Windows
RT, Bada, Blackberry OS/Blackberry 10, MeeGo, Firefox OS, Tizen, Ubuntu
Touch, Sailfish and webOS.

Android, a popular
operating system running
on the ARM architecture

Desktop/server operating systems

The ARM architecture is supported by RISC OS and multiple Unix-like operating systems including BSD
(NetBSD, FreeBSD), OpenSolaris[80] and various Linux distributions such as Ubuntu and Chrome OS.

64-bit operating systems

[edit]

Mobile device operating systems

iOS 7 and later, on 64-bit Apple SoCs, have ARMv8-A application support.
Android supports ARMv8-A in Android Lollipop (5.0) and later
Desktop/server operating systems
Support for ARMv8-A was merged into the Linux kernel version 3.7 in late 2012.[81] ARMv8-A is

supported by a number of Linux distributions, such as Debian,[82][83] Fedora,[84] openSUSE.[85]

Windows applications can be recompiled to run on 32-bit or 64-bit ARM in Linux with Winelib.[86][87]

See also

[edit]

ARM big.LITTLE ARM's heterogeneous computing architecture

ARM Accredited Engineer certification program
ARMulator
Amber (processor core) an open-source ARM-compatible processor core
AMULET microprocessor an asynchronous implementation of the ARM architecture
Unicore a 32-register architecture based heavily on a 32-bit ARM

Further reading

[edit]

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Electronics portal

ARM architecture - Wikipedia, the free encyclopedia

Assembly Language Programming: ARM Cortex-M3 ; 1st Edition; Vincent Mahout; Wiley-ISTE; 256
pages; 2012; ISBN 978-1848213296.

The Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors; 3rd Edition; Joseph Yiu; Newnes;
600 pages; 2013; ISBN 978-0124080829.

The Definitive Guide to the ARM Cortex-M3 ; 2nd Edition; Joseph Yiu; Newnes; 480 pages; 2009; ISBN
978-1-85617-963-8. (Online Sample)

The Definitive Guide to the ARM Cortex-M0 ; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN

978-0-12-385477-3. (Online Sample)

An Introduction To Reverse Engineering for Beginners" including ARM assembly ; Dennis Yurichev; online
book

.
ARM University Video introduction

External links

; YouTube.

[edit]

Official website

, ARM Ltd.
ARM Virtualization Extensions
Quick Reference Cards
Instructions: Thumb
Opcodes: Thumb

References

Wikimedia Commons has

media related to ARM
microprocessors.

, ARM and Thumb-2 , Vector Floating Point

, Thumb , ARM , ARM , GNU Assembler Directives

[edit]

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Retrieved 25 May 2007.

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